Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.flash_ctrl__prim_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	161599	1			T15	522		T16	22		T17	9
values[2]	4724	1			T15	69		T38	3		T61	2
values[3]	2097	1			T15	28		T62	1		T92	75
values[4]	1391	1			T15	7		T92	76		T96	9
values[5]	1102	1			T15	5		T92	53		T206	9
values[6]	875	1			T15	5		T92	27		T70	3
values[7]	794	1			T92	16		T70	4		T279	2
values[8]	743	1			T92	4		T70	4		T279	2
values[9]	626	1			T92	2		T70	2		T279	3
values[10]	620	1			T92	5		T70	11		T279	12
values[11]	544	1			T92	5		T70	14		T279	15
values[12]	547	1			T92	4		T70	17		T279	16
values[13]	455	1			T92	3		T70	5		T279	8
values[14]	485	1			T92	4		T70	8		T279	14
values[15]	427	1			T92	5		T70	5		T279	7
values[16]	330	1			T92	4		T70	4		T279	3
values[17]	324	1			T92	3		T70	14		T279	1
values[18]	338	1			T92	3		T70	6		T279	2
values[19]	346	1			T92	1		T70	6		T279	3
values[20]	333	1			T92	2		T70	13		T279	12
values[21]	257	1			T92	3		T70	12		T279	1
values[22]	210	1			T92	2		T70	19		T279	2
values[23]	227	1			T92	1		T70	19		T279	1
values[24]	216	1			T92	5		T70	12		T279	3
values[25]	180	1			T92	7		T279	4		T128	3
values[26]	222	1			T92	3		T279	19		T128	6
values[27]	238	1			T92	3		T279	26		T128	5
values[28]	264	1			T92	3		T279	26		T128	8
values[29]	304	1			T92	3		T279	34		T128	3
values[30]	241	1			T92	2		T279	38		T128	3
values[31]	227	1			T92	2		T279	42		T128	7
values[32]	205	1			T92	3		T279	14		T128	6
values[33]	191	1			T92	2		T279	10		T128	4
values[34]	186	1			T92	1		T279	16		T128	2
values[35]	197	1			T92	1		T279	27		T128	5
values[36]	194	1			T92	4		T279	33		T128	3
values[37]	179	1			T92	2		T279	21		T128	4
values[38]	154	1			T92	8		T279	7		T128	5
values[39]	154	1			T92	8		T279	7		T128	5
values[40]	157	1			T92	6		T279	5		T128	7
values[41]	119	1			T92	1		T279	7		T128	4
values[42]	104	1			T92	4		T128	5		T129	1
values[43]	107	1			T92	1		T128	6		T129	1
values[44]	116	1			T92	1		T128	6		T129	1
values[45]	112	1			T92	1		T128	3		T129	1
values[46]	138	1			T92	3		T128	4		T129	1
values[47]	117	1			T92	2		T128	3		T129	1
values[48]	95	1			T92	4		T128	5		T129	1
values[49]	86	1			T92	13		T128	6		T129	1
values[50]	82	1			T92	4		T128	5		T129	1
values[51]	75	1			T92	2		T128	7		T129	1
values[52]	102	1			T92	3		T128	6		T129	1
values[53]	95	1			T92	2		T128	8		T129	1
values[54]	62	1			T92	1		T128	5		T129	1
values[55]	64	1			T92	1		T128	7		T129	1
values[56]	69	1			T92	3		T128	5		T129	1
values[57]	75	1			T92	6		T128	7		T129	1
values[58]	69	1			T92	2		T128	8		T129	1
values[59]	50	1			T92	2		T128	2		T129	1
values[60]	53	1			T92	4		T128	2		T129	1
values[61]	68	1			T92	6		T128	5		T129	1
values[62]	63	1			T92	2		T128	6		T129	1
values[63]	57	1			T92	1		T128	7		T129	1
values[64]	59	1			T92	1		T128	4		T129	1
values[65]	64	1			T92	2		T128	7		T129	1
values[66]	69	1			T92	3		T128	6		T129	1
values[67]	71	1			T92	1		T128	6		T129	1
values[68]	60	1			T92	2		T128	4		T129	1
values[69]	66	1			T92	4		T128	5		T129	1
values[70]	65	1			T92	1		T128	4		T129	1
values[71]	63	1			T92	1		T128	3		T129	1
values[72]	69	1			T92	1		T128	7		T129	1
values[73]	67	1			T92	2		T128	7		T129	1
values[74]	78	1			T92	5		T128	6		T129	1
values[75]	69	1			T92	2		T128	4		T129	1
values[76]	75	1			T92	1		T128	3		T129	1
values[77]	83	1			T92	2		T128	7		T129	1
values[78]	69	1			T92	3		T128	4		T129	1
values[79]	73	1			T92	4		T128	4		T129	1
values[80]	57	1			T92	1		T128	4		T129	1
values[81]	67	1			T92	1		T128	7		T129	1
values[82]	72	1			T92	1		T128	12		T129	1
values[83]	68	1			T92	1		T128	10		T129	1
values[84]	74	1			T92	5		T128	10		T129	1
values[85]	68	1			T92	3		T128	5		T129	1
values[86]	75	1			T92	3		T128	4		T129	1
values[87]	78	1			T92	2		T128	6		T129	1
values[88]	82	1			T92	1		T128	3		T129	1
values[89]	64	1			T92	2		T128	4		T129	1
values[90]	76	1			T92	3		T128	6		T129	1
values[91]	78	1			T92	4		T128	5		T129	1
values[92]	84	1			T92	2		T128	5		T129	1
values[93]	71	1			T92	2		T128	4		T129	1
values[94]	78	1			T92	3		T128	7		T129	1
values[95]	93	1			T92	3		T128	12		T129	1
values[96]	81	1			T92	5		T128	6		T129	1
values[97]	77	1			T92	2		T128	4		T129	1
values[98]	84	1			T92	4		T128	4		T129	6
values[99]	79	1			T92	3		T128	7		T129	7
values[100]	83	1			T92	3		T128	11		T129	1
values[101]	93	1			T92	5		T128	9		T129	2
values[102]	84	1			T92	6		T128	4		T129	2
values[103]	97	1			T92	4		T128	5		T129	1
values[104]	93	1			T92	4		T128	3		T129	1
values[105]	86	1			T92	5		T128	3		T129	7
values[106]	76	1			T92	1		T128	4		T129	2
values[107]	85	1			T92	5		T128	14		T129	3
values[108]	93	1			T92	7		T128	8		T129	2
values[109]	85	1			T92	3		T128	7		T129	2
values[110]	89	1			T92	4		T128	4		T129	2
values[111]	99	1			T92	6		T128	6		T129	3
values[112]	98	1			T92	3		T128	10		T129	1
values[113]	84	1			T92	4		T128	5		T129	2
values[114]	94	1			T92	9		T128	8		T129	1
values[115]	95	1			T92	6		T128	7		T129	1
values[116]	113	1			T92	9		T128	7		T129	5
values[117]	116	1			T92	10		T128	6		T129	2
values[118]	111	1			T92	10		T128	10		T129	2
values[119]	117	1			T92	5		T128	5		T129	1
values[120]	121	1			T92	8		T128	14		T129	2
values[121]	106	1			T92	3		T128	9		T129	1
values[122]	122	1			T92	2		T128	13		T129	1
values[123]	146	1			T92	6		T128	12		T129	2
values[124]	232	1			T92	7		T128	20		T129	1
values[125]	454	1			T92	12		T128	72		T129	2
values[126]	1030	1			T92	32		T128	107		T129	7
values[127]	3441	1			T92	7		T128	85		T129	120
values[128]	5662	1			T92	1		T128	5		T129	203