Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.i2c1_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	138800	1			T15	217		T16	20		T17	10
values[2]	9807	1			T15	105		T17	1		T38	5
values[3]	3769	1			T15	93		T52	19		T79	2
values[4]	2283	1			T15	50		T52	4		T92	8
values[5]	1592	1			T15	27		T52	7		T92	2
values[6]	1032	1			T15	14		T52	4		T92	3
values[7]	844	1			T15	15		T52	3		T92	2
values[8]	683	1			T15	1		T52	13		T92	12
values[9]	595	1			T52	5		T92	9		T206	10
values[10]	522	1			T52	8		T92	4		T206	6
values[11]	523	1			T52	8		T92	2		T206	3
values[12]	467	1			T52	6		T92	1		T206	6
values[13]	431	1			T52	5		T92	2		T206	7
values[14]	413	1			T52	8		T92	2		T206	9
values[15]	442	1			T52	10		T92	4		T206	11
values[16]	431	1			T52	8		T92	6		T206	8
values[17]	400	1			T52	4		T92	5		T206	4
values[18]	396	1			T52	7		T92	1		T206	3
values[19]	336	1			T52	3		T92	1		T206	3
values[20]	355	1			T52	5		T92	3		T206	5
values[21]	378	1			T52	4		T92	4		T206	4
values[22]	382	1			T52	5		T92	13		T206	5
values[23]	332	1			T52	6		T92	10		T206	5
values[24]	328	1			T52	4		T92	1		T206	6
values[25]	419	1			T52	5		T92	3		T206	6
values[26]	379	1			T92	2		T206	4		T281	1
values[27]	367	1			T92	6		T206	4		T281	1
values[28]	421	1			T92	2		T206	8		T281	1
values[29]	345	1			T92	2		T206	7		T281	1
values[30]	308	1			T92	5		T206	6		T281	1
values[31]	332	1			T92	2		T206	3		T281	1
values[32]	357	1			T92	5		T206	3		T281	1
values[33]	306	1			T92	1		T206	3		T281	1
values[34]	308	1			T92	2		T206	6		T281	1
values[35]	337	1			T92	3		T206	8		T281	1
values[36]	330	1			T92	1		T206	7		T281	1
values[37]	350	1			T92	5		T206	6		T281	1
values[38]	352	1			T92	5		T206	8		T281	1
values[39]	388	1			T92	5		T206	4		T281	1
values[40]	298	1			T92	7		T206	6		T281	1
values[41]	347	1			T92	3		T206	4		T281	1
values[42]	324	1			T92	1		T206	3		T281	1
values[43]	335	1			T92	1		T206	7		T281	1
values[44]	335	1			T92	2		T206	8		T281	1
values[45]	316	1			T92	1		T206	4		T281	1
values[46]	316	1			T92	6		T206	8		T281	1
values[47]	344	1			T92	2		T206	5		T281	1
values[48]	275	1			T92	2		T206	4		T281	1
values[49]	309	1			T92	1		T206	4		T281	1
values[50]	302	1			T92	2		T206	6		T281	1
values[51]	325	1			T92	2		T206	4		T281	1
values[52]	326	1			T92	2		T206	5		T281	1
values[53]	271	1			T92	1		T206	4		T281	1
values[54]	305	1			T92	1		T206	4		T281	1
values[55]	312	1			T92	2		T206	8		T281	1
values[56]	339	1			T92	3		T206	4		T281	1
values[57]	368	1			T92	1		T206	5		T281	1
values[58]	340	1			T92	3		T206	7		T281	1
values[59]	306	1			T92	4		T206	5		T281	1
values[60]	237	1			T92	1		T206	2		T281	1
values[61]	255	1			T92	1		T206	3		T281	1
values[62]	291	1			T92	2		T206	6		T281	1
values[63]	242	1			T92	1		T206	8		T281	1
values[64]	252	1			T92	4		T206	5		T281	1
values[65]	223	1			T92	3		T206	6		T281	1
values[66]	188	1			T92	1		T206	10		T281	1
values[67]	198	1			T92	2		T206	8		T281	1
values[68]	167	1			T92	1		T206	10		T281	1
values[69]	174	1			T92	3		T206	12		T281	1
values[70]	157	1			T92	2		T206	7		T281	1
values[71]	185	1			T92	2		T206	3		T281	1
values[72]	162	1			T92	6		T206	4		T281	1
values[73]	166	1			T92	5		T206	7		T281	1
values[74]	135	1			T92	1		T206	5		T281	1
values[75]	141	1			T92	6		T206	4		T281	1
values[76]	157	1			T92	3		T206	8		T281	1
values[77]	108	1			T92	3		T206	8		T281	1
values[78]	96	1			T92	6		T206	10		T281	1
values[79]	90	1			T92	4		T206	5		T281	1
values[80]	97	1			T92	2		T206	3		T281	1
values[81]	91	1			T92	2		T206	8		T281	1
values[82]	119	1			T92	1		T206	12		T281	1
values[83]	104	1			T92	1		T206	4		T281	1
values[84]	92	1			T92	1		T206	8		T281	1
values[85]	89	1			T92	1		T206	7		T281	1
values[86]	111	1			T92	3		T206	6		T281	1
values[87]	94	1			T92	1		T206	5		T281	1
values[88]	113	1			T92	2		T206	5		T281	1
values[89]	118	1			T92	3		T206	12		T281	1
values[90]	116	1			T92	4		T206	7		T281	1
values[91]	111	1			T92	4		T206	8		T281	1
values[92]	107	1			T92	1		T206	4		T281	1
values[93]	105	1			T92	1		T206	2		T281	2
values[94]	122	1			T92	2		T206	3		T281	1
values[95]	123	1			T92	1		T206	9		T281	3
values[96]	124	1			T92	2		T206	7		T281	1
values[97]	124	1			T92	3		T206	5		T281	9
values[98]	107	1			T92	4		T206	7		T281	1
values[99]	94	1			T92	2		T206	8		T281	1
values[100]	89	1			T92	3		T206	4		T281	1
values[101]	94	1			T92	2		T206	11		T281	1
values[102]	87	1			T92	2		T206	14		T281	2
values[103]	102	1			T92	1		T206	7		T281	9
values[104]	122	1			T92	3		T206	9		T281	3
values[105]	140	1			T92	6		T206	6		T281	1
values[106]	120	1			T92	6		T206	8		T281	5
values[107]	115	1			T92	7		T206	7		T281	2
values[108]	114	1			T92	1		T206	8		T281	1
values[109]	115	1			T92	6		T206	8		T281	3
values[110]	86	1			T92	3		T206	6		T281	2
values[111]	91	1			T92	2		T206	7		T281	7
values[112]	100	1			T92	2		T206	5		T281	1
values[113]	87	1			T92	2		T206	4		T281	1
values[114]	109	1			T92	6		T206	4		T281	2
values[115]	124	1			T92	4		T206	3		T281	2
values[116]	107	1			T92	8		T206	3		T281	2
values[117]	92	1			T92	3		T206	2		T281	2
values[118]	106	1			T92	1		T206	4		T281	3
values[119]	108	1			T92	3		T206	4		T281	4
values[120]	91	1			T92	2		T206	8		T281	1
values[121]	96	1			T92	1		T206	8		T281	1
values[122]	80	1			T92	3		T206	5		T281	4
values[123]	99	1			T92	3		T206	6		T281	5
values[124]	97	1			T92	2		T206	6		T281	2
values[125]	134	1			T92	5		T206	6		T281	1
values[126]	268	1			T92	16		T206	8		T281	1
values[127]	1161	1			T92	59		T206	42		T281	26
values[128]	7960	1			T92	29		T206	19		T281	271