Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.edn0_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	165141	1			T15	143		T16	21		T17	4
values[2]	5134	1			T18	1		T38	5		T91	1
values[3]	2668	1			T72	70		T92	48		T84	54
values[4]	1748	1			T72	44		T92	15		T84	49
values[5]	1140	1			T72	27		T92	10		T84	34
values[6]	796	1			T72	28		T92	5		T84	15
values[7]	737	1			T72	23		T92	2		T84	14
values[8]	673	1			T72	27		T92	1		T84	37
values[9]	669	1			T72	29		T92	4		T84	45
values[10]	697	1			T72	39		T92	6		T84	28
values[11]	645	1			T72	40		T92	12		T84	29
values[12]	576	1			T72	36		T92	8		T84	26
values[13]	508	1			T72	36		T92	5		T84	8
values[14]	487	1			T72	31		T84	13		T96	26
values[15]	404	1			T72	27		T84	15		T96	16
values[16]	354	1			T72	16		T84	20		T96	11
values[17]	357	1			T72	3		T84	11		T96	12
values[18]	354	1			T84	16		T96	10		T206	4
values[19]	331	1			T84	14		T96	8		T80	1
values[20]	297	1			T84	10		T96	10		T80	1
values[21]	234	1			T84	9		T96	7		T80	1
values[22]	251	1			T84	13		T96	7		T80	1
values[23]	266	1			T84	11		T96	3		T80	1
values[24]	265	1			T84	7		T96	3		T80	1
values[25]	212	1			T84	1		T96	4		T80	1
values[26]	200	1			T96	9		T80	1		T282	1
values[27]	161	1			T96	9		T80	1		T282	1
values[28]	142	1			T96	8		T80	1		T282	1
values[29]	143	1			T96	9		T80	1		T282	1
values[30]	148	1			T96	24		T80	1		T282	1
values[31]	101	1			T96	5		T80	1		T282	1
values[32]	81	1			T96	5		T80	1		T282	1
values[33]	94	1			T96	6		T80	1		T282	1
values[34]	97	1			T96	2		T80	1		T282	1
values[35]	130	1			T80	1		T282	1		T283	1
values[36]	79	1			T80	1		T282	1		T283	1
values[37]	75	1			T80	1		T282	1		T283	1
values[38]	92	1			T80	1		T282	1		T283	1
values[39]	80	1			T80	1		T282	1		T283	1
values[40]	80	1			T80	1		T282	1		T283	1
values[41]	89	1			T80	1		T282	1		T283	1
values[42]	96	1			T80	1		T282	1		T283	1
values[43]	85	1			T80	1		T282	1		T283	1
values[44]	90	1			T80	1		T282	1		T283	1
values[45]	67	1			T80	1		T282	1		T283	2
values[46]	66	1			T80	1		T282	1		T283	1
values[47]	57	1			T80	1		T282	1		T283	1
values[48]	46	1			T80	1		T282	1		T283	1
values[49]	53	1			T80	1		T282	1		T283	1
values[50]	48	1			T80	1		T282	1		T283	1
values[51]	49	1			T80	1		T282	1		T283	1
values[52]	53	1			T80	1		T282	1		T283	1
values[53]	57	1			T80	1		T282	1		T283	1
values[54]	56	1			T80	1		T282	1		T283	1
values[55]	51	1			T80	1		T282	1		T283	1
values[56]	55	1			T80	1		T282	1		T283	1
values[57]	53	1			T80	1		T282	1		T283	1
values[58]	61	1			T80	1		T282	1		T283	1
values[59]	47	1			T80	1		T282	1		T283	1
values[60]	63	1			T80	1		T282	2		T283	1
values[61]	57	1			T80	1		T282	1		T283	1
values[62]	50	1			T80	1		T282	1		T283	1
values[63]	49	1			T80	1		T282	1		T283	1
values[64]	63	1			T80	1		T282	1		T283	1
values[65]	50	1			T80	1		T282	1		T283	1
values[66]	59	1			T80	1		T282	1		T283	1
values[67]	54	1			T80	1		T282	1		T283	1
values[68]	53	1			T80	1		T282	1		T283	1
values[69]	54	1			T80	1		T282	1		T283	1
values[70]	54	1			T80	1		T282	1		T283	1
values[71]	65	1			T80	1		T282	1		T283	1
values[72]	55	1			T80	1		T282	1		T283	1
values[73]	65	1			T80	1		T282	1		T283	1
values[74]	71	1			T80	1		T282	2		T283	1
values[75]	54	1			T80	1		T282	1		T283	1
values[76]	49	1			T80	1		T282	1		T283	1
values[77]	54	1			T80	1		T282	1		T283	1
values[78]	54	1			T80	1		T282	1		T283	1
values[79]	56	1			T80	1		T282	1		T283	1
values[80]	64	1			T80	1		T282	1		T283	1
values[81]	54	1			T80	1		T282	1		T283	1
values[82]	58	1			T80	1		T282	1		T283	1
values[83]	58	1			T80	1		T282	1		T283	1
values[84]	64	1			T80	1		T282	1		T283	1
values[85]	66	1			T80	1		T282	1		T283	1
values[86]	66	1			T80	1		T282	1		T283	1
values[87]	72	1			T80	1		T282	1		T283	1
values[88]	58	1			T80	1		T282	1		T283	1
values[89]	55	1			T80	1		T282	1		T283	1
values[90]	60	1			T80	1		T282	1		T283	1
values[91]	57	1			T80	1		T282	1		T283	1
values[92]	72	1			T80	1		T282	1		T283	1
values[93]	58	1			T80	1		T282	1		T283	1
values[94]	51	1			T80	1		T282	1		T283	1
values[95]	69	1			T80	1		T282	1		T283	1
values[96]	79	1			T80	1		T282	1		T283	1
values[97]	68	1			T80	1		T282	1		T283	1
values[98]	87	1			T80	1		T282	1		T283	2
values[99]	70	1			T80	1		T282	1		T283	1
values[100]	96	1			T80	6		T282	1		T283	1
values[101]	83	1			T80	5		T282	1		T283	1
values[102]	85	1			T80	3		T282	1		T283	1
values[103]	79	1			T80	1		T282	1		T283	6
values[104]	90	1			T80	3		T282	1		T283	1
values[105]	76	1			T80	4		T282	1		T283	2
values[106]	87	1			T80	1		T282	1		T283	2
values[107]	90	1			T80	1		T282	1		T283	1
values[108]	97	1			T80	1		T282	1		T283	2
values[109]	81	1			T80	2		T282	1		T283	1
values[110]	96	1			T80	1		T282	1		T283	1
values[111]	97	1			T80	1		T282	1		T283	1
values[112]	98	1			T80	1		T282	1		T283	1
values[113]	95	1			T80	1		T282	1		T283	2
values[114]	103	1			T80	1		T282	1		T283	1
values[115]	109	1			T80	3		T282	1		T283	2
values[116]	109	1			T80	1		T282	1		T283	5
values[117]	100	1			T80	1		T282	1		T283	2
values[118]	109	1			T80	4		T282	1		T283	1
values[119]	85	1			T80	1		T282	1		T283	2
values[120]	100	1			T80	1		T282	3		T283	1
values[121]	114	1			T80	1		T282	3		T283	1
values[122]	123	1			T80	1		T282	2		T283	1
values[123]	125	1			T80	2		T282	4		T283	1
values[124]	212	1			T80	2		T282	3		T283	2
values[125]	351	1			T80	3		T282	2		T283	1
values[126]	928	1			T80	13		T282	22		T283	12
values[127]	3716	1			T80	98		T282	142		T283	103
values[128]	6512	1			T80	169		T282	267		T283	194