Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	502	1			T15	3		T98	4		T291	3
all_values[1]	492	1			T14	1		T15	1		T38	2
all_values[2]	479	1			T15	4		T38	2		T98	3
all_values[3]	480	1			T15	3		T98	3		T291	6
all_values[4]	470	1			T15	2		T38	2		T98	1
all_values[5]	474	1			T15	3		T98	3		T291	4
all_values[6]	494	1			T15	3		T38	1		T98	2
all_values[7]	504	1			T14	1		T15	3		T38	3
all_values[8]	493	1			T15	3		T98	1		T291	2
all_values[9]	493	1			T14	1		T15	7		T98	1
all_values[10]	482	1			T15	3		T38	1		T52	1
all_values[11]	548	1			T14	2		T15	3		T98	2
all_values[12]	526	1			T14	1		T15	5		T38	1
all_values[13]	508	1			T15	2		T52	1		T98	4
all_values[14]	479	1			T14	1		T15	1		T98	3
all_values[15]	477	1			T15	2		T98	6		T72	1
all_values[16]	505	1			T15	1		T38	1		T98	1
all_values[17]	464	1			T14	4		T15	5		T98	1
all_values[18]	481	1			T14	1		T15	3		T38	1
all_values[19]	489	1			T15	4		T38	1		T52	1
all_values[20]	472	1			T15	2		T38	1		T52	1
all_values[21]	505	1			T15	2		T98	2		T291	1
all_values[22]	514	1			T15	2		T38	2		T98	1
all_values[23]	469	1			T15	2		T38	1		T98	1
all_values[24]	450	1			T15	1		T52	1		T98	7
all_values[25]	495	1			T15	1		T98	3		T291	1
all_values[26]	544	1			T15	7		T38	2		T98	5
all_values[27]	461	1			T15	5		T52	1		T98	2
all_values[28]	481	1			T15	1		T52	1		T98	3
all_values[29]	493	1			T15	2		T38	1		T52	1
all_values[30]	492	1			T15	2		T38	1		T52	1
all_values[31]	475	1			T15	2		T52	1		T98	1
all_values[32]	477	1			T14	1		T15	1		T52	1
all_values[33]	482	1			T15	3		T38	1		T98	4
all_values[34]	531	1			T14	1		T15	5		T38	1
all_values[35]	479	1			T15	1		T38	1		T98	4
all_values[36]	469	1			T15	2		T38	1		T98	3
all_values[37]	477	1			T15	3		T98	5		T291	2
all_values[38]	487	1			T14	1		T15	1		T98	8
all_values[39]	497	1			T15	2		T38	2		T98	4
all_values[40]	475	1			T14	1		T15	4		T38	2
all_values[41]	450	1			T14	1		T15	4		T38	2
all_values[42]	479	1			T15	3		T291	2		T208	1
all_values[43]	491	1			T98	3		T291	3		T208	1
all_values[44]	469	1			T14	1		T15	4		T98	2
all_values[45]	478	1			T15	3		T98	3		T208	2
all_values[46]	491	1			T15	3		T38	1		T98	2
all_values[47]	498	1			T15	2		T38	1		T98	2
all_values[48]	489	1			T15	3		T98	5		T291	5
all_values[49]	498	1			T15	3		T38	1		T98	6