Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3476	1			T15	22		T38	5		T52	3
all_values[1]	3505	1			T15	30		T38	7		T52	2
all_values[2]	3465	1			T15	27		T38	10		T52	3
all_values[3]	3565	1			T15	46		T38	4		T98	20
all_values[4]	3520	1			T15	35		T38	5		T52	3
all_values[5]	3549	1			T15	31		T38	5		T52	2
all_values[6]	3456	1			T15	32		T38	5		T52	5
all_values[7]	3637	1			T15	35		T38	4		T52	6
all_values[8]	3454	1			T15	28		T38	5		T52	3
all_values[9]	3427	1			T15	29		T38	5		T52	3
all_values[10]	3509	1			T15	39		T38	5		T52	4
all_values[11]	3426	1			T15	26		T38	5		T52	2
all_values[12]	3516	1			T15	30		T38	4		T52	4
all_values[13]	3461	1			T15	32		T38	5		T52	6
all_values[14]	3555	1			T15	26		T38	6		T52	2
all_values[15]	3522	1			T15	34		T38	7		T52	2
all_values[16]	3591	1			T15	23		T38	8		T98	17
all_values[17]	3440	1			T15	32		T38	10		T52	1
all_values[18]	3482	1			T15	37		T38	4		T52	7
all_values[19]	3503	1			T15	34		T38	9		T52	5
all_values[20]	3492	1			T15	33		T38	7		T52	4
all_values[21]	3443	1			T15	34		T38	5		T52	1
all_values[22]	3433	1			T15	28		T38	7		T52	1
all_values[23]	3379	1			T15	25		T38	5		T52	2
all_values[24]	3464	1			T15	27		T38	6		T52	6
all_values[25]	3492	1			T15	36		T38	9		T52	1
all_values[26]	3551	1			T15	30		T38	5		T52	4
all_values[27]	3553	1			T15	26		T38	2		T52	1
all_values[28]	3496	1			T15	25		T38	9		T52	2
all_values[29]	3401	1			T15	37		T38	4		T52	3
all_values[30]	3532	1			T15	34		T38	6		T52	2
all_values[31]	3484	1			T15	18		T38	7		T52	4
all_values[32]	3453	1			T15	35		T38	7		T52	5
all_values[33]	3430	1			T15	33		T38	8		T52	2
all_values[34]	3558	1			T15	24		T38	14		T52	1
all_values[35]	3561	1			T15	27		T38	6		T52	7
all_values[36]	3406	1			T15	33		T38	8		T52	4
all_values[37]	3529	1			T15	47		T38	7		T52	1
all_values[38]	3469	1			T15	24		T38	7		T52	4
all_values[39]	3554	1			T15	29		T38	10		T52	2
all_values[40]	3505	1			T15	29		T38	5		T52	4
all_values[41]	3359	1			T15	31		T38	6		T52	1
all_values[42]	3513	1			T15	29		T38	2		T52	5
all_values[43]	3484	1			T15	27		T38	9		T52	3
all_values[44]	3592	1			T15	23		T38	5		T52	2
all_values[45]	3552	1			T15	26		T38	4		T98	15
all_values[46]	3520	1			T15	30		T38	5		T52	2
all_values[47]	3474	1			T15	35		T38	5		T52	1
all_values[48]	3444	1			T15	18		T38	6		T52	2
all_values[49]	3450	1			T15	41		T38	4		T52	5
all_values[50]	3578	1			T15	43		T38	8		T52	1
all_values[51]	3453	1			T15	20		T38	9		T98	22
all_values[52]	3417	1			T15	22		T38	7		T98	16
all_values[53]	3499	1			T15	23		T38	5		T52	1
all_values[54]	3472	1			T15	24		T38	5		T52	2
all_values[55]	3570	1			T15	29		T38	4		T52	1
all_values[56]	3502	1			T15	33		T38	4		T52	4
all_values[57]	3484	1			T15	37		T38	9		T52	3
all_values[58]	3554	1			T15	21		T38	8		T52	3
all_values[59]	3529	1			T15	34		T38	3		T52	6
all_values[60]	3571	1			T15	37		T38	6		T52	1
all_values[61]	3507	1			T15	25		T38	7		T52	6
all_values[62]	3576	1			T15	32		T38	4		T52	2
all_values[63]	3474	1			T15	32		T38	6		T52	1