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 LINE       31976
 SUB-EXPRESSION (addr_hit[261] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T15,T38,T63
1	1	Covered	T38,T61,T63

 LINE       31976
 SUB-EXPRESSION (addr_hit[262] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T38,T11,T94
1	1	Covered	T14,T15,T38

 LINE       31976
 SUB-EXPRESSION (addr_hit[263] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T38,T52,T11
1	1	Covered	T38,T62,T52

 LINE       31976
 SUB-EXPRESSION (addr_hit[264] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T38,T11,T207
1	1	Covered	T14,T38,T61

 LINE       31976
 SUB-EXPRESSION (addr_hit[265] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T15,T38,T61
1	1	Covered	T15,T38,T11

 LINE       31976
 SUB-EXPRESSION (addr_hit[266] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T38,T11,T98
1	1	Covered	T15,T38,T52

 LINE       31976
 SUB-EXPRESSION (addr_hit[267] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T38,T11,T98
1	1	Covered	T15,T38,T52

 LINE       31976
 SUB-EXPRESSION (addr_hit[268] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T15,T11,T98
1	1	Covered	T15,T38,T52

 LINE       31976
 SUB-EXPRESSION (addr_hit[269] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T38,T11,T98
1	1	Covered	T38,T61,T52

 LINE       31976
 SUB-EXPRESSION (addr_hit[270] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T11,T98,T92
1	1	Covered	T14,T15,T38

 LINE       31976
 SUB-EXPRESSION (addr_hit[271] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T61,T11,T98
1	1	Covered	T15,T38,T11

 LINE       31976
 SUB-EXPRESSION (addr_hit[272] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T16,T38,T11
1	1	Covered	T15,T38,T61

 LINE       31976
 SUB-EXPRESSION (addr_hit[273] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T38,T11,T84
1	1	Covered	T38,T52,T11

 LINE       31976
 SUB-EXPRESSION (addr_hit[274] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T14,T38,T11
1	1	Covered	T38,T62,T98

 LINE       31976
 SUB-EXPRESSION (addr_hit[275] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T14,T38,T11
1	1	Covered	T14,T15,T38

 LINE       31976
 SUB-EXPRESSION (addr_hit[276] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T38,T11,T98
1	1	Covered	T14,T38,T11

 LINE       31976
 SUB-EXPRESSION (addr_hit[277] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T38,T11,T98
1	1	Covered	T15,T38,T52

 LINE       31976
 SUB-EXPRESSION (addr_hit[278] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T14,T11,T98
1	1	Covered	T15,T38,T52

 LINE       31976
 SUB-EXPRESSION (addr_hit[279] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T38,T61,T84
1	1	Covered	T14,T38,T11

 LINE       31976
 SUB-EXPRESSION (addr_hit[280] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T15,T11,T98
1	1	Covered	T14,T15,T38

 LINE       31976
 SUB-EXPRESSION (addr_hit[281] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T38,T11,T94
1	1	Covered	T15,T38,T11

 LINE       31976
 SUB-EXPRESSION (addr_hit[282] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T38,T11,T98
1	1	Covered	T14,T18,T38

 LINE       31976
 SUB-EXPRESSION (addr_hit[283] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T38,T11,T94
1	1	Covered	T38,T62,T52

 LINE       31976
 SUB-EXPRESSION (addr_hit[284] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T38,T11,T98
1	1	Covered	T38,T11,T98

 LINE       31976
 SUB-EXPRESSION (addr_hit[285] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T15,T38,T11
1	1	Covered	T15,T38,T61

 LINE       31976
 SUB-EXPRESSION (addr_hit[286] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T14,T11,T98
1	1	Covered	T15,T16,T38

 LINE       31976
 SUB-EXPRESSION (addr_hit[287] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T38,T61,T11
1	1	Covered	T15,T38,T11

 LINE       31976
 SUB-EXPRESSION (addr_hit[288] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T14,T38,T11
1	1	Covered	T15,T38,T11

 LINE       31976
 SUB-EXPRESSION (addr_hit[289] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T38,T52,T11
1	1	Covered	T16,T38,T61

 LINE       31976
 SUB-EXPRESSION (addr_hit[290] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T15,T38,T11
1	1	Covered	T14,T16,T38

 LINE       31976
 SUB-EXPRESSION (addr_hit[291] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T38,T11,T84
1	1	Covered	T14,T15,T38

 LINE       31976
 SUB-EXPRESSION (addr_hit[292] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T38,T11,T98
1	1	Covered	T15,T38,T63

 LINE       31976
 SUB-EXPRESSION (addr_hit[293] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T38,T52,T11
1	1	Covered	T38,T61,T11

 LINE       31976
 SUB-EXPRESSION (addr_hit[294] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T15,T38,T11
1	1	Covered	T52,T11,T98

 LINE       31976
 SUB-EXPRESSION (addr_hit[295] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T38,T11,T94
1	1	Covered	T14,T16,T38

 LINE       31976
 SUB-EXPRESSION (addr_hit[296] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T15,T38,T52
1	1	Covered	T38,T61,T11

 LINE       31976
 SUB-EXPRESSION (addr_hit[297] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T38,T52,T98
1	1	Covered	T14,T38,T52

 LINE       31976
 SUB-EXPRESSION (addr_hit[298] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T38,T11,T98
1	1	Covered	T38,T63,T52

 LINE       31976
 SUB-EXPRESSION (addr_hit[299] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T38,T11,T84
1	1	Covered	T38,T52,T11

 LINE       31976
 SUB-EXPRESSION (addr_hit[300] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T15,T38,T11
1	1	Covered	T14,T15,T38

 LINE       31976
 SUB-EXPRESSION (addr_hit[301] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T15,T38,T52
1	1	Covered	T14,T38,T52

 LINE       31976
 SUB-EXPRESSION (addr_hit[302] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T11,T98,T206
1	1	Covered	T16,T38,T11

 LINE       31976
 SUB-EXPRESSION (addr_hit[303] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T15,T38,T62
1	1	Covered	T38,T11,T98

 LINE       31976
 SUB-EXPRESSION (addr_hit[304] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T62,T11,T98
1	1	Covered	T61,T11,T94

 LINE       31976
 SUB-EXPRESSION (addr_hit[305] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T16,T38,T11
1	1	Covered	T14,T16,T38

 LINE       31976
 SUB-EXPRESSION (addr_hit[306] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T15,T38,T11
1	1	Covered	T38,T11,T94

 LINE       31976
 SUB-EXPRESSION (addr_hit[307] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T38,T11,T98
1	1	Covered	T15,T38,T11

 LINE       31976
 SUB-EXPRESSION (addr_hit[308] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T15,T38,T11
1	1	Covered	T14,T38,T61

 LINE       31976
 SUB-EXPRESSION (addr_hit[309] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T15,T38,T52
1	1	Covered	T15,T11,T98

 LINE       31976
 SUB-EXPRESSION (addr_hit[310] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T38,T52,T11
1	1	Covered	T38,T52,T98

 LINE       31976
 SUB-EXPRESSION (addr_hit[311] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T38,T61,T52
1	1	Covered	T15,T38,T61

 LINE       31976
 SUB-EXPRESSION (addr_hit[312] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T38,T52,T11
1	1	Covered	T17,T52,T11

 LINE       31976
 SUB-EXPRESSION (addr_hit[313] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T15,T11,T98
1	1	Covered	T38,T11,T98

 LINE       31976
 SUB-EXPRESSION (addr_hit[314] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T38,T52,T11
1	1	Covered	T38,T11,T98

 LINE       31976
 SUB-EXPRESSION (addr_hit[315] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T38,T11,T72
1	1	Covered	T38,T52,T11

 LINE       31976
 SUB-EXPRESSION (addr_hit[316] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T14,T15,T52
1	1	Covered	T14,T61,T62

 LINE       31976
 SUB-EXPRESSION (addr_hit[317] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T15,T38,T52
1	1	Covered	T38,T62,T11

 LINE       31976
 SUB-EXPRESSION (addr_hit[318] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T38,T61,T11
1	1	Covered	T14,T15,T62

 LINE       31976
 SUB-EXPRESSION (addr_hit[319] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T11,T98,T205
1	1	Covered	T15,T38,T61

 LINE       31976
 SUB-EXPRESSION (addr_hit[320] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T38,T84,T96
1	1	Covered	T14,T38,T52

 LINE       31976
 SUB-EXPRESSION (addr_hit[321] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T15,T38,T11
1	1	Covered	T15,T38,T52

 LINE       31976
 SUB-EXPRESSION (addr_hit[322] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T15,T52,T11
1	1	Covered	T14,T15,T38

 LINE       31976
 SUB-EXPRESSION (addr_hit[323] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T98,T72,T206
1	1	Covered	T15,T38,T11

 LINE       31976
 SUB-EXPRESSION (addr_hit[324] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T11,T98,T208
1	1	Covered	T15,T62,T11

 LINE       31976
 SUB-EXPRESSION (addr_hit[325] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T38,T52,T11
1	1	Covered	T38,T11,T98

 LINE       31976
 SUB-EXPRESSION (addr_hit[326] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T15,T38,T52
1	1	Covered	T14,T15,T38

 LINE       31976
 SUB-EXPRESSION (addr_hit[327] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T15,T52,T11
1	1	Covered	T38,T52,T11

 LINE       31976
 SUB-EXPRESSION (addr_hit[328] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T11,T206,T209
1	1	Covered	T15,T38,T61

 LINE       31976
 SUB-EXPRESSION (addr_hit[329] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T11,T98,T84
1	1	Covered	T38,T52,T11

 LINE       31976
 SUB-EXPRESSION (addr_hit[330] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T15,T52,T98
1	1	Covered	T16,T38,T11

 LINE       31976
 SUB-EXPRESSION (addr_hit[331] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T38,T11,T98
1	1	Covered	T38,T52,T11

 LINE       31976
 SUB-EXPRESSION (addr_hit[332] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T15,T11,T98
1	1	Covered	T14,T15,T38

 LINE       31976
 SUB-EXPRESSION (addr_hit[333] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T38,T11,T98
1	1	Covered	T15,T38,T52

 LINE       31976
 SUB-EXPRESSION (addr_hit[334] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T16,T38,T52
1	1	Covered	T38,T61,T63

 LINE       31976
 SUB-EXPRESSION (addr_hit[335] & ((|(4'b1111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T38,T11,T94
1	1	Covered	T14,T15,T38

 LINE       31976
 SUB-EXPRESSION (addr_hit[336] & ((|(4'b0011 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T15,T38,T11
1	1	Covered	T14,T38,T52

 LINE       31976
 SUB-EXPRESSION (addr_hit[337] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T38,T62,T11
1	1	Covered	T38,T98,T79

 LINE       31976
 SUB-EXPRESSION (addr_hit[338] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T15,T11,T98
1	1	Covered	T14,T38,T61

 LINE       31976
 SUB-EXPRESSION (addr_hit[339] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T38,T62,T11
1	1	Covered	T38,T11,T98

 LINE       31976
 SUB-EXPRESSION (addr_hit[340] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T38,T52,T11
1	1	Covered	T14,T15,T38

 LINE       31976
 SUB-EXPRESSION (addr_hit[341] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T38,T11,T98
1	1	Covered	T38,T11,T98

 LINE       31976
 SUB-EXPRESSION (addr_hit[342] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T15,T38,T11
1	1	Covered	T15,T38,T11

 LINE       31976
 SUB-EXPRESSION (addr_hit[343] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T38,T52,T11
1	1	Covered	T14,T15,T38

 LINE       31976
 SUB-EXPRESSION (addr_hit[344] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T38,T11,T94
1	1	Covered	T38,T61,T11

 LINE       31976
 SUB-EXPRESSION (addr_hit[345] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T15,T52,T11
1	1	Covered	T14,T15,T38

 LINE       31976
 SUB-EXPRESSION (addr_hit[346] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T38,T52,T11
1	1	Covered	T15,T38,T11

 LINE       31976
 SUB-EXPRESSION (addr_hit[347] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T38,T62,T52
1	1	Covered	T15,T61,T91

 LINE       31976
 SUB-EXPRESSION (addr_hit[348] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T15,T38,T11
1	1	Covered	T38,T61,T98

 LINE       31976
 SUB-EXPRESSION (addr_hit[349] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T38,T62,T11
1	1	Covered	T11,T98,T79

 LINE       31976
 SUB-EXPRESSION (addr_hit[350] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T14,T15,T38
1	1	Covered	T15,T98,T72

 LINE       31976
 SUB-EXPRESSION (addr_hit[351] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T14,T15,T98
1	1	Covered	T38,T11,T98

 LINE       31976
 SUB-EXPRESSION (addr_hit[352] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T14,T15,T38
1	1	Covered	T38,T98,T72

 LINE       31976
 SUB-EXPRESSION (addr_hit[353] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T38,T62,T52
1	1	Covered	T15,T38,T62

 LINE       31976
 SUB-EXPRESSION (addr_hit[354] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T14,T38,T11
1	1	Covered	T15,T38,T61

 LINE       31976
 SUB-EXPRESSION (addr_hit[355] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T38,T61,T52
1	1	Covered	T38,T62,T52

 LINE       31976
 SUB-EXPRESSION (addr_hit[356] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T15,T38,T11
1	1	Covered	T38,T61,T52

 LINE       31976
 SUB-EXPRESSION (addr_hit[357] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T38,T52,T11
1	1	Covered	T38,T11,T98

 LINE       31976
 SUB-EXPRESSION (addr_hit[358] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T14,T38,T62
1	1	Covered	T14,T15,T38

 LINE       31976
 SUB-EXPRESSION (addr_hit[359] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T17,T38,T11
1	1	Covered	T38,T61,T98

 LINE       31976
 SUB-EXPRESSION (addr_hit[360] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T38,T11,T94
1	1	Covered	T38,T91,T11

 LINE       31976
 SUB-EXPRESSION (addr_hit[361] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T38,T52,T11
1	1	Covered	T38,T94,T98

 LINE       31976
 SUB-EXPRESSION (addr_hit[362] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T15,T38,T11
1	1	Covered	T11,T98,T95

 LINE       31976
 SUB-EXPRESSION (addr_hit[363] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T38,T52,T11
1	1	Covered	T14,T38,T11

 LINE       31976
 SUB-EXPRESSION (addr_hit[364] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T15,T17,T38
1	1	Covered	T38,T94,T98

 LINE       31976
 SUB-EXPRESSION (addr_hit[365] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T38,T52,T11
1	1	Covered	T14,T38,T61

 LINE       31976
 SUB-EXPRESSION (addr_hit[366] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T14,T38,T52
1	1	Covered	T38,T62,T11

 LINE       31976
 SUB-EXPRESSION (addr_hit[367] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T38,T52,T11
1	1	Covered	T38,T52,T94

 LINE       31976
 SUB-EXPRESSION (addr_hit[368] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T38,T52,T11
1	1	Covered	T38,T62,T52

 LINE       31976
 SUB-EXPRESSION (addr_hit[369] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T38,T98,T72
1	1	Covered	T15,T38,T52

 LINE       31976
 SUB-EXPRESSION (addr_hit[370] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T38,T11,T98
1	1	Covered	T38,T98,T72

 LINE       31976
 SUB-EXPRESSION (addr_hit[371] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T38,T11,T94
1	1	Covered	T15,T38,T62

 LINE       31976
 SUB-EXPRESSION (addr_hit[372] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T38,T11,T98
1	1	Covered	T14,T15,T38

 LINE       31976
 SUB-EXPRESSION (addr_hit[373] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T15,T38,T52
1	1	Covered	T62,T98,T95

 LINE       31976
 SUB-EXPRESSION (addr_hit[374] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T38,T52,T98
1	1	Covered	T38,T52,T11

 LINE       31976
 SUB-EXPRESSION (addr_hit[375] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T15,T38,T61
1	1	Covered	T15,T38,T61

 LINE       31976
 SUB-EXPRESSION (addr_hit[376] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T38,T11,T98
1	1	Covered	T14,T38,T52

 LINE       31976
 SUB-EXPRESSION (addr_hit[377] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T11,T98,T207
1	1	Covered	T38,T98,T205

 LINE       31976
 SUB-EXPRESSION (addr_hit[378] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T38,T11,T98
1	1	Covered	T17,T38,T52

 LINE       31976
 SUB-EXPRESSION (addr_hit[379] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T15,T38,T52
1	1	Covered	T38,T11,T94

 LINE       31976
 SUB-EXPRESSION (addr_hit[380] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T38,T52,T11
1	1	Covered	T14,T15,T38

 LINE       31976
 SUB-EXPRESSION (addr_hit[381] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T52,T11,T98
1	1	Covered	T15,T38,T63

 LINE       31976
 SUB-EXPRESSION (addr_hit[382] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T38,T52,T11
1	1	Covered	T98,T72,T12

 LINE       31976
 SUB-EXPRESSION (addr_hit[383] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T38,T52,T11
1	1	Covered	T14,T38,T11

 LINE       31976
 SUB-EXPRESSION (addr_hit[384] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T14,T38,T52
1	1	Covered	T38,T11,T12

 LINE       31976
 SUB-EXPRESSION (addr_hit[385] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T15,T38,T11
1	1	Covered	T14,T15,T38

 LINE       31976
 SUB-EXPRESSION (addr_hit[386] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T15,T16,T38
1	1	Covered	T15,T38,T98

 LINE       31976
 SUB-EXPRESSION (addr_hit[387] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T52,T98,T92
1	1	Covered	T15,T38,T61

 LINE       31976
 SUB-EXPRESSION (addr_hit[388] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T38,T11,T98
1	1	Covered	T15,T38,T52

 LINE       31976
 SUB-EXPRESSION (addr_hit[389] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T15,T11,T98
1	1	Covered	T14,T15,T38

 LINE       31976
 SUB-EXPRESSION (addr_hit[390] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T15,T38,T52
1	1	Covered	T38,T61,T94