Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1065252	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1776179

1

T1

24924

T2

129

T3

115

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2209688	1			T1	12492		T2	34		T3	19
values[0x0]	301241	1			T1	6215		T2	117		T3	92
values[0x1]	330502	1			T1	6217		T2	1505		T3	860

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	790260	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2051171

1

T1

24924

T2

1168

T3

683

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	43807	1			T1	396		T2	25		T3	10
valid_sources[0x01]	44681	1			T1	374		T2	27		T3	19
valid_sources[0x02]	44977	1			T1	387		T2	31		T3	12
valid_sources[0x03]	44012	1			T1	421		T2	26		T3	29
valid_sources[0x04]	44153	1			T1	397		T2	27		T3	8
valid_sources[0x05]	45006	1			T1	393		T2	19		T3	17
valid_sources[0x06]	43951	1			T1	372		T2	26		T3	16
valid_sources[0x07]	44840	1			T1	370		T2	27		T3	20
valid_sources[0x08]	43042	1			T1	378		T2	25		T3	14
valid_sources[0x09]	44308	1			T1	469		T2	27		T3	19
valid_sources[0x0a]	44655	1			T1	370		T2	22		T3	17
valid_sources[0x0b]	45162	1			T1	395		T2	32		T3	7
valid_sources[0x0c]	44659	1			T1	389		T2	33		T3	19
valid_sources[0x0d]	44548	1			T1	391		T2	27		T3	30
valid_sources[0x0e]	44564	1			T1	392		T2	27		T3	5
valid_sources[0x0f]	43651	1			T1	432		T2	19		T3	10
valid_sources[0x10]	45886	1			T1	371		T2	14		T3	15
valid_sources[0x11]	44558	1			T1	375		T2	18		T3	18
valid_sources[0x12]	45014	1			T1	394		T2	27		T3	14
valid_sources[0x13]	44960	1			T1	387		T2	27		T3	13
valid_sources[0x14]	44792	1			T1	432		T2	32		T3	27
valid_sources[0x15]	44880	1			T1	392		T2	25		T3	17
valid_sources[0x16]	43651	1			T1	415		T2	20		T3	13
valid_sources[0x17]	44008	1			T1	382		T2	23		T3	11
valid_sources[0x18]	44604	1			T1	376		T2	25		T3	12
valid_sources[0x19]	44280	1			T1	368		T2	22		T3	13
valid_sources[0x1a]	44879	1			T1	381		T2	24		T3	10
valid_sources[0x1b]	44858	1			T1	377		T2	15		T3	12
valid_sources[0x1c]	45907	1			T1	385		T2	23		T3	15
valid_sources[0x1d]	44292	1			T1	390		T2	30		T3	11
valid_sources[0x1e]	44174	1			T1	407		T2	21		T3	4
valid_sources[0x1f]	45132	1			T1	377		T2	24		T3	15
valid_sources[0x20]	44216	1			T1	383		T2	23		T3	12

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1275442

1

T1

12492

T2

24

T3

15

values[0x0]

all_enables

biggest_size

257964

1

T1

6215

T2

50

T3

54

values[0x1]

all_enables

biggest_size

242773

1

T1

6217

T2

55

T3

46

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2942984	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

465091

1

T7

41

T4

215

T5

56

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1152385	1			T7	106		T4	527		T5	242
values[0x0]	1101559	1			T7	109		T4	504		T5	60
values[0x1]	1154131	1			T7	84		T4	511		T5	244

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2278707	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1129368

1

T7

93

T4

503

T5

212

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	52936	1			T7	7		T4	14		T5	14
valid_sources[0x01]	54032	1			T7	5		T4	16		T5	7
valid_sources[0x02]	53425	1			T7	4		T4	59		T5	7
valid_sources[0x03]	53531	1			T7	5		T4	61		T5	9
valid_sources[0x04]	53050	1			T7	3		T4	36		T5	7
valid_sources[0x05]	53848	1			T7	3		T4	12		T5	8
valid_sources[0x06]	52503	1			T7	5		T4	16		T5	7
valid_sources[0x07]	53565	1			T7	2		T4	4		T5	7
valid_sources[0x08]	53702	1			T7	5		T4	13		T5	4
valid_sources[0x09]	53448	1			T7	3		T4	20		T5	10
valid_sources[0x0a]	52405	1			T7	4		T4	60		T5	14
valid_sources[0x0b]	53687	1			T7	7		T4	60		T5	10
valid_sources[0x0c]	52874	1			T7	8		T4	10		T5	7
valid_sources[0x0d]	52944	1			T7	3		T4	10		T5	12
valid_sources[0x0e]	53551	1			T7	5		T4	6		T5	7
valid_sources[0x0f]	53143	1			T7	5		T4	12		T5	7
valid_sources[0x10]	53664	1			T7	4		T4	24		T5	5
valid_sources[0x11]	53194	1			T7	6		T4	19		T5	12
valid_sources[0x12]	52610	1			T7	2		T4	26		T5	9
valid_sources[0x13]	53180	1			T7	3		T4	7		T5	10
valid_sources[0x14]	53009	1			T7	5		T4	3		T5	10
valid_sources[0x15]	51989	1			T7	6		T4	19		T5	6
valid_sources[0x16]	54004	1			T7	4		T4	19		T5	7
valid_sources[0x17]	54135	1			T7	4		T4	36		T5	5
valid_sources[0x18]	53810	1			T7	5		T4	65		T5	10
valid_sources[0x19]	53225	1			T7	8		T4	13		T5	10
valid_sources[0x1a]	52152	1			T7	10		T4	11		T5	12
valid_sources[0x1b]	52034	1			T7	3		T4	7		T5	7
valid_sources[0x1c]	53837	1			T7	4		T4	12		T5	6
valid_sources[0x1d]	54103	1			T7	4		T4	3		T5	11
valid_sources[0x1e]	52981	1			T7	3		T4	14		T5	9
valid_sources[0x1f]	52362	1			T7	5		T4	71		T5	4
valid_sources[0x20]	53387	1			T7	5		T4	17		T5	11

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

48720

1

T7

6

T4

22

T5

18

values[0x0]

all_enables

biggest_size

367597

1

T7

28

T4

173

T5

23

values[0x1]

all_enables

biggest_size

48774

1

T7

7

T4

20

T5

15

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3146989	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

512393

1

T7

39

T4

360

T5

53

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1250831	1			T7	87		T4	903		T5	290
values[0x0]	1155595	1			T7	88		T4	812		T5	39
values[0x1]	1252956	1			T7	80		T4	877		T5	278

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2415740	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1243642

1

T7

81

T4

890

T5

236

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	56055	1			T7	2		T4	41		T5	14
valid_sources[0x01]	56707	1			T7	2		T4	43		T5	13
valid_sources[0x02]	57256	1			T7	3		T4	55		T5	10
valid_sources[0x03]	56745	1			T7	1		T4	81		T5	7
valid_sources[0x04]	56715	1			T7	10		T4	53		T5	5
valid_sources[0x05]	57209	1			T7	1		T4	40		T5	7
valid_sources[0x06]	57599	1			T7	1		T4	36		T5	7
valid_sources[0x07]	57270	1			T7	4		T4	26		T5	15
valid_sources[0x08]	58093	1			T7	4		T4	57		T5	15
valid_sources[0x09]	56416	1			T7	3		T4	33		T5	10
valid_sources[0x0a]	56952	1			T7	2		T4	53		T5	11
valid_sources[0x0b]	57469	1			T7	8		T4	54		T5	9
valid_sources[0x0c]	57001	1			T7	5		T4	48		T5	10
valid_sources[0x0d]	57214	1			T7	2		T4	47		T5	7
valid_sources[0x0e]	57028	1			T7	2		T4	45		T5	5
valid_sources[0x0f]	56490	1			T7	3		T4	41		T5	16
valid_sources[0x10]	56602	1			T7	5		T4	31		T5	5
valid_sources[0x11]	57602	1			T7	5		T4	48		T5	9
valid_sources[0x12]	57192	1			T7	5		T4	35		T5	13
valid_sources[0x13]	57954	1			T7	3		T4	29		T5	7
valid_sources[0x14]	57373	1			T7	5		T4	29		T5	5
valid_sources[0x15]	56344	1			T7	6		T4	46		T5	11
valid_sources[0x16]	56273	1			T7	8		T4	31		T5	8
valid_sources[0x17]	56721	1			T7	1		T4	45		T5	13
valid_sources[0x18]	59127	1			T7	2		T4	26		T5	4
valid_sources[0x19]	57150	1			T7	1		T4	41		T5	7
valid_sources[0x1a]	57226	1			T7	3		T4	52		T5	7
valid_sources[0x1b]	57567	1			T7	7		T4	34		T5	14
valid_sources[0x1c]	57134	1			T4	31		T5	10		T6	29
valid_sources[0x1d]	58081	1			T7	1		T4	32		T5	15
valid_sources[0x1e]	57987	1			T7	4		T4	53		T5	5
valid_sources[0x1f]	56347	1			T7	3		T4	39		T5	10
valid_sources[0x20]	57059	1			T7	7		T4	41		T5	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

53754

1

T7

2

T4

35

T5

19

values[0x0]

all_enables

biggest_size

404812

1

T7

35

T4

295

T5

20

values[0x1]

all_enables

biggest_size

53827

1

T7

2

T4

30

T5

14

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2974406	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

469669

1

T7

39

T4

245

T5

65

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1165930	1			T7	69		T4	502		T5	277
values[0x0]	1112507	1			T7	80		T4	572		T5	49
values[0x1]	1165638	1			T7	88		T4	507		T5	312

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2303179	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1140896

1

T7

87

T4

539

T5

244

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	54404	1			T7	4		T4	7		T5	7
valid_sources[0x01]	52695	1			T7	2		T4	18		T5	11
valid_sources[0x02]	53472	1			T7	6		T4	36		T5	13
valid_sources[0x03]	55025	1			T7	5		T4	28		T5	6
valid_sources[0x04]	54212	1			T7	5		T4	28		T5	13
valid_sources[0x05]	53737	1			T7	4		T4	42		T5	11
valid_sources[0x06]	53785	1			T7	3		T4	26		T5	4
valid_sources[0x07]	54446	1			T7	2		T4	13		T5	13
valid_sources[0x08]	53722	1			T7	3		T4	30		T5	14
valid_sources[0x09]	53011	1			T7	5		T4	37		T5	11
valid_sources[0x0a]	53661	1			T7	4		T4	43		T5	14
valid_sources[0x0b]	54216	1			T7	3		T4	21		T5	14
valid_sources[0x0c]	53795	1			T7	4		T4	13		T5	6
valid_sources[0x0d]	54374	1			T7	2		T4	6		T5	5
valid_sources[0x0e]	53111	1			T7	4		T4	25		T5	4
valid_sources[0x0f]	53942	1			T7	4		T4	44		T5	7
valid_sources[0x10]	53901	1			T7	6		T4	19		T5	6
valid_sources[0x11]	53936	1			T7	2		T4	39		T5	9
valid_sources[0x12]	53766	1			T7	4		T4	29		T5	15
valid_sources[0x13]	54434	1			T7	3		T4	15		T5	5
valid_sources[0x14]	53716	1			T7	5		T4	28		T5	5
valid_sources[0x15]	53638	1			T7	3		T4	26		T5	12
valid_sources[0x16]	52853	1			T7	6		T4	27		T5	16
valid_sources[0x17]	54041	1			T7	2		T4	14		T5	10
valid_sources[0x18]	54730	1			T7	3		T4	13		T5	8
valid_sources[0x19]	53797	1			T7	5		T4	47		T5	4
valid_sources[0x1a]	52695	1			T7	4		T4	23		T5	15
valid_sources[0x1b]	53470	1			T7	6		T4	8		T5	7
valid_sources[0x1c]	54397	1			T7	3		T4	7		T5	8
valid_sources[0x1d]	54852	1			T7	2		T4	18		T5	18
valid_sources[0x1e]	53982	1			T7	2		T4	37		T5	9
valid_sources[0x1f]	52705	1			T7	3		T4	14		T5	14
valid_sources[0x20]	54080	1			T7	5		T4	12		T5	17

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

49354

1

T7

5

T4

28

T5

24

values[0x0]

all_enables

biggest_size

371213

1

T7

29

T4

196

T5

21

values[0x1]

all_enables

biggest_size

49102

1

T7

5

T4

21

T5

20