Unified Coverage Report :: Module :: i2c

Module : i2c

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.78			98.78

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_i2c1	97.55			97.55
tb.dut.top_earlgrey.u_i2c0	98.15			98.15
tb.dut.top_earlgrey.u_i2c2	98.16			98.16

---

Module Instance : tb.dut.top_earlgrey.u_i2c1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.55			97.55

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.55			97.55

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
79.29	54.12		83.74			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_i2c0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.15			98.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.15			98.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
79.29	54.12		83.74			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_i2c2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.16			98.16

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.16			98.16

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
79.29	54.12		83.74			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : i2c

	Total	Covered	Percent
Totals	48	46	95.83
Total Bits	328	324	98.78
Total Bits 0->1	164	162	98.78
Total Bits 1->0	164	162	98.78

Ports	48	46	95.83
Port Bits	328	324	98.78
Port Bits 0->1	164	162	98.78
Port Bits 1->0	164	162	98.78

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T7,T4,T5	Yes	T7,T4,T5	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T7,T4,T5	Yes	T7,T4,T5	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T7,T4,T5	Yes	T7,T4,T5	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T7,T4,T5	Yes	T7,T4,T5	INPUT
tl_i.a_address[6:0]	Yes	Yes	*T7,T4,T5	Yes	T7,T4,T5	INPUT
tl_i.a_address[15:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T7,T4,T5	Yes	T7,T4,T5	INPUT
tl_i.a_address[18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T7,*T4,*T5	Yes	T7,T4,T5	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	T7,T4,T5	Yes	T7,T4,T5	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T7,T4,T5	Yes	T7,T4,T5	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T7,T4,T5	Yes	T7,T4,T5	INPUT
tl_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_o.a_ready	Yes	Yes	T7,T4,T5	Yes	T7,T4,T5	OUTPUT
tl_o.d_error	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_sink	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T20,T8	Yes	T1,T20,T8	INPUT
alert_rx_i[0].ping_n	No	No		No		INPUT
alert_rx_i[0].ping_p	No	No		No		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T20,T8	Yes	T1,T20,T8	OUTPUT
cio_scl_i	Yes	Yes	T29,T14,T15	Yes	T29,T14,T15	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T1,T20,T8	Yes	T1,T20,T8	OUTPUT
cio_sda_i	Yes	Yes	T31,T29,T14	Yes	T31,T29,T14	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T1,T20,T10	Yes	T1,T20,T10	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T1,T9,T13	Yes	T1,T9,T13	OUTPUT
intr_rx_threshold_o	Yes	Yes	T13,T11,T21	Yes	T13,T11,T21	OUTPUT
intr_fmt_overflow_o	Yes	Yes	T12,T13,T11	Yes	T12,T13,T11	OUTPUT
intr_rx_overflow_o	Yes	Yes	T12,T13,T11	Yes	T12,T13,T11	OUTPUT
intr_nak_o	Yes	Yes	T10,T12,T13	Yes	T10,T12,T13	OUTPUT
intr_scl_interference_o	Yes	Yes	T10,T12,T13	Yes	T10,T12,T13	OUTPUT
intr_sda_interference_o	Yes	Yes	T1,T20,T8	Yes	T1,T20,T8	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T13,T11,T21	Yes	T13,T11,T21	OUTPUT
intr_sda_unstable_o	Yes	Yes	T12,T11,T21	Yes	T12,T11,T21	OUTPUT
intr_cmd_complete_o	Yes	Yes	T12,T13,T11	Yes	T12,T13,T11	OUTPUT
intr_tx_stretch_o	Yes	Yes	T12,T11,T21	Yes	T12,T11,T21	OUTPUT
intr_tx_overflow_o	Yes	Yes	T13,T11,T21	Yes	T13,T11,T21	OUTPUT
intr_acq_full_o	Yes	Yes	T10,T11,T21	Yes	T10,T11,T21	OUTPUT
intr_unexp_stop_o	Yes	Yes	T12,T11	Yes	T12,T11	OUTPUT
intr_host_timeout_o	Yes	Yes	T10,T12,T13	Yes	T10,T12,T13	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c1

	Total	Covered	Percent
Totals	48	44	91.67
Total Bits	326	318	97.55
Total Bits 0->1	163	159	97.55
Total Bits 1->0	163	159	97.55

Ports	48	44	91.67
Port Bits	326	318	97.55
Port Bits 0->1	163	159	97.55
Port Bits 1->0	163	159	97.55

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T7,T4,T5	Yes	T7,T4,T5	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T7,T4,T5	Yes	T7,T4,T5	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T7,T4,T5	Yes	T7,T4,T5	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T7,T4,T5	Yes	T7,T4,T5	INPUT
tl_i.a_address[6:0]	Yes	Yes	*T7,T4,T5	Yes	T7,T4,T5	INPUT
tl_i.a_address[15:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T7,*T4,*T5	Yes	T7,T4,T5	INPUT
tl_i.a_address[18:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T7,*T4,*T5	Yes	T7,T4,T5	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	T7,T4,T5	Yes	T7,T4,T5	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T7,T4,T5	Yes	T7,T4,T5	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T7,T4,T5	Yes	T7,T4,T5	INPUT
tl_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_o.a_ready	Yes	Yes	T7,T4,T5	Yes	T7,T4,T5	OUTPUT
tl_o.d_error	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_sink	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T20,T10	Yes	T1,T20,T10	INPUT
alert_rx_i[0].ping_n	No	No		No		INPUT
alert_rx_i[0].ping_p	No	No		No		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T20,T10	Yes	T1,T20,T10	OUTPUT
cio_scl_i	Yes	Yes	T29,T14,T15	Yes	T29,T14,T15	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T1,T20,T8	Yes	T1,T20,T8	OUTPUT
cio_sda_i	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T1,T20,T9	Yes	T1,T20,T9	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T9,T13,T150	Yes	T9,T13,T150	OUTPUT
intr_rx_threshold_o	Yes	Yes	T13,T11,T21	Yes	T13,T11,T21	OUTPUT
intr_fmt_overflow_o	No	No		No		OUTPUT
intr_rx_overflow_o	Yes	Yes	T12,T21	Yes	T12,T21	OUTPUT
intr_nak_o	Yes	Yes	T12	Yes	T12	OUTPUT
intr_scl_interference_o	Yes	Yes	T10,T13,T21	Yes	T10,T13,T21	OUTPUT
intr_sda_interference_o	Yes	Yes	T1,T8,T9	Yes	T1,T8,T9	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T13,T11	Yes	T13,T11	OUTPUT
intr_sda_unstable_o	Yes	Yes	T12	Yes	T12	OUTPUT
intr_cmd_complete_o	Yes	Yes	T12,T11	Yes	T12,T11	OUTPUT
intr_tx_stretch_o	Yes	Yes	T12	Yes	T12	OUTPUT
intr_tx_overflow_o	Yes	Yes	T13,T11,T21	Yes	T13,T11,T21	OUTPUT
intr_acq_full_o	Yes	Yes	T11,T21	Yes	T11,T21	OUTPUT
intr_unexp_stop_o	No	No		No		OUTPUT
intr_host_timeout_o	Yes	Yes	T10,T11,T21	Yes	T10,T11,T21	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c0

	Total	Covered	Percent
Totals	48	45	93.75
Total Bits	324	318	98.15
Total Bits 0->1	162	159	98.15
Total Bits 1->0	162	159	98.15

Ports	48	45	93.75
Port Bits	324	318	98.15
Port Bits 0->1	162	159	98.15
Port Bits 1->0	162	159	98.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T7,T4,T5	Yes	T7,T4,T5	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T7,T4,T5	Yes	T7,T4,T5	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T7,T4,T5	Yes	T7,T4,T5	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T7,T4,T5	Yes	T7,T4,T5	INPUT
tl_i.a_address[6:0]	Yes	Yes	*T7,T4,T5	Yes	T7,T4,T5	INPUT
tl_i.a_address[18:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T7,*T4,*T5	Yes	T7,T4,T5	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	T7,T4,T5	Yes	T7,T4,T5	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T7,T4,T5	Yes	T7,T4,T5	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T7,T4,T5	Yes	T7,T4,T5	INPUT
tl_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_o.a_ready	Yes	Yes	T7,T4,T5	Yes	T7,T4,T5	OUTPUT
tl_o.d_error	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_sink	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T20,T9	Yes	T1,T20,T9	INPUT
alert_rx_i[0].ping_n	No	No		No		INPUT
alert_rx_i[0].ping_p	No	No		No		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T20,T9	Yes	T1,T20,T9	OUTPUT
cio_scl_i	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T1,T20,T9	Yes	T1,T20,T9	OUTPUT
cio_sda_i	Yes	Yes	T31,T14,T15	Yes	T31,T14,T15	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T1,T20,T9	Yes	T1,T20,T9	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T1,T56,T45	Yes	T1,T56,T45	OUTPUT
intr_rx_threshold_o	Yes	Yes	T13,T21	Yes	T13,T21	OUTPUT
intr_fmt_overflow_o	Yes	Yes	T12	Yes	T12	OUTPUT
intr_rx_overflow_o	Yes	Yes	T13,T11,T21	Yes	T13,T11,T21	OUTPUT
intr_nak_o	Yes	Yes	T10,T13,T11	Yes	T10,T13,T11	OUTPUT
intr_scl_interference_o	Yes	Yes	T12,T21	Yes	T12,T21	OUTPUT
intr_sda_interference_o	Yes	Yes	T1,T9,T44	Yes	T1,T9,T44	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T11,T21	Yes	T11,T21	OUTPUT
intr_sda_unstable_o	Yes	Yes	T11,T21	Yes	T11,T21	OUTPUT
intr_cmd_complete_o	Yes	Yes	T13,T11	Yes	T13,T11	OUTPUT
intr_tx_stretch_o	Yes	Yes	T11,T21	Yes	T11,T21	OUTPUT
intr_tx_overflow_o	Yes	Yes	T11,T21	Yes	T11,T21	OUTPUT
intr_acq_full_o	No	No		No		OUTPUT
intr_unexp_stop_o	Yes	Yes	T12,T11	Yes	T12,T11	OUTPUT
intr_host_timeout_o	Yes	Yes	T12	Yes	T12	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c2

	Total	Covered	Percent
Totals	48	45	93.75
Total Bits	326	320	98.16
Total Bits 0->1	163	160	98.16
Total Bits 1->0	163	160	98.16

Ports	48	45	93.75
Port Bits	326	320	98.16
Port Bits 0->1	163	160	98.16
Port Bits 1->0	163	160	98.16

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T7,T4,T5	Yes	T7,T4,T5	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T7,T4,T5	Yes	T7,T4,T5	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T7,T4,T5	Yes	T7,T4,T5	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T7,T4,T5	Yes	T7,T4,T5	INPUT
tl_i.a_address[6:0]	Yes	Yes	*T7,T4,T5	Yes	T7,T4,T5	INPUT
tl_i.a_address[16:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T7,*T4,*T5	Yes	T7,T4,T5	INPUT
tl_i.a_address[18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T7,*T4,*T5	Yes	T7,T4,T5	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	T7,T4,T5	Yes	T7,T4,T5	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T7,T4,T5	Yes	T7,T4,T5	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T7,T4,T5	Yes	T7,T4,T5	INPUT
tl_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_o.a_ready	Yes	Yes	T7,T4,T5	Yes	T7,T4,T5	OUTPUT
tl_o.d_error	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_sink	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T20,T8	Yes	T1,T20,T8	INPUT
alert_rx_i[0].ping_n	No	No		No		INPUT
alert_rx_i[0].ping_p	No	No		No		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T20,T8	Yes	T1,T20,T8	OUTPUT
cio_scl_i	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T1,T20,T9	Yes	T1,T20,T9	OUTPUT
cio_sda_i	Yes	Yes	T29,T14,T15	Yes	T29,T14,T15	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T1,T10,T23	Yes	T1,T10,T23	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T13,T150,T55	Yes	T13,T150,T55	OUTPUT
intr_rx_threshold_o	Yes	Yes	T11,T21	Yes	T11,T21	OUTPUT
intr_fmt_overflow_o	Yes	Yes	T12,T13,T11	Yes	T12,T13,T11	OUTPUT
intr_rx_overflow_o	Yes	Yes	T12,T13,T21	Yes	T12,T13,T21	OUTPUT
intr_nak_o	Yes	Yes	T12,T13,T21	Yes	T12,T13,T21	OUTPUT
intr_scl_interference_o	Yes	Yes	T10,T12,T13	Yes	T10,T12,T13	OUTPUT
intr_sda_interference_o	Yes	Yes	T20,T8,T31	Yes	T20,T8,T31	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T21	Yes	T21	OUTPUT
intr_sda_unstable_o	Yes	Yes	T12,T21	Yes	T12,T21	OUTPUT
intr_cmd_complete_o	Yes	Yes	T13,T21	Yes	T13,T21	OUTPUT
intr_tx_stretch_o	Yes	Yes	T11,T21	Yes	T11,T21	OUTPUT
intr_tx_overflow_o	No	No		No		OUTPUT
intr_acq_full_o	Yes	Yes	T10,T11	Yes	T10,T11	OUTPUT
intr_unexp_stop_o	Yes	Yes	T12	Yes	T12	OUTPUT
intr_host_timeout_o	Yes	Yes	T13,T11,T21	Yes	T13,T11,T21	OUTPUT

*Tests covering at least one bit in the range