Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_42.wr_en_data_arb

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_42.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_mio_pad_sleep_mode_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_43.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_mio_pad_sleep_mode_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_44.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_mio_pad_sleep_mode_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_45.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_mio_pad_sleep_mode_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_46.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_mio_pad_sleep_mode_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_sleep_status_en_0.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.00	100.00	90.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.00	100.00	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.24	85.71	100.00			100.00		u_dio_pad_sleep_status_en_0

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_sleep_status_en_1.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.00	100.00	90.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.00	100.00	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.24	85.71	100.00			100.00		u_dio_pad_sleep_status_en_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_sleep_status_en_2.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.00	100.00	90.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.00	100.00	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.24	85.71	100.00			100.00		u_dio_pad_sleep_status_en_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_sleep_status_en_3.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.00	100.00	90.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.00	100.00	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.24	85.71	100.00			100.00		u_dio_pad_sleep_status_en_3

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_sleep_status_en_4.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.00	100.00	90.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.00	100.00	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.24	85.71	100.00			100.00		u_dio_pad_sleep_status_en_4

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_sleep_status_en_5.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.00	100.00	90.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.00	100.00	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.24	85.71	100.00			100.00		u_dio_pad_sleep_status_en_5

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_sleep_status_en_6.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.00	100.00	90.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.00	100.00	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.24	85.71	100.00			100.00		u_dio_pad_sleep_status_en_6

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_sleep_status_en_7.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.00	100.00	90.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.00	100.00	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.24	85.71	100.00			100.00		u_dio_pad_sleep_status_en_7

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_42.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	33	1	1	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	39	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1
34	1	1
39		unreachable

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_42.wr_en_data_arb

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T7,T4,T5
0	1	Unreachable
1	0	Covered	T6,T1,T72

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T7,T4,T5
1	Covered	T6,T1,T72

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T7,T4,T5
1	Covered	T6,T1,T72

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_42.wr_en_data_arb

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	34	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	34	((we == 1'b1)) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T72
0	Covered	T7,T4,T5

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_43.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	33	1	1	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	39	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1
34	1	1
39		unreachable

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_43.wr_en_data_arb

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T7,T4,T5
0	1	Unreachable
1	0	Covered	T20,T8,T90

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T7,T4,T5
1	Covered	T20,T8,T90

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T7,T4,T5
1	Covered	T20,T8,T90

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_43.wr_en_data_arb

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	34	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	34	((we == 1'b1)) ? 

Branches:

-1-	Status	Tests
1	Covered	T20,T8,T90
0	Covered	T7,T4,T5

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_44.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	33	1	1	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	39	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1
34	1	1
39		unreachable

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_44.wr_en_data_arb

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T7,T4,T5
0	1	Unreachable
1	0	Covered	T82,T1,T90

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T7,T4,T5
1	Covered	T82,T1,T90

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T7,T4,T5
1	Covered	T82,T1,T90

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_44.wr_en_data_arb

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	34	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	34	((we == 1'b1)) ? 

Branches:

-1-	Status	Tests
1	Covered	T82,T1,T90
0	Covered	T7,T4,T5

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_45.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	33	1	1	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	39	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1
34	1	1
39		unreachable

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_45.wr_en_data_arb

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T7,T4,T5
0	1	Unreachable
1	0	Covered	T59,T1,T78

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T7,T4,T5
1	Covered	T59,T1,T78

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T7,T4,T5
1	Covered	T59,T1,T78

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_45.wr_en_data_arb

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	34	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	34	((we == 1'b1)) ? 

Branches:

-1-	Status	Tests
1	Covered	T59,T1,T78
0	Covered	T7,T4,T5

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_46.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	33	1	1	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	39	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1
34	1	1
39		unreachable

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_46.wr_en_data_arb

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T7,T4,T5
0	1	Unreachable
1	0	Covered	T71,T20,T8

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T7,T4,T5
1	Covered	T71,T20,T8

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T7,T4,T5
1	Covered	T71,T20,T8

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_mode_46.wr_en_data_arb

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	34	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	34	((we == 1'b1)) ? 

Branches:

-1-	Status	Tests
1	Covered	T71,T20,T8
0	Covered	T7,T4,T5

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_sleep_status_en_0.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	135	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
113	1	1
135	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_sleep_status_en_0.wr_en_data_arb

	Total	Covered	Percent
Conditions	10	9	90.00
Logical	10	9	90.00
Non-Logical	0	0
Event	0	0

 LINE       113
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T7,T4,T5
0	1	Covered	T20,T10,T22
1	0	Covered	T1,T72,T20

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Not Covered
1	1	Covered	T20,T10,T22

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1

-1-	Status	Tests
0	Covered	T7,T4,T5
1	Covered	T20,T10,T22

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1

-1-	Status	Tests
0	Covered	T7,T4,T5
1	Covered	T1,T72,T20

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_sleep_status_en_1.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	135	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
113	1	1
135	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_sleep_status_en_1.wr_en_data_arb

	Total	Covered	Percent
Conditions	10	9	90.00
Logical	10	9	90.00
Non-Logical	0	0
Event	0	0

 LINE       113
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T7,T4,T5
0	1	Covered	T9,T44,T62
1	0	Covered	T1,T72,T20

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Not Covered
1	1	Covered	T9,T44,T62

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1

-1-	Status	Tests
0	Covered	T7,T4,T5
1	Covered	T9,T44,T62

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1

-1-	Status	Tests
0	Covered	T7,T4,T5
1	Covered	T1,T72,T20

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_sleep_status_en_2.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	135	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
113	1	1
135	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_sleep_status_en_2.wr_en_data_arb

	Total	Covered	Percent
Conditions	10	9	90.00
Logical	10	9	90.00
Non-Logical	0	0
Event	0	0

 LINE       113
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T7,T4,T5
0	1	Covered	T20,T8,T10
1	0	Covered	T1,T72,T20

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Not Covered
1	1	Covered	T20,T8,T10

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1

-1-	Status	Tests
0	Covered	T7,T4,T5
1	Covered	T20,T8,T10

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1

-1-	Status	Tests
0	Covered	T7,T4,T5
1	Covered	T1,T72,T20

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_sleep_status_en_3.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	135	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
113	1	1
135	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_sleep_status_en_3.wr_en_data_arb

	Total	Covered	Percent
Conditions	10	9	90.00
Logical	10	9	90.00
Non-Logical	0	0
Event	0	0

 LINE       113
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T7,T4,T5
0	1	Covered	T1,T8,T10
1	0	Covered	T1,T72,T20

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Not Covered
1	1	Covered	T1,T8,T10

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1

-1-	Status	Tests
0	Covered	T7,T4,T5
1	Covered	T1,T8,T10

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1

-1-	Status	Tests
0	Covered	T7,T4,T5
1	Covered	T1,T72,T20

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_sleep_status_en_4.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	135	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
113	1	1
135	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_sleep_status_en_4.wr_en_data_arb

	Total	Covered	Percent
Conditions	10	9	90.00
Logical	10	9	90.00
Non-Logical	0	0
Event	0	0

 LINE       113
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T7,T4,T5
0	1	Covered	T23,T62,T29
1	0	Covered	T1,T72,T20

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Not Covered
1	1	Covered	T23,T62,T29

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1

-1-	Status	Tests
0	Covered	T7,T4,T5
1	Covered	T23,T62,T29

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1

-1-	Status	Tests
0	Covered	T7,T4,T5
1	Covered	T1,T72,T20

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_sleep_status_en_5.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	135	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
113	1	1
135	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_sleep_status_en_5.wr_en_data_arb

	Total	Covered	Percent
Conditions	10	9	90.00
Logical	10	9	90.00
Non-Logical	0	0
Event	0	0

 LINE       113
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T7,T4,T5
0	1	Covered	T10,T9,T62
1	0	Covered	T1,T72,T20

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Not Covered
1	1	Covered	T10,T9,T62

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1

-1-	Status	Tests
0	Covered	T7,T4,T5
1	Covered	T10,T9,T62

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1

-1-	Status	Tests
0	Covered	T7,T4,T5
1	Covered	T1,T72,T20

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_sleep_status_en_6.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	135	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
113	1	1
135	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_sleep_status_en_6.wr_en_data_arb

	Total	Covered	Percent
Conditions	10	9	90.00
Logical	10	9	90.00
Non-Logical	0	0
Event	0	0

 LINE       113
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T7,T4,T5
0	1	Covered	T1,T8,T44
1	0	Covered	T1,T72,T20

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Not Covered
1	1	Covered	T1,T8,T44

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1

-1-	Status	Tests
0	Covered	T7,T4,T5
1	Covered	T1,T8,T44

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1

-1-	Status	Tests
0	Covered	T7,T4,T5
1	Covered	T1,T72,T20

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_sleep_status_en_7.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	135	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
113	1	1
135	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_sleep_status_en_7.wr_en_data_arb

	Total	Covered	Percent
Conditions	10	9	90.00
Logical	10	9	90.00
Non-Logical	0	0
Event	0	0

 LINE       113
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T7,T4,T5
0	1	Covered	T1,T20,T8
1	0	Covered	T1,T72,T20

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Not Covered
1	1	Covered	T1,T20,T8

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1

-1-	Status	Tests
0	Covered	T7,T4,T5
1	Covered	T1,T20,T8

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1

-1-	Status	Tests
0	Covered	T7,T4,T5
1	Covered	T1,T72,T20