Unified Coverage Report :: Module :: aon_timer

Module : aon_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.18			96.18

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_aon_timer_0.1/rtl/aon_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_aon_timer_aon	96.18			96.18

---

Module Instance : tb.dut.top_earlgrey.u_aon_timer_aon

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.18			96.18

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.18			96.18

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
79.29	54.12		83.74			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : aon_timer

	Total	Covered	Percent
Totals	38	35	92.11
Total Bits	314	302	96.18
Total Bits 0->1	157	151	96.18
Total Bits 1->0	157	151	96.18

Ports	38	35	92.11
Port Bits	314	302	96.18
Port Bits 0->1	157	151	96.18
Port Bits 1->0	157	151	96.18

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_aon_i	Yes	Yes	T7,T4,T5	Yes	T7,T4,T5	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_aon_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T7,T4,T5	Yes	T7,T4,T5	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T7,T4,T5	Yes	T7,T4,T5	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T7,T4,T5	Yes	T7,T4,T5	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T7,T4,T5	Yes	T7,T4,T5	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T7,T4,T5	Yes	T7,T4,T5	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T7,T4,T5	Yes	T7,T4,T5	INPUT
tl_i.a_address[5:0]	Yes	Yes	T7,T4,T5	Yes	T7,T4,T5	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[18:16]	Yes	Yes	T7,T4,T5	Yes	T7,T4,T5	INPUT
tl_i.a_address[21:19]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[22]	Yes	Yes	*T7,*T4,*T5	Yes	T7,T4,T5	INPUT
tl_i.a_address[29:23]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T7,*T4,*T5	Yes	T7,T4,T5	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	T7,T4,T5	Yes	T7,T4,T5	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T7,T4,T5	Yes	T7,T4,T5	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T7,T4,T5	Yes	T7,T4,T5	INPUT
tl_i.a_valid	Yes	Yes	T7,T4,T5	Yes	T7,T4,T5	INPUT
tl_o.a_ready	Yes	Yes	T7,T4,T5	Yes	T7,T4,T5	OUTPUT
tl_o.d_error	Yes	Yes	T7,T4,T5	Yes	T7,T4,T5	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T7,T4,T5	Yes	T7,T4,T5	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T7,T4,T5	Yes	T7,T4,T5	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T7,T4,T5	Yes	T7,T4,T5	OUTPUT
tl_o.d_sink	Yes	Yes	T7,T4,T5	Yes	T7,T4,T5	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	T7,T4,T5	Yes	T7,T4,T5	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T7,T4,T5	Yes	T7,T4,T5	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T7,*T4,*T5	Yes	T7,T4,T5	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T7,T4,T5	Yes	T7,T4,T5	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T9,T23	Yes	T1,T9,T23	INPUT
alert_rx_i[0].ping_n	No	No		No		INPUT
alert_rx_i[0].ping_p	No	No		No		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T9,T23	Yes	T1,T9,T23	OUTPUT
lc_escalate_en_i[3:0]	No	No		No		INPUT
intr_wkup_timer_expired_o	Yes	Yes	T1,T20,T23	Yes	T1,T20,T23	OUTPUT
intr_wdog_timer_bark_o	Yes	Yes	T1,T20,T8	Yes	T1,T20,T8	OUTPUT
nmi_wdog_timer_bark_o	Yes	Yes	T1,T20,T8	Yes	T1,T20,T8	OUTPUT
wkup_req_o	Yes	Yes	T20,T23,T22	Yes	T20,T23,T22	OUTPUT
aon_timer_rst_req_o	Yes	Yes	T20,T23,T22	Yes	T20,T23,T22	OUTPUT
sleep_mode_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT

*Tests covering at least one bit in the range