Unified Coverage Report :: Module :: entropy_src

Module : entropy_src

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
32.53			32.53

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_entropy_src_0.1/rtl/entropy_src.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_entropy_src	34.46			34.46

---

Module Instance : tb.dut.top_earlgrey.u_entropy_src

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
34.46			34.46

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
34.46			34.46

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
79.29	54.12		83.74			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : entropy_src

	Total	Covered	Percent
Totals	65	38	58.46
Total Bits	1322	430	32.53
Total Bits 0->1	661	215	32.53
Total Bits 1->0	661	215	32.53

Ports	65	38	58.46
Port Bits	1322	430	32.53
Port Bits 0->1	661	215	32.53
Port Bits 1->0	661	215	32.53

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T7,T4,T5	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[7:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[16:8]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[18:17]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[19]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[20]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[24]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_o.a_ready	Yes	Yes	T7,T4,T5	Yes	T7,T4,T5	OUTPUT
tl_o.d_error	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_sink	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otp_en_entropy_src_fw_read_i[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
otp_en_entropy_src_fw_over_i[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rng_fips_o	No	No		No		OUTPUT
entropy_src_hw_if_i.es_req	No	No		No		INPUT
entropy_src_hw_if_o.es_fips	No	No		No		OUTPUT
entropy_src_hw_if_o.es_bits[383:0]	No	No		No		OUTPUT
entropy_src_hw_if_o.es_ack	No	No		No		OUTPUT
entropy_src_rng_o.rng_enable	No	No		No		OUTPUT
entropy_src_rng_i.rng_b[3:0]	No	No		No		INPUT
entropy_src_rng_i.rng_valid	No	No		No		INPUT
cs_aes_halt_o.cs_aes_halt_req	No	No		No		OUTPUT
cs_aes_halt_i.cs_aes_halt_ack	No	No		No		INPUT
entropy_src_xht_o.threshold_scope	No	No		No		OUTPUT
entropy_src_xht_o.window_wrap_pulse	No	No		No		OUTPUT
entropy_src_xht_o.health_test_window[15:0]	Yes	Yes	T1,T20,T8	Yes	T1,T20,T8	OUTPUT
entropy_src_xht_o.thresh_lo[0]	Yes	Yes	*T12,*T21	Yes	T12,T21	OUTPUT
entropy_src_xht_o.thresh_lo[1]	No	No		No		OUTPUT
entropy_src_xht_o.thresh_lo[15:2]	Yes	Yes	T13,T11,T21	Yes	T13,T11,T21	OUTPUT
entropy_src_xht_o.thresh_hi[15:0]	Yes	Yes	T10,T13,T11	Yes	T10,T13,T11	OUTPUT
entropy_src_xht_o.active	No	No		No		OUTPUT
entropy_src_xht_o.clear	No	No		No		OUTPUT
entropy_src_xht_o.entropy_bit_valid	No	No		No		OUTPUT
entropy_src_xht_o.entropy_bit[3:0]	No	No		No		OUTPUT
entropy_src_xht_i.test_fail_lo_pulse	No	No		No		INPUT
entropy_src_xht_i.test_fail_hi_pulse	No	No		No		INPUT
entropy_src_xht_i.continuous_test	No	No		No		INPUT
entropy_src_xht_i.test_cnt_lo[15:0]	No	No		No		INPUT
entropy_src_xht_i.test_cnt_hi[15:0]	No	No		No		INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T20,T10	Yes	T1,T20,T10	INPUT
alert_rx_i[0].ping_n	No	No		No		INPUT
alert_rx_i[0].ping_p	No	No		No		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T1,T20,T9	Yes	T1,T20,T9	INPUT
alert_rx_i[1].ping_n	No	No		No		INPUT
alert_rx_i[1].ping_p	No	No		No		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T20,T10	Yes	T1,T20,T10	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T1,T20,T9	Yes	T1,T20,T9	OUTPUT
intr_es_entropy_valid_o	Yes	Yes	T11	Yes	T11	OUTPUT
intr_es_health_test_failed_o	Yes	Yes	T12,T21	Yes	T12,T21	OUTPUT
intr_es_observe_fifo_ready_o	Yes	Yes	T12,T13,T11	Yes	T12,T13,T11	OUTPUT
intr_es_fatal_err_o	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_entropy_src

	Total	Covered	Percent
Totals	58	38	65.52
Total Bits	1248	430	34.46
Total Bits 0->1	624	215	34.46
Total Bits 1->0	624	215	34.46

Ports	58	38	65.52
Port Bits	1248	430	34.46
Port Bits 0->1	624	215	34.46
Port Bits 1->0	624	215	34.46

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T7,T4,T5	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[7:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[16:8]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[18:17]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[19]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[20]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[24]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_o.a_ready	Yes	Yes	T7,T4,T5	Yes	T7,T4,T5	OUTPUT
tl_o.d_error	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_sink	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
otp_en_entropy_src_fw_read_i[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
otp_en_entropy_src_fw_over_i[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rng_fips_o	No	No		No		OUTPUT
entropy_src_hw_if_i.es_req	No	No		No		INPUT
entropy_src_hw_if_o.es_fips	No	No		No		OUTPUT
entropy_src_hw_if_o.es_bits[383:0]	No	No		No		OUTPUT
entropy_src_hw_if_o.es_ack	No	No		No		OUTPUT
entropy_src_rng_o.rng_enable	No	No		No		OUTPUT
entropy_src_rng_i.rng_b[3:0]	No	No		No		INPUT
entropy_src_rng_i.rng_valid	No	No		No		INPUT
cs_aes_halt_o.cs_aes_halt_req	No	No		No		OUTPUT
cs_aes_halt_i.cs_aes_halt_ack	No	No		No		INPUT
entropy_src_xht_o.threshold_scope[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off / unconnected port.
entropy_src_xht_o.window_wrap_pulse	No	No		No		OUTPUT
entropy_src_xht_o.health_test_window[15:0]	Yes	Yes	T1,T20,T8	Yes	T1,T20,T8	OUTPUT
entropy_src_xht_o.thresh_lo[0]	Yes	Yes	*T12,*T21	Yes	T12,T21	OUTPUT
entropy_src_xht_o.thresh_lo[1]	No	No		No		OUTPUT
entropy_src_xht_o.thresh_lo[15:2]	Yes	Yes	T13,T11,T21	Yes	T13,T11,T21	OUTPUT
entropy_src_xht_o.thresh_hi[15:0]	Yes	Yes	T10,T13,T11	Yes	T10,T13,T11	OUTPUT
entropy_src_xht_o.active[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off / unconnected port.
entropy_src_xht_o.clear	No	No		No		OUTPUT
entropy_src_xht_o.entropy_bit_valid	No	No		No		OUTPUT
entropy_src_xht_o.entropy_bit[3:0]	No	No		No		OUTPUT
entropy_src_xht_i.test_fail_lo_pulse[0:0]	Excluded	Excluded		Excluded		INPUT	[UNR] Tied off / unconnected port.
entropy_src_xht_i.test_fail_hi_pulse[0:0]	Excluded	Excluded		Excluded		INPUT	[UNR] Tied off / unconnected port.
entropy_src_xht_i.continuous_test[0:0]	Excluded	Excluded		Excluded		INPUT	[UNR] Tied off / unconnected port.
entropy_src_xht_i.test_cnt_lo[15:0]	Excluded	Excluded		Excluded		INPUT	[UNR] Tied off / unconnected port.
entropy_src_xht_i.test_cnt_hi[15:0]	Excluded	Excluded		Excluded		INPUT	[UNR] Tied off / unconnected port.
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T20,T10	Yes	T1,T20,T10	INPUT
alert_rx_i[0].ping_n	No	No		No		INPUT
alert_rx_i[0].ping_p	No	No		No		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T1,T20,T9	Yes	T1,T20,T9	INPUT
alert_rx_i[1].ping_n	No	No		No		INPUT
alert_rx_i[1].ping_p	No	No		No		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T20,T10	Yes	T1,T20,T10	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T1,T20,T9	Yes	T1,T20,T9	OUTPUT
intr_es_entropy_valid_o	Yes	Yes	T11	Yes	T11	OUTPUT
intr_es_health_test_failed_o	Yes	Yes	T12,T21	Yes	T12,T21	OUTPUT
intr_es_observe_fifo_ready_o	Yes	Yes	T12,T13,T11	Yes	T12,T13,T11	OUTPUT
intr_es_fatal_err_o	No	No		No		OUTPUT

*Tests covering at least one bit in the range