Unified Coverage Report :: Module :: rv_core_ibex_cfg_reg_top

Module : rv_core_ibex_cfg_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	99.44	98.08			97.14	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex_cfg_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg	98.67	99.44	98.08			97.14	100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	99.44	98.08			97.14	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.06	96.56	96.53			99.16	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
55.88	48.24	46.43	62.34		75.00	47.37	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_alert_test_fatal_hw_err	100.00	100.00
u_alert_test_fatal_sw_err	100.00	100.00
u_alert_test_recov_hw_err	100.00	100.00
u_alert_test_recov_sw_err	100.00	100.00
u_chk	100.00	100.00					100.00
u_dbus_addr_en_0	100.00	100.00	100.00			100.00
u_dbus_addr_en_1	100.00	100.00	100.00			100.00
u_dbus_addr_matching_0	100.00	100.00	100.00			100.00
u_dbus_addr_matching_1	100.00	100.00	100.00			100.00
u_dbus_regwen_0	100.00	100.00	100.00			100.00
u_dbus_regwen_1	100.00	100.00	100.00			100.00
u_dbus_remap_addr_0	100.00	100.00	100.00			100.00
u_dbus_remap_addr_1	100.00	100.00	100.00			100.00
u_err_status_fatal_core_err	85.19	88.89	66.67			100.00
u_err_status_fatal_intg_err	96.30	88.89	100.00			100.00
u_err_status_recov_core_err	85.19	88.89	66.67			100.00
u_err_status_reg_intg_err	93.52	88.89	91.67			100.00
u_fpga_info	33.33	33.33
u_ibus_addr_en_0	100.00	100.00	100.00			100.00
u_ibus_addr_en_1	100.00	100.00	100.00			100.00
u_ibus_addr_matching_0	100.00	100.00	100.00			100.00
u_ibus_addr_matching_1	100.00	100.00	100.00			100.00
u_ibus_regwen_0	100.00	100.00	100.00			100.00
u_ibus_regwen_1	100.00	100.00	100.00			100.00
u_ibus_remap_addr_0	100.00	100.00	100.00			100.00
u_ibus_remap_addr_1	100.00	100.00	100.00			100.00
u_nmi_enable_alert_en	100.00	100.00	100.00			100.00
u_nmi_enable_wdog_en	100.00	100.00	100.00			100.00
u_nmi_state_alert	85.19	88.89	66.67			100.00
u_nmi_state_wdog	100.00	100.00	100.00			100.00
u_prim_reg_we_check	100.00	100.00
u_reg_if	98.67	97.14	97.53			100.00	100.00
u_rnd_data	33.33	33.33
u_rnd_status_rnd_data_fips	33.33	33.33
u_rnd_status_rnd_data_valid	33.33	33.33
u_rsp_intg_gen	100.00	100.00					100.00
u_socket	96.10	93.75	94.64			96.00	100.00
u_sw_fatal_err	100.00	100.00	100.00			100.00
u_sw_recov_err	100.00	100.00	100.00			100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rv_core_ibex_cfg_reg_top

	Line No.	Total	Covered	Percent
TOTAL		178	177	99.44
ALWAYS	76	4	3	75.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
ALWAYS	133	3	3	100.00
CONT_ASSIGN	170	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	281	1	1	100.00
CONT_ASSIGN	297	1	1	100.00
CONT_ASSIGN	313	1	1	100.00
CONT_ASSIGN	329	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	514	1	1	100.00
CONT_ASSIGN	546	1	1	100.00
CONT_ASSIGN	578	1	1	100.00
CONT_ASSIGN	610	1	1	100.00
CONT_ASSIGN	700	1	1	100.00
CONT_ASSIGN	732	1	1	100.00
CONT_ASSIGN	764	1	1	100.00
CONT_ASSIGN	796	1	1	100.00
CONT_ASSIGN	828	1	1	100.00
CONT_ASSIGN	860	1	1	100.00
ALWAYS	1177	26	26	100.00
CONT_ASSIGN	1205	1	1	100.00
ALWAYS	1209	1	1	100.00
CONT_ASSIGN	1238	1	1	100.00
CONT_ASSIGN	1240	1	1	100.00
CONT_ASSIGN	1242	1	1	100.00
CONT_ASSIGN	1244	1	1	100.00
CONT_ASSIGN	1246	1	1	100.00
CONT_ASSIGN	1247	1	1	100.00
CONT_ASSIGN	1249	1	1	100.00
CONT_ASSIGN	1250	1	1	100.00
CONT_ASSIGN	1252	1	1	100.00
CONT_ASSIGN	1253	1	1	100.00
CONT_ASSIGN	1255	1	1	100.00
CONT_ASSIGN	1256	1	1	100.00
CONT_ASSIGN	1258	1	1	100.00
CONT_ASSIGN	1259	1	1	100.00
CONT_ASSIGN	1261	1	1	100.00
CONT_ASSIGN	1262	1	1	100.00
CONT_ASSIGN	1264	1	1	100.00
CONT_ASSIGN	1265	1	1	100.00
CONT_ASSIGN	1267	1	1	100.00
CONT_ASSIGN	1268	1	1	100.00
CONT_ASSIGN	1270	1	1	100.00
CONT_ASSIGN	1271	1	1	100.00
CONT_ASSIGN	1273	1	1	100.00
CONT_ASSIGN	1274	1	1	100.00
CONT_ASSIGN	1276	1	1	100.00
CONT_ASSIGN	1277	1	1	100.00
CONT_ASSIGN	1279	1	1	100.00
CONT_ASSIGN	1280	1	1	100.00
CONT_ASSIGN	1282	1	1	100.00
CONT_ASSIGN	1283	1	1	100.00
CONT_ASSIGN	1285	1	1	100.00
CONT_ASSIGN	1286	1	1	100.00
CONT_ASSIGN	1288	1	1	100.00
CONT_ASSIGN	1289	1	1	100.00
CONT_ASSIGN	1291	1	1	100.00
CONT_ASSIGN	1292	1	1	100.00
CONT_ASSIGN	1294	1	1	100.00
CONT_ASSIGN	1295	1	1	100.00
CONT_ASSIGN	1297	1	1	100.00
CONT_ASSIGN	1298	1	1	100.00
CONT_ASSIGN	1300	1	1	100.00
CONT_ASSIGN	1301	1	1	100.00
CONT_ASSIGN	1303	1	1	100.00
CONT_ASSIGN	1305	1	1	100.00
CONT_ASSIGN	1306	1	1	100.00
CONT_ASSIGN	1308	1	1	100.00
CONT_ASSIGN	1310	1	1	100.00
CONT_ASSIGN	1311	1	1	100.00
CONT_ASSIGN	1313	1	1	100.00
CONT_ASSIGN	1315	1	1	100.00
CONT_ASSIGN	1317	1	1	100.00
CONT_ASSIGN	1319	1	1	100.00
CONT_ASSIGN	1320	1	1	100.00
CONT_ASSIGN	1321	1	1	100.00
CONT_ASSIGN	1322	1	1	100.00
ALWAYS	1326	26	26	100.00
ALWAYS	1356	36	36	100.00
CONT_ASSIGN	1478	0	0
CONT_ASSIGN	1486	1	1	100.00
CONT_ASSIGN	1487	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex_cfg_reg_top.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex_cfg_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
76	1	1
77	1	1
78	1	1
79	0	1
			MISSING_ELSE
85	1	1
103	1	1
104	1	1
106	1	1
107	1	1
133	1	1
139	1	1
140	1	1
			MISSING_ELSE
170	1	1
171	1	1
266	1	1
281	1	1
297	1	1
313	1	1
329	1	1
450	1	1
482	1	1
514	1	1
546	1	1
578	1	1
610	1	1
700	1	1
732	1	1
764	1	1
796	1	1
828	1	1
860	1	1
1177	1	1
1178	1	1
1179	1	1
1180	1	1
1181	1	1
1182	1	1
1183	1	1
1184	1	1
1185	1	1
1186	1	1
1187	1	1
1188	1	1
1189	1	1
1190	1	1
1191	1	1
1192	1	1
1193	1	1
1194	1	1
1195	1	1
1196	1	1
1197	1	1
1198	1	1
1199	1	1
1200	1	1
1201	1	1
1202	1	1
1205	1	1
1209	1	1
1238	1	1
1240	1	1
1242	1	1
1244	1	1
1246	1	1
1247	1	1
1249	1	1
1250	1	1
1252	1	1
1253	1	1
1255	1	1
1256	1	1
1258	1	1
1259	1	1
1261	1	1
1262	1	1
1264	1	1
1265	1	1
1267	1	1
1268	1	1
1270	1	1
1271	1	1
1273	1	1
1274	1	1
1276	1	1
1277	1	1
1279	1	1
1280	1	1
1282	1	1
1283	1	1
1285	1	1
1286	1	1
1288	1	1
1289	1	1
1291	1	1
1292	1	1
1294	1	1
1295	1	1
1297	1	1
1298	1	1
1300	1	1
1301	1	1
1303	1	1
1305	1	1
1306	1	1
1308	1	1
1310	1	1
1311	1	1
1313	1	1
1315	1	1
1317	1	1
1319	1	1
1320	1	1
1321	1	1
1322	1	1
1326	1	1
1327	1	1
1328	1	1
1329	1	1
1330	1	1
1331	1	1
1332	1	1
1333	1	1
1334	1	1
1335	1	1
1336	1	1
1337	1	1
1338	1	1
1339	1	1
1340	1	1
1341	1	1
1342	1	1
1343	1	1
1344	1	1
1345	1	1
1346	1	1
1347	1	1
1348	1	1
1349	1	1
1350	1	1
1351	1	1
1356	1	1
1357	1	1
1359	1	1
1360	1	1
1361	1	1
1362	1	1
1366	1	1
1370	1	1
1374	1	1
1378	1	1
1382	1	1
1386	1	1
1390	1	1
1394	1	1
1398	1	1
1402	1	1
1406	1	1
1410	1	1
1414	1	1
1418	1	1
1422	1	1
1426	1	1
1430	1	1
1434	1	1
1438	1	1
1439	1	1
1443	1	1
1444	1	1
1448	1	1
1449	1	1
1450	1	1
1451	1	1
1455	1	1
1459	1	1
1460	1	1
1464	1	1
1478		unreachable
1486	1	1
1487	1	1

---

Cond Coverage for Module : rv_core_ibex_cfg_reg_top

	Total	Covered	Percent
Conditions	313	307	98.08
Logical	313	307	98.08
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T4,T6,T46
1	1	Covered	T4,T6,T46

 LINE       78
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       85
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T7,T4,T5
0	0	1	Not Covered
0	1	0	Covered	T5,T42,T148
1	0	0	Not Covered

 LINE       133
 EXPRESSION ((tl_i.a_address[(AW - 1):0] inside {[128:159]}) ? 1'b0 : 1'b1)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T7,T4,T5
1	Covered	T4,T5,T6

 LINE       171
 EXPRESSION ((devmode_i & addrmiss) | wr_err | intg_err)
             -----------1----------   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T7,T4,T5
0	0	1	Covered	T5,T42,T148
0	1	0	Covered	T4,T6,T46
1	0	0	Covered	T4,T6,T46

 LINE       171
 SUB-EXPRESSION (devmode_i & addrmiss)
                 ----1----   ----2---

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T7,T4,T5
1	1	Covered	T4,T5,T6

 LINE       450
 EXPRESSION (ibus_addr_en_0_we & ibus_regwen_0_qs)
             --------1--------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T20,T43,T29
1	1	Covered	T46,T61,T86

 LINE       482
 EXPRESSION (ibus_addr_en_1_we & ibus_regwen_1_qs)
             --------1--------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T1,T20,T8
1	1	Covered	T6,T59,T60

 LINE       514
 EXPRESSION (ibus_addr_matching_0_we & ibus_regwen_0_qs)
             -----------1-----------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T1,T20,T8
1	1	Covered	T4,T6,T46

 LINE       546
 EXPRESSION (ibus_addr_matching_1_we & ibus_regwen_1_qs)
             -----------1-----------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T1,T20,T9
1	1	Covered	T60,T83,T47

 LINE       578
 EXPRESSION (ibus_remap_addr_0_we & ibus_regwen_0_qs)
             ----------1---------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T20,T8,T10
1	1	Covered	T47,T48,T1

 LINE       610
 EXPRESSION (ibus_remap_addr_1_we & ibus_regwen_1_qs)
             ----------1---------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T1,T20,T32
1	1	Covered	T4,T82,T47

 LINE       700
 EXPRESSION (dbus_addr_en_0_we & dbus_regwen_0_qs)
             --------1--------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T1,T20,T9
1	1	Covered	T4,T46,T59

 LINE       732
 EXPRESSION (dbus_addr_en_1_we & dbus_regwen_1_qs)
             --------1--------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T1,T31,T44
1	1	Covered	T89,T47,T48

 LINE       764
 EXPRESSION (dbus_addr_matching_0_we & dbus_regwen_0_qs)
             -----------1-----------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T20,T9,T23
1	1	Covered	T59,T47,T48

 LINE       796
 EXPRESSION (dbus_addr_matching_1_we & dbus_regwen_1_qs)
             -----------1-----------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T1,T20,T8
1	1	Covered	T4,T6,T86

 LINE       828
 EXPRESSION (dbus_remap_addr_0_we & dbus_regwen_0_qs)
             ----------1---------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T20,T9,T23
1	1	Covered	T4,T59,T61

 LINE       860
 EXPRESSION (dbus_remap_addr_1_we & dbus_regwen_1_qs)
             ----------1---------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T1,T20,T23
1	1	Covered	T83,T47,T48

 LINE       1178
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_ALERT_TEST_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T4,T5

 LINE       1179
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_SW_RECOV_ERR_OFFSET)
            ----------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T7,T4,T5
1	Covered	T5,T6,T86

 LINE       1180
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_SW_FATAL_ERR_OFFSET)
            ----------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T7,T4,T5
1	Covered	T5,T42,T46

 LINE       1181
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_IBUS_REGWEN_0_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T7,T4,T5
1	Covered	T4,T5,T6

 LINE       1182
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_IBUS_REGWEN_1_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T7,T4,T5
1	Covered	T5,T42,T60

 LINE       1183
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_IBUS_ADDR_EN_0_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T7,T4,T5
1	Covered	T5,T6,T46

 LINE       1184
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_IBUS_ADDR_EN_1_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T7,T4,T5
1	Covered	T4,T5,T6

 LINE       1185
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_IBUS_ADDR_MATCHING_0_OFFSET)
            --------------------------------------1-------------------------------------

-1-	Status	Tests
0	Covered	T7,T4,T5
1	Covered	T4,T5,T6

 LINE       1186
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_IBUS_ADDR_MATCHING_1_OFFSET)
            --------------------------------------1-------------------------------------

-1-	Status	Tests
0	Covered	T7,T4,T5
1	Covered	T4,T5,T42

 LINE       1187
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_IBUS_REMAP_ADDR_0_OFFSET)
            ------------------------------------1------------------------------------

-1-	Status	Tests
0	Covered	T7,T4,T5
1	Covered	T4,T5,T42

 LINE       1188
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_IBUS_REMAP_ADDR_1_OFFSET)
            ------------------------------------1------------------------------------

-1-	Status	Tests
0	Covered	T7,T4,T5
1	Covered	T4,T5,T42

 LINE       1189
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_DBUS_REGWEN_0_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T7,T4,T5
1	Covered	T4,T5,T42

 LINE       1190
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_DBUS_REGWEN_1_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T7,T4,T5
1	Covered	T4,T5,T6

 LINE       1191
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_DBUS_ADDR_EN_0_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T7,T4,T5
1	Covered	T4,T5,T42

 LINE       1192
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_DBUS_ADDR_EN_1_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T7,T4,T5
1	Covered	T4,T5,T42

 LINE       1193
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_DBUS_ADDR_MATCHING_0_OFFSET)
            --------------------------------------1-------------------------------------

-1-	Status	Tests
0	Covered	T7,T4,T5
1	Covered	T4,T5,T42

 LINE       1194
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_DBUS_ADDR_MATCHING_1_OFFSET)
            --------------------------------------1-------------------------------------

-1-	Status	Tests
0	Covered	T7,T4,T5
1	Covered	T4,T5,T6

 LINE       1195
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_DBUS_REMAP_ADDR_0_OFFSET)
            ------------------------------------1------------------------------------

-1-	Status	Tests
0	Covered	T7,T4,T5
1	Covered	T4,T5,T42

 LINE       1196
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_DBUS_REMAP_ADDR_1_OFFSET)
            ------------------------------------1------------------------------------

-1-	Status	Tests
0	Covered	T7,T4,T5
1	Covered	T4,T5,T42

 LINE       1197
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_NMI_ENABLE_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T7,T4,T5
1	Covered	T4,T5,T6

 LINE       1198
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_NMI_STATE_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T7,T4,T5
1	Covered	T4,T5,T6

 LINE       1199
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_ERR_STATUS_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T7,T4,T5
1	Covered	T5,T6,T42

 LINE       1200
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_RND_DATA_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T7,T4,T5
1	Covered	T4,T5,T6

 LINE       1201
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_RND_STATUS_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T7,T4,T5
1	Covered	T4,T5,T42

 LINE       1202
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_FPGA_INFO_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T7,T4,T5
1	Covered	T4,T5,T6

 LINE       1205
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T7,T4,T5
1	Covered	T4,T5,T6

 LINE       1205
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T7,T4,T5
0	1	Covered	T4,T6,T46
1	0	Covered	T4,T5,T6

 LINE       1209
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1 & (~reg_be))))) | (addr_hit[13] & ((|(4'b1 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | (addr_hit[15] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[19] & ((|(4'b1 & (~reg_be))))) | (addr_hit[20] & ((|(4'b1 & (~reg_be))))) | (addr_hit[21] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[22] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[23] & ((|(4'b1 & (~reg_be))))) | (addr_hit[24] & ((|(4'b1111 & (~reg_be)))))))

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T4,T6,T46
1	1	Covered	T4,T6,T46

 LINE       1209
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b1 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b1 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b1 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b1111 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | 
     19  (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | 
     20  (addr_hit[19] & ((|(4'b1 & (~reg_be))))) | 
     21  (addr_hit[20] & ((|(4'b1 & (~reg_be))))) | 
     22  (addr_hit[21] & ((|(4'b0011 & (~reg_be))))) | 
     23  (addr_hit[22] & ((|(4'b1111 & (~reg_be))))) | 
     24  (addr_hit[23] & ((|(4'b1 & (~reg_be))))) | 
     25  (addr_hit[24] & ((|(4'b1111 & (~reg_be))))))

Sensitive Expression == 1	Status	Tests
ALL ZEROS	Covered	T4,T5,T6
25 (addr_hit[24] & ((|(4'...	Covered	T4,T5,T6
24 (addr_hit[23] & ((|(4'...	Covered	T5,T42,T46
23 (addr_hit[22] & ((|(4'...	Covered	T4,T5,T6
22 (addr_hit[21] & ((|(4'...	Covered	T5,T6,T42
21 (addr_hit[20] & ((|(4'...	Covered	T5,T6,T42
20 (addr_hit[19] & ((|(4'...	Covered	T4,T5,T6
19 (addr_hit[18] & ((|(4'...	Covered	T4,T5,T42
18 (addr_hit[17] & ((|(4'...	Covered	T5,T42,T46
17 (addr_hit[16] & ((|(4'...	Covered	T4,T5,T6
16 (addr_hit[15] & ((|(4'...	Covered	T4,T5,T42
15 (addr_hit[14] & ((|(4'...	Covered	T4,T5,T42
14 (addr_hit[13] & ((|(4'...	Covered	T5,T42,T60
13 (addr_hit[12] & ((|(4'...	Covered	T4,T5,T6
12 (addr_hit[11] & ((|(4'...	Covered	T4,T5,T46
11 (addr_hit[10] & ((|(4'...	Covered	T4,T5,T42
10 (addr_hit[9] & ((|(4'b...	Covered	T4,T5,T42
9 (addr_hit[8] & ((|(4'b...	Covered	T4,T5,T42
8 (addr_hit[7] & ((|(4'b...	Covered	T4,T5,T6
7 (addr_hit[6] & ((|(4'b...	Covered	T4,T5,T6
6 (addr_hit[5] & ((|(4'b...	Covered	T5,T6,T46
5 (addr_hit[4] & ((|(4'b...	Covered	T5,T42,T60
4 (addr_hit[3] & ((|(4'b...	Covered	T4,T5,T6
3 (addr_hit[2] & ((|(4'b...	Covered	T5,T46,T60
2 (addr_hit[1] & ((|(4'b...	Covered	T5,T83,T47
1 (addr_hit[0] & ((|(4'b...	Covered	T7,T4,T5

 LINE       1209
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T6,T46
1	1	Covered	T7,T4,T5

 LINE       1209
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T6,T86
1	1	Covered	T5,T83,T47

 LINE       1209
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T59
1	1	Covered	T5,T46,T60

 LINE       1209
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T6,T59
1	1	Covered	T4,T5,T6

 LINE       1209
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T61,T82
1	1	Covered	T5,T42,T60

 LINE       1209
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T6,T46
1	1	Covered	T5,T6,T46

 LINE       1209
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T6,T42
1	1	Covered	T4,T5,T6

 LINE       1209
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       1209
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T60,T83
1	1	Covered	T4,T5,T42

 LINE       1209
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T47,T48
1	1	Covered	T4,T5,T42

 LINE       1209
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T4,T42,T82
1	1	Covered	T4,T5,T42

 LINE       1209
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T83
1	1	Covered	T4,T5,T46

 LINE       1209
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T58
1	1	Covered	T4,T5,T6

 LINE       1209
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T4,T5,T46
1	1	Covered	T5,T42,T60

 LINE       1209
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T89
1	1	Covered	T4,T5,T42

 LINE       1209
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T59,T47,T48
1	1	Covered	T4,T5,T42

 LINE       1209
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       1209
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T4,T5,T59
1	1	Covered	T5,T42,T46

 LINE       1209
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T42,T83,T47
1	1	Covered	T4,T5,T42

 LINE       1209
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T42,T59
1	1	Covered	T4,T5,T6

 LINE       1209
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T4,T5,T42
1	1	Covered	T5,T6,T42

 LINE       1209
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T58,T59
1	1	Covered	T5,T6,T42

 LINE       1209
 SUB-EXPRESSION (addr_hit[22] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T5,T60,T83
1	1	Covered	T4,T5,T6

 LINE       1209
 SUB-EXPRESSION (addr_hit[23] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T4,T5,T59
1	1	Covered	T5,T42,T46

 LINE       1209
 SUB-EXPRESSION (addr_hit[24] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T5
1	0	Covered	T4,T5,T47
1	1	Covered	T4,T5,T6

 LINE       1238
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T46
1	0	1	Covered	T7,T4,T5
1	1	0	Covered	T47,T70,T87
1	1	1	Covered	T6,T46,T59

 LINE       1247
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T46
1	0	1	Covered	T83,T47,T84
1	1	0	Covered	T84,T2,T78
1	1	1	Covered	T6,T86,T47

 LINE       1250
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T46
1	0	1	Covered	T46,T60,T61
1	1	0	Covered	T61,T47,T2
1	1	1	Covered	T59,T82,T83

 LINE       1253
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T46
1	0	1	Covered	T4,T6,T82
1	1	0	Covered	T82,T89,T47
1	1	1	Covered	T6,T59,T83

 LINE       1256
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T46
1	0	1	Covered	T60,T82,T47
1	1	0	Covered	T61,T83,T47
1	1	1	Covered	T61,T82,T47

 LINE       1259
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T46
1	0	1	Covered	T6,T46,T59
1	1	0	Covered	T82,T47,T48
1	1	1	Covered	T46,T61,T86

 LINE       1262
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T46
1	0	1	Covered	T4,T6,T61
1	1	0	Covered	T59,T2,T140
1	1	1	Covered	T6,T59,T60

 LINE       1265
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T46
1	0	1	Covered	T4,T6,T46
1	1	0	Covered	T6,T61,T47
1	1	1	Covered	T4,T6,T46

 LINE       1268
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T46
1	0	1	Covered	T4,T46,T47
1	1	0	Covered	T4,T60,T82
1	1	1	Covered	T60,T83,T47

 LINE       1271
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T46
1	0	1	Covered	T4,T46,T60
1	1	0	Covered	T61,T82,T76
1	1	1	Covered	T47,T48,T1

 LINE       1274
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T46
1	0	1	Covered	T4,T61,T82
1	1	0	Covered	T47,T2,T68
1	1	1	Covered	T4,T82,T47

 LINE       1277
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T46
1	0	1	Covered	T46,T61,T47
1	1	0	Covered	T4,T47,T48
1	1	1	Covered	T83,T47,T1

 LINE       1280
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T46
1	0	1	Covered	T4,T60,T61
1	1	0	Covered	T6,T86,T83
1	1	1	Covered	T58,T82,T86

 LINE       1283
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T46
1	0	1	Covered	T60,T82,T83
1	1	0	Covered	T84,T87,T71
1	1	1	Covered	T4,T46,T59

 LINE       1286
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T46
1	0	1	Covered	T4,T59,T60
1	1	0	Covered	T4,T46,T47
1	1	1	Covered	T89,T47,T48

 LINE       1289
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T46
1	0	1	Covered	T59,T83,T47
1	1	0	Covered	T4,T89,T47
1	1	1	Covered	T59,T47,T48

 LINE       1292
 EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T46
1	0	1	Covered	T4,T6,T46
1	1	0	Covered	T61,T83,T47
1	1	1	Covered	T4,T6,T86

 LINE       1295
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T46
1	0	1	Covered	T46,T82,T86
1	1	0	Covered	T46,T83,T47
1	1	1	Covered	T4,T59,T61

 LINE       1298
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T46
1	0	1	Covered	T4,T59,T60
1	1	0	Covered	T4,T47,T48
1	1	1	Covered	T83,T47,T48

 LINE       1301
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T46
1	0	1	Covered	T4,T6,T46
1	1	0	Covered	T59,T47,T48
1	1	1	Covered	T59,T60,T83

 LINE       1306
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T46
1	0	1	Covered	T6,T46,T82
1	1	0	Covered	T47,T48,T84
1	1	1	Covered	T4,T46,T58

 LINE       1311
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T46
1	0	1	Covered	T6,T59,T86
1	1	0	Covered	T47,T48,T76
1	1	1	Covered	T58,T60,T47

 LINE       1320
 EXPRESSION (addr_hit[22] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T46
1	0	1	Covered	T60,T83,T141
1	1	0	Not Covered
1	1	1	Covered	T4,T6,T59

 LINE       1321
 EXPRESSION (addr_hit[23] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T46
1	0	1	Covered	T4,T46,T59
1	1	0	Covered	T149
1	1	1	Covered	T60,T47,T48

 LINE       1322
 EXPRESSION (addr_hit[24] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T46
1	0	1	Covered	T4,T82,T47
1	1	0	Not Covered
1	1	1	Covered	T4,T6,T47

---

Branch Coverage for Module : rv_core_ibex_cfg_reg_top

	Line No.	Total	Covered	Percent
Branches		35	34	97.14
TERNARY	1205	2	2	100.00
IF	76	3	2	66.67
TERNARY	133	2	2	100.00
IF	139	2	2	100.00
CASE	1357	26	26	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex_cfg_reg_top.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex_cfg_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	1205	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T7,T4,T5

	LineNo.	Expression
-1-:	76	if ((!rst_ni))
-2-:	78	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	133	((tl_i.a_address[(AW - 1):0] inside {[128:159]})) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T7,T4,T5

	LineNo.	Expression
-1-:	139	if (intg_err)

Branches:

-1-	Status	Tests
1	Covered	T5,T42,T148
0	Covered	T7,T4,T5

	LineNo.	Expression
-1-:	1357	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T7,T4,T5
addr_hit[1]	Covered	T5,T6,T86
addr_hit[2]	Covered	T5,T42,T46
addr_hit[3]	Covered	T4,T5,T6
addr_hit[4]	Covered	T5,T42,T60
addr_hit[5]	Covered	T5,T6,T46
addr_hit[6]	Covered	T4,T5,T6
addr_hit[7]	Covered	T4,T5,T6
addr_hit[8]	Covered	T4,T5,T42
addr_hit[9]	Covered	T4,T5,T42
addr_hit[10]	Covered	T4,T5,T42
addr_hit[11]	Covered	T4,T5,T42
addr_hit[12]	Covered	T4,T5,T6
addr_hit[13]	Covered	T4,T5,T42
addr_hit[14]	Covered	T4,T5,T42
addr_hit[15]	Covered	T4,T5,T42
addr_hit[16]	Covered	T4,T5,T6
addr_hit[17]	Covered	T4,T5,T42
addr_hit[18]	Covered	T4,T5,T42
addr_hit[19]	Covered	T4,T5,T6
addr_hit[20]	Covered	T4,T5,T6
addr_hit[21]	Covered	T5,T6,T42
addr_hit[22]	Covered	T4,T5,T6
addr_hit[23]	Covered	T4,T5,T42
addr_hit[24]	Covered	T4,T5,T6
default	Covered	T4,T5,T6

---

Assert Coverage for Module : rv_core_ibex_cfg_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	87808980	28228	0	0
reAfterRv	87808980	28228	0	0
rePulse	87808980	22891	0	0
wePulse	87808980	5337	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	87808980	28228	0	0
T1	118170	266	0	0
T2	188507	17	0	0
T3	106965	10	0	0
T8	170332	53	0	0
T9	138516	244	0	0
T10	75371	25	0	0
T20	348452	104	0	0
T39	190132	12	0	0
T40	703998	0	0	0
T41	168850	18	0	0
T50	0	50	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	87808980	28228	0	0
T1	118170	266	0	0
T2	188507	17	0	0
T3	106965	10	0	0
T8	170332	53	0	0
T9	138516	244	0	0
T10	75371	25	0	0
T20	348452	104	0	0
T39	190132	12	0	0
T40	703998	0	0	0
T41	168850	18	0	0
T50	0	50	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	87808980	22891	0	0
T1	118170	137	0	0
T2	188507	0	0	0
T8	170332	29	0	0
T9	138516	113	0	0
T10	75371	25	0	0
T20	348452	56	0	0
T23	128123	119	0	0
T31	0	128	0	0
T40	703998	0	0	0
T41	168850	0	0	0
T50	182237	50	0	0
T51	0	25	0	0
T53	0	25	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	87808980	5337	0	0
T1	118170	129	0	0
T2	188507	17	0	0
T3	106965	10	0	0
T8	170332	24	0	0
T9	138516	131	0	0
T20	348452	48	0	0
T23	128123	106	0	0
T31	0	116	0	0
T39	190132	12	0	0
T40	703998	0	0	0
T41	168850	18	0	0