Unified Coverage Report :: Module :: rv_core_addr_trans

Module : rv_core_addr_trans

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
68.04	95.77	58.33			50.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_addr_trans.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans	47.89	43.66	50.00			50.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans	56.92	95.77	25.00			50.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
47.89	43.66	50.00			50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
21.34	35.63	25.93			16.67	7.14

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
55.88	48.24	46.43	62.34		75.00	47.37	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_sel_region	3.45	0.00	6.67			0.00	7.14

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
56.92	95.77	25.00			50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
43.82	88.51	29.63			50.00	7.14

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
55.88	48.24	46.43	62.34		75.00	47.37	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_sel_region	36.68	56.25	33.33			50.00	7.14

Line Coverage for Module : rv_core_addr_trans

	Line No.	Total	Covered	Percent
TOTAL		71	68	95.77
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	46	1	0	0.00
CONT_ASSIGN	46	1	0	0.00
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	83	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_addr_trans.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_addr_trans.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
41	62	62
45	2	2
46	0	2
51	2	2
76	1	1
82	1	1
83	0	1

---

Cond Coverage for Module : rv_core_addr_trans

	Total	Covered	Percent
Conditions	12	7	58.33
Logical	12	7	58.33
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (region_cfg_i[0].en & ((region_cfg_i[0].matching_region & input_masks[0]) == (addr_i & input_masks[0])))
             ---------1--------   ----------------------------------------2----------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Not Covered
1	1	Not Covered

 LINE       51
 SUB-EXPRESSION ((region_cfg_i[0].matching_region & input_masks[0]) == (addr_i & input_masks[0]))
                ----------------------------------------1----------------------------------------

-1-	Status	Tests
0	Covered	T14,T15,T16
1	Covered	T14,T15,T16

 LINE       51
 EXPRESSION (region_cfg_i[1].en & ((region_cfg_i[1].matching_region & input_masks[1]) == (addr_i & input_masks[1])))
             ---------1--------   ----------------------------------------2----------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Not Covered
1	1	Not Covered

 LINE       51
 SUB-EXPRESSION ((region_cfg_i[1].matching_region & input_masks[1]) == (addr_i & input_masks[1]))
                ----------------------------------------1----------------------------------------

-1-	Status	Tests
0	Covered	T14,T15,T16
1	Covered	T14,T15,T16

 LINE       76
 EXPRESSION (sel_match ? (((addr_i & sel_region.output_mask) | sel_region.remap_addr)) : addr_i)
             ----1----

-1-	Status	Tests
0	Covered	T14,T15,T16
1	Not Covered

---

Branch Coverage for Module : rv_core_addr_trans

	Line No.	Total	Covered	Percent
Branches		2	1	50.00
TERNARY	76	2	1	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_addr_trans.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_addr_trans.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	(sel_match) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T14,T15,T16

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans

	Line No.	Total	Covered	Percent
TOTAL		71	31	43.66
CONT_ASSIGN	41	1	0	0.00
CONT_ASSIGN	41	1	0	0.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	0	0.00
CONT_ASSIGN	41	1	0	0.00
CONT_ASSIGN	41	1	0	0.00
CONT_ASSIGN	41	1	0	0.00
CONT_ASSIGN	41	1	0	0.00
CONT_ASSIGN	41	1	0	0.00
CONT_ASSIGN	41	1	0	0.00
CONT_ASSIGN	41	1	0	0.00
CONT_ASSIGN	41	1	0	0.00
CONT_ASSIGN	41	1	0	0.00
CONT_ASSIGN	41	1	0	0.00
CONT_ASSIGN	41	1	0	0.00
CONT_ASSIGN	41	1	0	0.00
CONT_ASSIGN	41	1	0	0.00
CONT_ASSIGN	41	1	0	0.00
CONT_ASSIGN	41	1	0	0.00
CONT_ASSIGN	41	1	0	0.00
CONT_ASSIGN	41	1	0	0.00
CONT_ASSIGN	41	1	0	0.00
CONT_ASSIGN	41	1	0	0.00
CONT_ASSIGN	41	1	0	0.00
CONT_ASSIGN	41	1	0	0.00
CONT_ASSIGN	41	1	0	0.00
CONT_ASSIGN	41	1	0	0.00
CONT_ASSIGN	41	1	0	0.00
CONT_ASSIGN	41	1	0	0.00
CONT_ASSIGN	41	1	0	0.00
CONT_ASSIGN	41	1	0	0.00
CONT_ASSIGN	41	1	0	0.00
CONT_ASSIGN	41	1	0	0.00
CONT_ASSIGN	41	1	0	0.00
CONT_ASSIGN	45	1	0	0.00
CONT_ASSIGN	45	1	0	0.00
CONT_ASSIGN	46	1	0	0.00
CONT_ASSIGN	46	1	0	0.00
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	51	1	0	0.00
CONT_ASSIGN	76	1	0	0.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	83	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_addr_trans.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_addr_trans.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
41	29	62
45	0	2
46	0	2
51	1	2
76	0	1
82	1	1
83	0	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans

	Total	Covered	Percent
Conditions	12	6	50.00
Logical	12	6	50.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (region_cfg_i[0].en & ((region_cfg_i[0].matching_region & input_masks[0]) == (addr_i & input_masks[0])))
             ---------1--------   ----------------------------------------2----------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Not Covered
1	1	Not Covered

 LINE       51
 SUB-EXPRESSION ((region_cfg_i[0].matching_region & input_masks[0]) == (addr_i & input_masks[0]))
                ----------------------------------------1----------------------------------------

-1-	Status	Tests
0	Covered	T19
1	Covered	T14,T15,T16

 LINE       51
 EXPRESSION (region_cfg_i[1].en & ((region_cfg_i[1].matching_region & input_masks[1]) == (addr_i & input_masks[1])))
             ---------1--------   ----------------------------------------2----------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Not Covered
1	1	Not Covered

 LINE       51
 SUB-EXPRESSION ((region_cfg_i[1].matching_region & input_masks[1]) == (addr_i & input_masks[1]))
                ----------------------------------------1----------------------------------------

-1-	Status	Tests
0	Not Covered
1	Covered	T14,T15,T16

 LINE       76
 EXPRESSION (sel_match ? (((addr_i & sel_region.output_mask) | sel_region.remap_addr)) : addr_i)
             ----1----

-1-	Status	Tests
0	Covered	T14,T15,T16
1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans

	Line No.	Total	Covered	Percent
Branches		2	1	50.00
TERNARY	76	2	1	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_addr_trans.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_addr_trans.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	(sel_match) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T14,T15,T16

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans

	Line No.	Total	Covered	Percent
TOTAL		71	68	95.77
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	46	1	0	0.00
CONT_ASSIGN	46	1	0	0.00
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	83	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_addr_trans.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_addr_trans.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
41	62	62
45	2	2
46	0	2
51	2	2
76	1	1
82	1	1
83	0	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans

	Total	Covered	Percent
Conditions	12	3	25.00
Logical	12	3	25.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (region_cfg_i[0].en & ((region_cfg_i[0].matching_region & input_masks[0]) == (addr_i & input_masks[0])))
             ---------1--------   ----------------------------------------2----------------------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       51
 SUB-EXPRESSION ((region_cfg_i[0].matching_region & input_masks[0]) == (addr_i & input_masks[0]))
                ----------------------------------------1----------------------------------------

-1-	Status	Tests
0	Covered	T14,T15,T16
1	Not Covered

 LINE       51
 EXPRESSION (region_cfg_i[1].en & ((region_cfg_i[1].matching_region & input_masks[1]) == (addr_i & input_masks[1])))
             ---------1--------   ----------------------------------------2----------------------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       51
 SUB-EXPRESSION ((region_cfg_i[1].matching_region & input_masks[1]) == (addr_i & input_masks[1]))
                ----------------------------------------1----------------------------------------

-1-	Status	Tests
0	Covered	T14,T15,T16
1	Not Covered

 LINE       76
 EXPRESSION (sel_match ? (((addr_i & sel_region.output_mask) | sel_region.remap_addr)) : addr_i)
             ----1----

-1-	Status	Tests
0	Covered	T14,T15,T16
1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans

	Line No.	Total	Covered	Percent
Branches		2	1	50.00
TERNARY	76	2	1	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_addr_trans.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_addr_trans.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	(sel_match) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T14,T15,T16