Unified Coverage Report :: Module

Module : rv_plic_target

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
57.41	55.56	50.00			66.67

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rv_plic_component_0.1/rtl/rv_plic_target.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target	57.41	55.56	50.00			66.67

Module Instance : tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
57.41	55.56	50.00			66.67

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.95	0.40	38.62			58.13	66.67

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
36.71	0.00	0.00	94.68		0.00	88.89	u_rv_plic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_max_tree	40.84	0.00	38.60			58.09	66.67

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rv_plic_target

	Line No.	Total	Covered	Percent
TOTAL		9	5	55.56
CONT_ASSIGN	58	1	0	0.00
CONT_ASSIGN	59	1	0	0.00
ALWAYS	62	5	5	100.00
CONT_ASSIGN	71	1	0	0.00
CONT_ASSIGN	72	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_plic_component_0.1/rtl/rv_plic_target.sv' or '../src/lowrisc_ip_rv_plic_component_0.1/rtl/rv_plic_target.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	0	1
59	0	1
62	1	1
63	1	1
64	1	1
66	1	1
67	1	1
71	0	1
72	0	1

Cond Coverage for Module : rv_plic_target

	Total	Covered	Percent
Conditions	4	2	50.00
Logical	4	2	50.00
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION ((max_value > threshold_i) ? max_valid : 1'b0)
             ------------1------------

-1-	Status	Tests
0	Covered	T14,T15,T16
1	Not Covered

 LINE       59
 EXPRESSION (max_valid ? max_idx : '0)
             ----1----

-1-	Status	Tests
0	Covered	T14,T15,T16
1	Not Covered

Branch Coverage for Module : rv_plic_target

	Line No.	Total	Covered	Percent
Branches		6	4	66.67
TERNARY	58	2	1	50.00
TERNARY	59	2	1	50.00
IF	62	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_plic_component_0.1/rtl/rv_plic_target.sv' or '../src/lowrisc_ip_rv_plic_component_0.1/rtl/rv_plic_target.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	58	((max_value > threshold_i)) ?

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T14,T15,T16



	LineNo.	Expression
-1-:	59	(max_valid) ?

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T14,T15,T16



	LineNo.	Expression
-1-:	62	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T14,T15,T16
0	Covered	T14,T15,T16