Unified Coverage Report :: Module :: prim_mubi4_sync

Module : prim_mubi4_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync	100.00						100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.93	96.37	100.00			93.22	94.12	u_pinmux_strap_sampling

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : prim_mubi4_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	11	11	0	0
OutputsKnown_A	1030903	1021378	0	0
gen_no_flops.OutputDelay_A	1030903	1021378	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11	11	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030903	1021378	0	0
T14	10609	9467	0	0
T15	10432	9194	0	0
T16	10144	9350	0	0
T17	263894	263078	0	0
T18	266870	265792	0	0
T19	245101	244380	0	0
T24	10447	9402	0	0
T25	9718	9155	0	0
T26	10233	9387	0	0
T27	9897	9274	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030903	1021378	0	0
T14	10609	9467	0	0
T15	10432	9194	0	0
T16	10144	9350	0	0
T17	263894	263078	0	0
T18	266870	265792	0	0
T19	245101	244380	0	0
T24	10447	9402	0	0
T25	9718	9155	0	0
T26	10233	9387	0	0
T27	9897	9274	0	0

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	11	11	0	0
OutputsKnown_A	1030903	1021378	0	0
gen_no_flops.OutputDelay_A	1030903	1021378	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11	11	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030903	1021378	0	0
T14	10609	9467	0	0
T15	10432	9194	0	0
T16	10144	9350	0	0
T17	263894	263078	0	0
T18	266870	265792	0	0
T19	245101	244380	0	0
T24	10447	9402	0	0
T25	9718	9155	0	0
T26	10233	9387	0	0
T27	9897	9274	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030903	1021378	0	0
T14	10609	9467	0	0
T15	10432	9194	0	0
T16	10144	9350	0	0
T17	263894	263078	0	0
T18	266870	265792	0	0
T19	245101	244380	0	0
T24	10447	9402	0	0
T25	9718	9155	0	0
T26	10233	9387	0	0
T27	9897	9274	0	0