Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1084327	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1774593

1

T11

2006

T12

1962

T13

2029

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2206118	1			T11	2964		T12	3046		T13	2915
values[0x0]	308315	1			T11	1123		T12	1144		T13	1152
values[0x1]	344487	1			T11	1187		T12	1166		T13	1158

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	801659	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2057261

1

T11

2944

T12

2859

T13

2904

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	44513	1			T11	84		T12	46		T13	86
valid_sources[0x01]	45372	1			T11	75		T12	94		T13	59
valid_sources[0x02]	45131	1			T11	65		T12	100		T13	62
valid_sources[0x03]	44460	1			T11	74		T12	63		T13	48
valid_sources[0x04]	44543	1			T11	68		T12	91		T13	50
valid_sources[0x05]	45455	1			T11	64		T12	53		T13	93
valid_sources[0x06]	45620	1			T11	104		T12	105		T13	128
valid_sources[0x07]	45529	1			T11	79		T12	68		T13	75
valid_sources[0x08]	44841	1			T11	71		T12	76		T13	90
valid_sources[0x09]	42933	1			T11	100		T12	93		T13	71
valid_sources[0x0a]	43271	1			T11	58		T12	114		T13	65
valid_sources[0x0b]	44827	1			T11	76		T12	87		T13	79
valid_sources[0x0c]	45238	1			T11	84		T12	80		T13	76
valid_sources[0x0d]	44354	1			T11	114		T12	73		T13	65
valid_sources[0x0e]	44231	1			T11	85		T12	108		T13	77
valid_sources[0x0f]	44063	1			T11	96		T12	99		T13	41
valid_sources[0x10]	44736	1			T11	96		T12	78		T13	40
valid_sources[0x11]	44482	1			T11	73		T12	69		T13	100
valid_sources[0x12]	46117	1			T11	81		T12	53		T13	131
valid_sources[0x13]	43650	1			T11	96		T12	99		T13	91
valid_sources[0x14]	44257	1			T11	87		T12	92		T13	68
valid_sources[0x15]	44549	1			T11	79		T12	90		T13	62
valid_sources[0x16]	44356	1			T11	87		T12	103		T13	80
valid_sources[0x17]	43933	1			T11	101		T12	85		T13	83
valid_sources[0x18]	44807	1			T11	90		T12	87		T13	94
valid_sources[0x19]	44035	1			T11	75		T12	140		T13	82
valid_sources[0x1a]	45461	1			T11	68		T12	82		T13	64
valid_sources[0x1b]	44410	1			T11	78		T12	61		T13	64
valid_sources[0x1c]	44378	1			T11	55		T12	79		T13	99
valid_sources[0x1d]	45075	1			T11	79		T12	75		T13	91
valid_sources[0x1e]	44463	1			T11	77		T12	71		T13	83
valid_sources[0x1f]	44379	1			T11	90		T12	121		T13	100
valid_sources[0x20]	43656	1			T11	108		T12	68		T13	55

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1267428

1

T11

746

T12

725

T13

763

values[0x0]

all_enables

biggest_size

262226

1

T11

669

T12

667

T13

685

values[0x1]

all_enables

biggest_size

244939

1

T11

591

T12

570

T13

581

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2884708	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

455997

1

T14

25

T15

10

T16

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1129542	1			T14	63		T15	46		T16	12
values[0x0]	1078970	1			T14	53		T15	4		T16	5
values[0x1]	1132193	1			T14	62		T15	46		T16	27

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2234083	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1106622

1

T14

54

T15

33

T16

15

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	51992	1			T15	4		T17	9		T55	10
valid_sources[0x01]	52260	1			T15	1		T55	19		T56	32
valid_sources[0x02]	51727	1			T14	15		T15	1		T55	19
valid_sources[0x03]	51776	1			T14	10		T15	1		T16	1
valid_sources[0x04]	52378	1			T14	2		T15	1		T16	1
valid_sources[0x05]	51218	1			T14	1		T15	1		T16	1
valid_sources[0x06]	51329	1			T17	7		T55	23		T34	2
valid_sources[0x07]	51468	1			T14	6		T15	1		T16	1
valid_sources[0x08]	52859	1			T15	1		T16	3		T17	6
valid_sources[0x09]	53650	1			T14	2		T15	2		T16	2
valid_sources[0x0a]	52038	1			T15	1		T16	1		T55	7
valid_sources[0x0b]	51279	1			T15	2		T17	1		T55	8
valid_sources[0x0c]	52668	1			T14	1		T15	3		T17	11
valid_sources[0x0d]	52868	1			T15	1		T18	2		T55	10
valid_sources[0x0e]	52888	1			T15	2		T17	9		T18	8
valid_sources[0x0f]	52245	1			T14	8		T15	1		T18	17
valid_sources[0x10]	52395	1			T14	4		T15	1		T16	2
valid_sources[0x11]	52002	1			T14	7		T16	1		T18	3
valid_sources[0x12]	52860	1			T15	1		T17	10		T18	20
valid_sources[0x13]	51805	1			T14	8		T16	2		T55	33
valid_sources[0x14]	52440	1			T15	3		T16	1		T18	1
valid_sources[0x15]	53768	1			T15	3		T16	6		T17	3
valid_sources[0x16]	52964	1			T15	2		T18	1		T55	19
valid_sources[0x17]	52691	1			T15	2		T55	8		T56	32
valid_sources[0x18]	51738	1			T15	1		T16	1		T17	3
valid_sources[0x19]	51508	1			T14	7		T15	1		T17	6
valid_sources[0x1a]	51998	1			T14	3		T17	9		T18	6
valid_sources[0x1b]	52424	1			T14	5		T18	1		T55	23
valid_sources[0x1c]	51605	1			T14	10		T15	2		T17	2
valid_sources[0x1d]	52177	1			T14	2		T16	2		T18	6
valid_sources[0x1e]	51910	1			T15	1		T18	12		T55	14
valid_sources[0x1f]	52305	1			T14	1		T15	1		T17	5
valid_sources[0x20]	51852	1			T14	2		T15	1		T16	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

47525

1

T14

3

T15

3

T18

5

values[0x0]

all_enables

biggest_size

360729

1

T14

22

T15

1

T16

1

values[0x1]

all_enables

biggest_size

47743

1

T15

6

T16

2

T18

5

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3078616	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

500930

1

T14

22

T15

8

T16

5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1225122	1			T14	68		T15	37		T16	13
values[0x0]	1129146	1			T14	57		T15	9		T16	6
values[0x1]	1225278	1			T14	49		T15	44		T16	22

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2363539	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1216007

1

T14

57

T15

34

T16

18

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	56641	1			T14	1		T15	2		T17	2
valid_sources[0x01]	56090	1			T14	3		T15	2		T18	7
valid_sources[0x02]	56586	1			T14	2		T15	1		T16	1
valid_sources[0x03]	55487	1			T14	3		T15	2		T16	2
valid_sources[0x04]	55676	1			T14	1		T15	1		T18	8
valid_sources[0x05]	55917	1			T14	4		T16	1		T17	2
valid_sources[0x06]	54611	1			T14	6		T15	3		T16	2
valid_sources[0x07]	57213	1			T15	2		T18	12		T55	20
valid_sources[0x08]	55839	1			T14	3		T15	3		T18	6
valid_sources[0x09]	57105	1			T14	4		T15	1		T16	2
valid_sources[0x0a]	56418	1			T14	1		T17	3		T18	4
valid_sources[0x0b]	56013	1			T14	4		T17	3		T18	5
valid_sources[0x0c]	55864	1			T14	3		T15	2		T16	1
valid_sources[0x0d]	56715	1			T16	1		T18	6		T55	6
valid_sources[0x0e]	55853	1			T14	3		T15	1		T16	1
valid_sources[0x0f]	55748	1			T14	1		T15	2		T17	6
valid_sources[0x10]	56922	1			T17	2		T18	3		T55	19
valid_sources[0x11]	55050	1			T14	2		T16	1		T17	2
valid_sources[0x12]	55531	1			T14	5		T15	3		T16	2
valid_sources[0x13]	55810	1			T14	2		T15	3		T18	8
valid_sources[0x14]	56750	1			T14	6		T16	1		T18	2
valid_sources[0x15]	55822	1			T14	2		T18	4		T56	20
valid_sources[0x16]	55488	1			T14	2		T15	1		T16	1
valid_sources[0x17]	55943	1			T14	3		T15	1		T17	4
valid_sources[0x18]	55071	1			T14	2		T15	2		T17	6
valid_sources[0x19]	56156	1			T14	2		T15	3		T16	3
valid_sources[0x1a]	55337	1			T14	2		T15	1		T16	1
valid_sources[0x1b]	56448	1			T14	6		T15	1		T17	8
valid_sources[0x1c]	56525	1			T14	2		T15	1		T16	2
valid_sources[0x1d]	55305	1			T14	4		T15	1		T16	2
valid_sources[0x1e]	55848	1			T14	4		T15	5		T18	4
valid_sources[0x1f]	55584	1			T15	1		T18	7		T55	6
valid_sources[0x20]	55557	1			T14	2		T15	4		T17	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

52685

1

T14

1

T15

1

T16

1

values[0x0]

all_enables

biggest_size

395685

1

T14

20

T15

4

T16

2

values[0x1]

all_enables

biggest_size

52560

1

T14

1

T15

3

T16

2

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2907090	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

458609

1

T14

24

T15

13

T16

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1140895	1			T14	59		T15	57		T16	19
values[0x0]	1084192	1			T14	57		T15	6		T16	5
values[0x1]	1140612	1			T14	69		T15	38		T16	19

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2250740	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1114959

1

T14

61

T15

41

T16

20

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	52829	1			T15	2		T16	2		T17	1
valid_sources[0x01]	53505	1			T14	8		T15	1		T16	1
valid_sources[0x02]	53013	1			T14	5		T15	2		T17	4
valid_sources[0x03]	51848	1			T16	1		T17	3		T18	2
valid_sources[0x04]	53103	1			T14	8		T15	3		T17	3
valid_sources[0x05]	52661	1			T14	8		T15	2		T17	9
valid_sources[0x06]	53357	1			T15	1		T18	4		T55	17
valid_sources[0x07]	52752	1			T14	3		T15	1		T17	3
valid_sources[0x08]	52834	1			T14	2		T15	1		T17	2
valid_sources[0x09]	52949	1			T15	4		T16	2		T17	1
valid_sources[0x0a]	52651	1			T14	1		T15	1		T16	1
valid_sources[0x0b]	53321	1			T14	8		T15	1		T17	4
valid_sources[0x0c]	52662	1			T14	2		T15	4		T17	1
valid_sources[0x0d]	52942	1			T14	1		T15	2		T17	1
valid_sources[0x0e]	52426	1			T14	8		T55	18		T34	1
valid_sources[0x0f]	52737	1			T14	2		T15	1		T16	1
valid_sources[0x10]	53023	1			T14	4		T16	1		T17	3
valid_sources[0x11]	52388	1			T14	2		T15	1		T17	3
valid_sources[0x12]	52672	1			T14	2		T15	3		T55	31
valid_sources[0x13]	52348	1			T14	4		T15	4		T16	1
valid_sources[0x14]	52515	1			T14	8		T16	1		T18	11
valid_sources[0x15]	53079	1			T15	2		T16	1		T17	2
valid_sources[0x16]	51638	1			T15	3		T16	1		T17	4
valid_sources[0x17]	53521	1			T14	1		T15	2		T16	1
valid_sources[0x18]	51853	1			T14	2		T15	4		T18	14
valid_sources[0x19]	52742	1			T14	2		T16	1		T17	2
valid_sources[0x1a]	52489	1			T14	2		T17	1		T18	4
valid_sources[0x1b]	52623	1			T15	1		T18	3		T55	29
valid_sources[0x1c]	52048	1			T14	4		T15	1		T16	1
valid_sources[0x1d]	51821	1			T14	1		T15	3		T16	2
valid_sources[0x1e]	52225	1			T15	2		T16	1		T17	4
valid_sources[0x1f]	52094	1			T14	3		T15	2		T16	4
valid_sources[0x20]	52474	1			T14	2		T15	1		T17	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

48257

1

T14

1

T15

6

T16

1

values[0x0]

all_enables

biggest_size

362183

1

T14

20

T15

4

T17

15

values[0x1]

all_enables

biggest_size

48169

1

T14

3

T15

3

T16

3