Module Definition
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Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_alert_tx[0].u_prim_alert_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
33.33 33.33


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
33.33 33.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
70.77 92.32 50.23 96.08 34.45 80.77 u_pinmux_aon


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[0].u_alert_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
33.33 33.33


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
33.33 33.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
42.11 28.24 14.29 62.34 58.33 47.37 u_rv_core_ibex


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[1].u_alert_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
33.33 33.33


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
33.33 33.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
42.11 28.24 14.29 62.34 58.33 47.37 u_rv_core_ibex


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
33.33 33.33


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
33.33 33.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
42.11 28.24 14.29 62.34 58.33 47.37 u_rv_core_ibex


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[3].u_alert_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
33.33 33.33


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
33.33 33.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
42.11 28.24 14.29 62.34 58.33 47.37 u_rv_core_ibex


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
58.33 58.33


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
58.33 58.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
85.60 66.08 100.00 98.04 75.00 88.89 u_rv_plic


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : prim_alert_sender
TotalCoveredPercent
Totals 12 7 58.33
Total Bits 24 14 58.33
Total Bits 0->1 12 7 58.33
Total Bits 1->0 12 7 58.33

Ports 12 7 58.33
Port Bits 24 14 58.33
Port Bits 0->1 12 7 58.33
Port Bits 1->0 12 7 58.33

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_test_i Yes Yes T27,T28 Yes T27,T28 INPUT
alert_req_i No No No INPUT
alert_ack_o No No No OUTPUT
alert_state_o No No No OUTPUT
alert_rx_i.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i.ack_p Yes Yes T27,T28 Yes T27,T28 INPUT
alert_rx_i.ping_n No No No INPUT
alert_rx_i.ping_p No No No INPUT
alert_tx_o.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o.alert_p Yes Yes T27,T28 Yes T27,T28 OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_alert_tx[0].u_prim_alert_sender
TotalCoveredPercent
Totals 12 4 33.33
Total Bits 24 8 33.33
Total Bits 0->1 12 4 33.33
Total Bits 1->0 12 4 33.33

Ports 12 4 33.33
Port Bits 24 8 33.33
Port Bits 0->1 12 4 33.33
Port Bits 1->0 12 4 33.33

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_test_i No No No INPUT
alert_req_i No No No INPUT
alert_ack_o No No No OUTPUT
alert_state_o No No No OUTPUT
alert_rx_i.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i.ack_p No No No INPUT
alert_rx_i.ping_n No No No INPUT
alert_rx_i.ping_p No No No INPUT
alert_tx_o.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o.alert_p No No No OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[0].u_alert_sender
TotalCoveredPercent
Totals 12 4 33.33
Total Bits 24 8 33.33
Total Bits 0->1 12 4 33.33
Total Bits 1->0 12 4 33.33

Ports 12 4 33.33
Port Bits 24 8 33.33
Port Bits 0->1 12 4 33.33
Port Bits 1->0 12 4 33.33

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_test_i No No No INPUT
alert_req_i No No No INPUT
alert_ack_o No No No OUTPUT
alert_state_o No No No OUTPUT
alert_rx_i.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i.ack_p No No No INPUT
alert_rx_i.ping_n No No No INPUT
alert_rx_i.ping_p No No No INPUT
alert_tx_o.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o.alert_p No No No OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[1].u_alert_sender
TotalCoveredPercent
Totals 12 4 33.33
Total Bits 24 8 33.33
Total Bits 0->1 12 4 33.33
Total Bits 1->0 12 4 33.33

Ports 12 4 33.33
Port Bits 24 8 33.33
Port Bits 0->1 12 4 33.33
Port Bits 1->0 12 4 33.33

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_test_i No No No INPUT
alert_req_i No No No INPUT
alert_ack_o No No No OUTPUT
alert_state_o No No No OUTPUT
alert_rx_i.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i.ack_p No No No INPUT
alert_rx_i.ping_n No No No INPUT
alert_rx_i.ping_p No No No INPUT
alert_tx_o.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o.alert_p No No No OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender
TotalCoveredPercent
Totals 12 4 33.33
Total Bits 24 8 33.33
Total Bits 0->1 12 4 33.33
Total Bits 1->0 12 4 33.33

Ports 12 4 33.33
Port Bits 24 8 33.33
Port Bits 0->1 12 4 33.33
Port Bits 1->0 12 4 33.33

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_test_i No No No INPUT
alert_req_i No No No INPUT
alert_ack_o No No No OUTPUT
alert_state_o No No No OUTPUT
alert_rx_i.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i.ack_p No No No INPUT
alert_rx_i.ping_n No No No INPUT
alert_rx_i.ping_p No No No INPUT
alert_tx_o.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o.alert_p No No No OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[3].u_alert_sender
TotalCoveredPercent
Totals 12 4 33.33
Total Bits 24 8 33.33
Total Bits 0->1 12 4 33.33
Total Bits 1->0 12 4 33.33

Ports 12 4 33.33
Port Bits 24 8 33.33
Port Bits 0->1 12 4 33.33
Port Bits 1->0 12 4 33.33

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_test_i No No No INPUT
alert_req_i No No No INPUT
alert_ack_o No No No OUTPUT
alert_state_o No No No OUTPUT
alert_rx_i.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i.ack_p No No No INPUT
alert_rx_i.ping_n No No No INPUT
alert_rx_i.ping_p No No No INPUT
alert_tx_o.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o.alert_p No No No OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender
TotalCoveredPercent
Totals 12 7 58.33
Total Bits 24 14 58.33
Total Bits 0->1 12 7 58.33
Total Bits 1->0 12 7 58.33

Ports 12 7 58.33
Port Bits 24 14 58.33
Port Bits 0->1 12 7 58.33
Port Bits 1->0 12 7 58.33

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_test_i Yes Yes T27,T28 Yes T27,T28 INPUT
alert_req_i No No No INPUT
alert_ack_o No No No OUTPUT
alert_state_o No No No OUTPUT
alert_rx_i.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i.ack_p Yes Yes T27,T28 Yes T27,T28 INPUT
alert_rx_i.ping_n No No No INPUT
alert_rx_i.ping_p No No No INPUT
alert_tx_o.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o.alert_p Yes Yes T27,T28 Yes T27,T28 OUTPUT

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