Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : entropy_src
SCORELINECONDTOGGLEFSMBRANCHASSERT
32.83 32.83

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_entropy_src_0.1/rtl/entropy_src.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_entropy_src 34.78 34.78


Module Instance : tb.dut.top_earlgrey.u_entropy_src

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
34.78 34.78


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
34.78 34.78


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
84.80 70.25 84.16 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : entropy_src
TotalCoveredPercent
Totals 65 40 61.54
Total Bits 1322 434 32.83
Total Bits 0->1 661 217 32.83
Total Bits 1->0 661 217 32.83

Ports 65 40 61.54
Port Bits 1322 434 32.83
Port Bits 0->1 661 217 32.83
Port Bits 1->0 661 217 32.83

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T11,T12,T13 Yes T11,T12,T13 INPUT
rst_ni Yes Yes T11,T12,T13 Yes T11,T12,T13 INPUT
tl_i.d_ready Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_i.a_mask[3:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_i.a_address[7:0] Yes Yes T15,T16,T17 Yes T15,T16,T17 INPUT
tl_i.a_address[16:8] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[18:17] Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_i.a_address[19] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[20] Yes Yes *T14,*T15,*T16 Yes T14,T15,T16 INPUT
tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[24] Yes Yes *T14,*T15,*T16 Yes T14,T15,T16 INPUT
tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T14,*T15,*T16 Yes T14,T15,T16 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_i.a_valid Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_o.a_ready Yes Yes T14,T17,T18 Yes T14,T15,T16 OUTPUT
tl_o.d_error Yes Yes T14,T15,T16 Yes T14,T15,T16 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 OUTPUT
tl_o.d_data[31:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 OUTPUT
tl_o.d_sink Yes Yes T14,T15,T16 Yes T14,T15,T16 OUTPUT
tl_o.d_source[5:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T14,*T15,*T16 Yes T14,T15,T16 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T14,T15,T16 Yes T14,T15,T16 OUTPUT
otp_en_entropy_src_fw_read_i[7:0] Yes Yes T11,T12,T13 Yes T11,T12,T13 INPUT
otp_en_entropy_src_fw_over_i[7:0] Yes Yes T11,T12,T13 Yes T11,T12,T13 INPUT
rng_fips_o No No No OUTPUT
entropy_src_hw_if_i.es_req No No No INPUT
entropy_src_hw_if_o.es_fips No No No OUTPUT
entropy_src_hw_if_o.es_bits[383:0] No No No OUTPUT
entropy_src_hw_if_o.es_ack No No No OUTPUT
entropy_src_rng_o.rng_enable No No No OUTPUT
entropy_src_rng_i.rng_b[3:0] No No No INPUT
entropy_src_rng_i.rng_valid No No No INPUT
cs_aes_halt_o.cs_aes_halt_req No No No OUTPUT
cs_aes_halt_i.cs_aes_halt_ack No No No INPUT
entropy_src_xht_o.threshold_scope No No No OUTPUT
entropy_src_xht_o.window_wrap_pulse No No No OUTPUT
entropy_src_xht_o.health_test_window[15:0] Yes Yes T11,T13,T19 Yes T11,T13,T19 OUTPUT
entropy_src_xht_o.thresh_lo[15:0] Yes Yes T20,T22,T30 Yes T20,T22,T30 OUTPUT
entropy_src_xht_o.thresh_hi[15:0] Yes Yes T20,T22,T30 Yes T20,T22,T30 OUTPUT
entropy_src_xht_o.active No No No OUTPUT
entropy_src_xht_o.clear No No No OUTPUT
entropy_src_xht_o.entropy_bit_valid No No No OUTPUT
entropy_src_xht_o.entropy_bit[3:0] No No No OUTPUT
entropy_src_xht_i.test_fail_lo_pulse No No No INPUT
entropy_src_xht_i.test_fail_hi_pulse No No No INPUT
entropy_src_xht_i.continuous_test No No No INPUT
entropy_src_xht_i.test_cnt_lo[15:0] No No No INPUT
entropy_src_xht_i.test_cnt_hi[15:0] No No No INPUT
alert_rx_i[0].ack_n Yes Yes T11,T12,T13 Yes T11,T12,T13 INPUT
alert_rx_i[0].ack_p Yes Yes T11,T19,T31 Yes T11,T19,T31 INPUT
alert_rx_i[0].ping_n No No No INPUT
alert_rx_i[0].ping_p No No No INPUT
alert_rx_i[1].ack_n Yes Yes T11,T12,T13 Yes T11,T12,T13 INPUT
alert_rx_i[1].ack_p Yes Yes T11,T12,T13 Yes T11,T12,T13 INPUT
alert_rx_i[1].ping_n No No No INPUT
alert_rx_i[1].ping_p No No No INPUT
alert_tx_o[0].alert_n Yes Yes T11,T12,T13 Yes T11,T12,T13 OUTPUT
alert_tx_o[0].alert_p Yes Yes T11,T19,T31 Yes T11,T19,T31 OUTPUT
alert_tx_o[1].alert_n Yes Yes T11,T12,T13 Yes T11,T12,T13 OUTPUT
alert_tx_o[1].alert_p Yes Yes T11,T12,T13 Yes T11,T12,T13 OUTPUT
intr_es_entropy_valid_o Yes Yes T20,T23,T21 Yes T20,T23,T21 OUTPUT
intr_es_health_test_failed_o Yes Yes T22,T30 Yes T22,T30 OUTPUT
intr_es_observe_fifo_ready_o Yes Yes T20,T22 Yes T20,T22 OUTPUT
intr_es_fatal_err_o Yes Yes T22,T23 Yes T22,T23 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_entropy_src
TotalCoveredPercent
Totals 58 40 68.97
Total Bits 1248 434 34.78
Total Bits 0->1 624 217 34.78
Total Bits 1->0 624 217 34.78

Ports 58 40 68.97
Port Bits 1248 434 34.78
Port Bits 0->1 624 217 34.78
Port Bits 1->0 624 217 34.78

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
clk_i Yes Yes T11,T12,T13 Yes T11,T12,T13 INPUT
rst_ni Yes Yes T11,T12,T13 Yes T11,T12,T13 INPUT
tl_i.d_ready Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_i.a_mask[3:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_i.a_address[7:0] Yes Yes T15,T16,T17 Yes T15,T16,T17 INPUT
tl_i.a_address[16:8] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[18:17] Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_i.a_address[19] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[20] Yes Yes *T14,*T15,*T16 Yes T14,T15,T16 INPUT
tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[24] Yes Yes *T14,*T15,*T16 Yes T14,T15,T16 INPUT
tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T14,*T15,*T16 Yes T14,T15,T16 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_i.a_valid Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_o.a_ready Yes Yes T14,T17,T18 Yes T14,T15,T16 OUTPUT
tl_o.d_error Yes Yes T14,T15,T16 Yes T14,T15,T16 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 OUTPUT
tl_o.d_data[31:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 OUTPUT
tl_o.d_sink Yes Yes T14,T15,T16 Yes T14,T15,T16 OUTPUT
tl_o.d_source[5:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T14,*T15,*T16 Yes T14,T15,T16 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T14,T15,T16 Yes T14,T15,T16 OUTPUT
otp_en_entropy_src_fw_read_i[7:0] Yes Yes T11,T12,T13 Yes T11,T12,T13 INPUT
otp_en_entropy_src_fw_over_i[7:0] Yes Yes T11,T12,T13 Yes T11,T12,T13 INPUT
rng_fips_o No No No OUTPUT
entropy_src_hw_if_i.es_req No No No INPUT
entropy_src_hw_if_o.es_fips No No No OUTPUT
entropy_src_hw_if_o.es_bits[383:0] No No No OUTPUT
entropy_src_hw_if_o.es_ack No No No OUTPUT
entropy_src_rng_o.rng_enable No No No OUTPUT
entropy_src_rng_i.rng_b[3:0] No No No INPUT
entropy_src_rng_i.rng_valid No No No INPUT
cs_aes_halt_o.cs_aes_halt_req No No No OUTPUT
cs_aes_halt_i.cs_aes_halt_ack No No No INPUT
entropy_src_xht_o.threshold_scope[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off / unconnected port.
entropy_src_xht_o.window_wrap_pulse No No No OUTPUT
entropy_src_xht_o.health_test_window[15:0] Yes Yes T11,T13,T19 Yes T11,T13,T19 OUTPUT
entropy_src_xht_o.thresh_lo[15:0] Yes Yes T20,T22,T30 Yes T20,T22,T30 OUTPUT
entropy_src_xht_o.thresh_hi[15:0] Yes Yes T20,T22,T30 Yes T20,T22,T30 OUTPUT
entropy_src_xht_o.active[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off / unconnected port.
entropy_src_xht_o.clear No No No OUTPUT
entropy_src_xht_o.entropy_bit_valid No No No OUTPUT
entropy_src_xht_o.entropy_bit[3:0] No No No OUTPUT
entropy_src_xht_i.test_fail_lo_pulse[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off / unconnected port.
entropy_src_xht_i.test_fail_hi_pulse[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off / unconnected port.
entropy_src_xht_i.continuous_test[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off / unconnected port.
entropy_src_xht_i.test_cnt_lo[15:0] Excluded Excluded Excluded INPUT [UNR] Tied off / unconnected port.
entropy_src_xht_i.test_cnt_hi[15:0] Excluded Excluded Excluded INPUT [UNR] Tied off / unconnected port.
alert_rx_i[0].ack_n Yes Yes T11,T12,T13 Yes T11,T12,T13 INPUT
alert_rx_i[0].ack_p Yes Yes T11,T19,T31 Yes T11,T19,T31 INPUT
alert_rx_i[0].ping_n No No No INPUT
alert_rx_i[0].ping_p No No No INPUT
alert_rx_i[1].ack_n Yes Yes T11,T12,T13 Yes T11,T12,T13 INPUT
alert_rx_i[1].ack_p Yes Yes T11,T12,T13 Yes T11,T12,T13 INPUT
alert_rx_i[1].ping_n No No No INPUT
alert_rx_i[1].ping_p No No No INPUT
alert_tx_o[0].alert_n Yes Yes T11,T12,T13 Yes T11,T12,T13 OUTPUT
alert_tx_o[0].alert_p Yes Yes T11,T19,T31 Yes T11,T19,T31 OUTPUT
alert_tx_o[1].alert_n Yes Yes T11,T12,T13 Yes T11,T12,T13 OUTPUT
alert_tx_o[1].alert_p Yes Yes T11,T12,T13 Yes T11,T12,T13 OUTPUT
intr_es_entropy_valid_o Yes Yes T20,T23,T21 Yes T20,T23,T21 OUTPUT
intr_es_health_test_failed_o Yes Yes T22,T30 Yes T22,T30 OUTPUT
intr_es_observe_fifo_ready_o Yes Yes T20,T22 Yes T20,T22 OUTPUT
intr_es_fatal_err_o Yes Yes T22,T23 Yes T22,T23 OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%