Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : edn
SCORELINECONDTOGGLEFSMBRANCHASSERT
26.20 26.20

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_edn0 26.08 26.08
tb.dut.top_earlgrey.u_edn1 41.97 41.97


Module Instance : tb.dut.top_earlgrey.u_edn0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
26.08 26.08


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
26.08 26.08


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
84.80 70.25 84.16 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_edn1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
41.97 41.97


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
41.97 41.97


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
84.80 70.25 84.16 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : edn
TotalCoveredPercent
Totals 78 39 50.00
Total Bits 1206 316 26.20
Total Bits 0->1 603 158 26.20
Total Bits 1->0 603 158 26.20

Ports 78 39 50.00
Port Bits 1206 316 26.20
Port Bits 0->1 603 158 26.20
Port Bits 1->0 603 158 26.20

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T11,T12,T13 Yes T11,T12,T13 INPUT
rst_ni Yes Yes T11,T12,T13 Yes T11,T12,T13 INPUT
tl_i.d_ready Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_i.a_mask[3:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_i.a_address[6:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_i.a_address[15:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[20:16] Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[24] Yes Yes *T14,*T15,*T16 Yes T14,T15,T16 INPUT
tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T14,*T15,*T16 Yes T14,T15,T16 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_i.a_valid Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_o.a_ready Yes Yes T14,T17,T18 Yes T14,T15,T16 OUTPUT
tl_o.d_error Yes Yes T14,T15,T16 Yes T14,T15,T16 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 OUTPUT
tl_o.d_data[31:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 OUTPUT
tl_o.d_sink Yes Yes T14,T15,T16 Yes T14,T15,T16 OUTPUT
tl_o.d_source[5:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T14,*T15,*T16 Yes T14,T15,T16 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T14,T15,T16 Yes T14,T15,T16 OUTPUT
edn_i[0].edn_req No No No INPUT
edn_i[1].edn_req Yes Yes T20,T22,T30 Yes T20,T22,T30 INPUT
edn_i[2].edn_req Yes Yes T11,T12,T13 Yes T11,T12,T13 INPUT
edn_i[3].edn_req No No No INPUT
edn_i[4].edn_req Yes Yes T11,T12,T13 Yes T11,T12,T13 INPUT
edn_i[5].edn_req Yes Yes T11,T12,T13 Yes T11,T12,T13 INPUT
edn_i[6].edn_req Yes Yes T11,T12,T13 Yes T11,T12,T13 INPUT
edn_i[7].edn_req Yes Yes T11,T12,T13 Yes T11,T12,T13 INPUT
edn_o[0].edn_bus[31:0] No No No OUTPUT
edn_o[0].edn_fips No No No OUTPUT
edn_o[0].edn_ack No No No OUTPUT
edn_o[1].edn_bus[31:0] No No No OUTPUT
edn_o[1].edn_fips No No No OUTPUT
edn_o[1].edn_ack No No No OUTPUT
edn_o[2].edn_bus[31:0] No No No OUTPUT
edn_o[2].edn_fips No No No OUTPUT
edn_o[2].edn_ack No No No OUTPUT
edn_o[3].edn_bus[31:0] No No No OUTPUT
edn_o[3].edn_fips No No No OUTPUT
edn_o[3].edn_ack No No No OUTPUT
edn_o[4].edn_bus[31:0] No No No OUTPUT
edn_o[4].edn_fips No No No OUTPUT
edn_o[4].edn_ack No No No OUTPUT
edn_o[5].edn_bus[31:0] No No No OUTPUT
edn_o[5].edn_fips No No No OUTPUT
edn_o[5].edn_ack No No No OUTPUT
edn_o[6].edn_bus[31:0] No No No OUTPUT
edn_o[6].edn_fips No No No OUTPUT
edn_o[6].edn_ack No No No OUTPUT
edn_o[7].edn_bus[31:0] No No No OUTPUT
edn_o[7].edn_fips No No No OUTPUT
edn_o[7].edn_ack No No No OUTPUT
csrng_cmd_o.genbits_ready No No No OUTPUT
csrng_cmd_o.csrng_req_bus[31:0] No No No OUTPUT
csrng_cmd_o.csrng_req_valid No No No OUTPUT
csrng_cmd_i.genbits_bus[127:0] No No No INPUT
csrng_cmd_i.genbits_fips No No No INPUT
csrng_cmd_i.genbits_valid No No No INPUT
csrng_cmd_i.csrng_rsp_sts No No No INPUT
csrng_cmd_i.csrng_rsp_ack No No No INPUT
csrng_cmd_i.csrng_req_ready No No No INPUT
alert_rx_i[0].ack_n Yes Yes T11,T12,T13 Yes T11,T12,T13 INPUT
alert_rx_i[0].ack_p Yes Yes T12,T13,T19 Yes T12,T13,T19 INPUT
alert_rx_i[0].ping_n No No No INPUT
alert_rx_i[0].ping_p No No No INPUT
alert_rx_i[1].ack_n Yes Yes T11,T12,T13 Yes T11,T12,T13 INPUT
alert_rx_i[1].ack_p Yes Yes T11,T13,T19 Yes T11,T13,T19 INPUT
alert_rx_i[1].ping_n No No No INPUT
alert_rx_i[1].ping_p No No No INPUT
alert_tx_o[0].alert_n Yes Yes T11,T12,T13 Yes T11,T12,T13 OUTPUT
alert_tx_o[0].alert_p Yes Yes T12,T13,T19 Yes T12,T13,T19 OUTPUT
alert_tx_o[1].alert_n Yes Yes T11,T12,T13 Yes T11,T12,T13 OUTPUT
alert_tx_o[1].alert_p Yes Yes T11,T13,T19 Yes T11,T13,T19 OUTPUT
intr_edn_cmd_req_done_o Yes Yes T30,T23 Yes T30,T23 OUTPUT
intr_edn_fatal_err_o Yes Yes T20,T22,T21 Yes T20,T22,T21 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_edn0
TotalCoveredPercent
Totals 78 39 50.00
Total Bits 1204 314 26.08
Total Bits 0->1 602 157 26.08
Total Bits 1->0 602 157 26.08

Ports 78 39 50.00
Port Bits 1204 314 26.08
Port Bits 0->1 602 157 26.08
Port Bits 1->0 602 157 26.08

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T11,T12,T13 Yes T11,T12,T13 INPUT
rst_ni Yes Yes T11,T12,T13 Yes T11,T12,T13 INPUT
tl_i.d_ready Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_i.a_mask[3:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_i.a_address[6:0] Yes Yes T15,T16,T17 Yes T15,T16,T17 INPUT
tl_i.a_address[15:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[18:16] Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_i.a_address[19] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[20] Yes Yes *T14,*T15,*T16 Yes T14,T15,T16 INPUT
tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[24] Yes Yes *T14,*T15,*T16 Yes T14,T15,T16 INPUT
tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T14,*T15,*T16 Yes T14,T15,T16 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_i.a_valid Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_o.a_ready Yes Yes T14,T17,T18 Yes T14,T15,T16 OUTPUT
tl_o.d_error Yes Yes T14,T15,T16 Yes T14,T15,T16 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 OUTPUT
tl_o.d_data[31:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 OUTPUT
tl_o.d_sink Yes Yes T14,T15,T16 Yes T14,T15,T16 OUTPUT
tl_o.d_source[5:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T14,*T15,*T16 Yes T14,T15,T16 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T14,T15,T16 Yes T14,T15,T16 OUTPUT
edn_i[0].edn_req No No No INPUT
edn_i[1].edn_req Yes Yes T20,T22,T30 Yes T20,T22,T30 INPUT
edn_i[2].edn_req Yes Yes T11,T12,T13 Yes T11,T12,T13 INPUT
edn_i[3].edn_req No No No INPUT
edn_i[4].edn_req Yes Yes T11,T12,T13 Yes T11,T12,T13 INPUT
edn_i[5].edn_req Yes Yes T11,T12,T13 Yes T11,T12,T13 INPUT
edn_i[6].edn_req Yes Yes T11,T12,T13 Yes T11,T12,T13 INPUT
edn_i[7].edn_req Yes Yes T11,T12,T13 Yes T11,T12,T13 INPUT
edn_o[0].edn_bus[31:0] No No No OUTPUT
edn_o[0].edn_fips No No No OUTPUT
edn_o[0].edn_ack No No No OUTPUT
edn_o[1].edn_bus[31:0] No No No OUTPUT
edn_o[1].edn_fips No No No OUTPUT
edn_o[1].edn_ack No No No OUTPUT
edn_o[2].edn_bus[31:0] No No No OUTPUT
edn_o[2].edn_fips No No No OUTPUT
edn_o[2].edn_ack No No No OUTPUT
edn_o[3].edn_bus[31:0] No No No OUTPUT
edn_o[3].edn_fips No No No OUTPUT
edn_o[3].edn_ack No No No OUTPUT
edn_o[4].edn_bus[31:0] No No No OUTPUT
edn_o[4].edn_fips No No No OUTPUT
edn_o[4].edn_ack No No No OUTPUT
edn_o[5].edn_bus[31:0] No No No OUTPUT
edn_o[5].edn_fips No No No OUTPUT
edn_o[5].edn_ack No No No OUTPUT
edn_o[6].edn_bus[31:0] No No No OUTPUT
edn_o[6].edn_fips No No No OUTPUT
edn_o[6].edn_ack No No No OUTPUT
edn_o[7].edn_bus[31:0] No No No OUTPUT
edn_o[7].edn_fips No No No OUTPUT
edn_o[7].edn_ack No No No OUTPUT
csrng_cmd_o.genbits_ready No No No OUTPUT
csrng_cmd_o.csrng_req_bus[31:0] No No No OUTPUT
csrng_cmd_o.csrng_req_valid No No No OUTPUT
csrng_cmd_i.genbits_bus[127:0] No No No INPUT
csrng_cmd_i.genbits_fips No No No INPUT
csrng_cmd_i.genbits_valid No No No INPUT
csrng_cmd_i.csrng_rsp_sts No No No INPUT
csrng_cmd_i.csrng_rsp_ack No No No INPUT
csrng_cmd_i.csrng_req_ready No No No INPUT
alert_rx_i[0].ack_n Yes Yes T11,T12,T13 Yes T11,T12,T13 INPUT
alert_rx_i[0].ack_p Yes Yes T12,T19,T31 Yes T12,T19,T31 INPUT
alert_rx_i[0].ping_n No No No INPUT
alert_rx_i[0].ping_p No No No INPUT
alert_rx_i[1].ack_n Yes Yes T11,T12,T13 Yes T11,T12,T13 INPUT
alert_rx_i[1].ack_p Yes Yes T11,T19,T31 Yes T11,T19,T31 INPUT
alert_rx_i[1].ping_n No No No INPUT
alert_rx_i[1].ping_p No No No INPUT
alert_tx_o[0].alert_n Yes Yes T11,T12,T13 Yes T11,T12,T13 OUTPUT
alert_tx_o[0].alert_p Yes Yes T12,T19,T31 Yes T12,T19,T31 OUTPUT
alert_tx_o[1].alert_n Yes Yes T11,T12,T13 Yes T11,T12,T13 OUTPUT
alert_tx_o[1].alert_p Yes Yes T11,T19,T31 Yes T11,T19,T31 OUTPUT
intr_edn_cmd_req_done_o Yes Yes T23 Yes T23 OUTPUT
intr_edn_fatal_err_o Yes Yes T21 Yes T21 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_edn1
TotalCoveredPercent
Totals 50 33 66.00
Total Bits 710 298 41.97
Total Bits 0->1 355 149 41.97
Total Bits 1->0 355 149 41.97

Ports 50 33 66.00
Port Bits 710 298 41.97
Port Bits 0->1 355 149 41.97
Port Bits 1->0 355 149 41.97

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
clk_i Yes Yes T11,T12,T13 Yes T11,T12,T13 INPUT
rst_ni Yes Yes T11,T12,T13 Yes T11,T12,T13 INPUT
tl_i.d_ready Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_i.a_mask[3:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_i.a_address[6:0] Yes Yes *T14,T15,T16 Yes T14,T15,T16 INPUT
tl_i.a_address[18:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[20:19] Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[24] Yes Yes *T14,*T15,*T16 Yes T14,T15,T16 INPUT
tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T14,*T15,*T16 Yes T14,T15,T16 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_i.a_valid Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_o.a_ready Yes Yes T14,T17,T18 Yes T14,T15,T16 OUTPUT
tl_o.d_error Yes Yes T14,T15,T16 Yes T14,T15,T16 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 OUTPUT
tl_o.d_data[31:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 OUTPUT
tl_o.d_sink Yes Yes T14,T15,T16 Yes T14,T15,T16 OUTPUT
tl_o.d_source[5:0] Yes Yes T15,T16,T18 Yes T14,T15,T16 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T15,*T16,*T17 Yes T14,T15,T16 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T14,T15,T16 Yes T14,T15,T16 OUTPUT
edn_i[0].edn_req No No No INPUT
edn_i[1].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[2].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[3].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[4].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[5].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[6].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[7].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_o[0].edn_bus[31:0] No No No OUTPUT
edn_o[0].edn_fips No No No OUTPUT
edn_o[0].edn_ack No No No OUTPUT
edn_o[1].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[1].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[1].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[2].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[2].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[2].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[3].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[3].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[3].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[4].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[4].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[4].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[5].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[5].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[5].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[6].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[6].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[6].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[7].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[7].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[7].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
csrng_cmd_o.genbits_ready No No No OUTPUT
csrng_cmd_o.csrng_req_bus[31:0] No No No OUTPUT
csrng_cmd_o.csrng_req_valid No No No OUTPUT
csrng_cmd_i.genbits_bus[127:0] No No No INPUT
csrng_cmd_i.genbits_fips No No No INPUT
csrng_cmd_i.genbits_valid No No No INPUT
csrng_cmd_i.csrng_rsp_sts No No No INPUT
csrng_cmd_i.csrng_rsp_ack No No No INPUT
csrng_cmd_i.csrng_req_ready No No No INPUT
alert_rx_i[0].ack_n Yes Yes T11,T12,T13 Yes T11,T12,T13 INPUT
alert_rx_i[0].ack_p Yes Yes T12,T13,T19 Yes T12,T13,T19 INPUT
alert_rx_i[0].ping_n No No No INPUT
alert_rx_i[0].ping_p No No No INPUT
alert_rx_i[1].ack_n Yes Yes T11,T12,T13 Yes T11,T12,T13 INPUT
alert_rx_i[1].ack_p Yes Yes T13,T19,T32 Yes T13,T19,T32 INPUT
alert_rx_i[1].ping_n No No No INPUT
alert_rx_i[1].ping_p No No No INPUT
alert_tx_o[0].alert_n Yes Yes T11,T12,T13 Yes T11,T12,T13 OUTPUT
alert_tx_o[0].alert_p Yes Yes T12,T13,T19 Yes T12,T13,T19 OUTPUT
alert_tx_o[1].alert_n Yes Yes T11,T12,T13 Yes T11,T12,T13 OUTPUT
alert_tx_o[1].alert_p Yes Yes T13,T19,T32 Yes T13,T19,T32 OUTPUT
intr_edn_cmd_req_done_o Yes Yes T30 Yes T30 OUTPUT
intr_edn_fatal_err_o Yes Yes T20,T22,T21 Yes T20,T22,T21 OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%