Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_pwm_aon.u_reg.u_cfg_cdc

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.88	90.91	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.38	94.00	87.50			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.05	99.16	97.20			99.83	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	93.79	93.33	81.82			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.88	90.91	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.38	94.00	87.50			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.05	99.16	97.20			99.83	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	93.79	93.33	81.82			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.88	90.91	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.38	94.00	87.50			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.05	99.16	97.20			99.83	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	93.79	93.33	81.82			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.88	90.91	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.38	94.00	87.50			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.05	99.16	97.20			99.83	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	93.79	93.33	81.82			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.88	90.91	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.38	94.00	87.50			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.05	99.16	97.20			99.83	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	93.79	93.33	81.82			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.88	90.91	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.38	94.00	87.50			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.05	99.16	97.20			99.83	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	93.79	93.33	81.82			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.88	90.91	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.38	94.00	87.50			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.05	99.16	97.20			99.83	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	93.79	93.33	81.82			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.88	90.91	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.38	94.00	87.50			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.05	99.16	97.20			99.83	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	93.79	93.33	81.82			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.05	99.16	97.20			99.83	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.05	99.16	97.20			99.83	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.05	99.16	97.20			99.83	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.05	99.16	97.20			99.83	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.05	99.16	97.20			99.83	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.05	99.16	97.20			99.83	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.05	99.16	97.20			99.83	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.05	99.16	97.20			99.83	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	20	90.91
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	0	1
145	0	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc

	Total	Covered	Percent
Conditions	13	11	84.62
Logical	13	11	84.62
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Unreachable
1	0	Covered	T11,T12,T13

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T11,T12,T13
1	-	Not Covered

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T13
0	1	Unreachable
1	0	Covered	T11,T12,T13

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T11,T12,T13
0	0	1	Covered	T11,T12,T13
0	0	0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T11,T12,T13
0	0	1	Covered	T11,T12,T13
0	0	0	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	22678979	92445	0	0
DstReqKnown_A	241561	206720	0	0
SrcAckBusyChk_A	22678979	229	0	0
SrcBusyKnown_A	22678979	22539838	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22678979	92445	0	0
T11	49951	436	0	0
T12	42379	335	0	0
T13	50369	481	0	0
T19	309259	2023	0	0
T31	330497	1928	0	0
T32	87324	688	0	0
T35	156496	818	0	0
T38	323644	302	0	0
T41	88782	0	0	0
T46	0	4235	0	0
T57	76125	726	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241561	206720	0	0
T11	715	490	0	0
T12	690	466	0	0
T13	677	451	0	0
T19	2822	2599	0	0
T20	603	377	0	0
T31	3024	2803	0	0
T32	949	724	0	0
T39	561	336	0	0
T47	438	214	0	0
T62	534	310	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22678979	229	0	0
T11	49951	1	0	0
T12	42379	1	0	0
T13	50369	1	0	0
T19	309259	5	0	0
T31	330497	5	0	0
T32	87324	2	0	0
T35	156496	2	0	0
T38	323644	1	0	0
T41	88782	0	0	0
T46	0	11	0	0
T57	76125	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22678979	22539838	0	0
T11	49951	49293	0	0
T12	42379	41781	0	0
T13	50369	49318	0	0
T19	309259	308113	0	0
T20	30481	29901	0	0
T31	330497	329673	0	0
T32	87324	85975	0	0
T39	35864	34991	0	0
T47	21476	20644	0	0
T62	30774	29981	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	20	90.91
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	0	1
145	0	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc

	Total	Covered	Percent
Conditions	13	11	84.62
Logical	13	11	84.62
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Unreachable
1	0	Covered	T11,T12,T13

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T11,T12,T13
1	-	Not Covered

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T13
0	1	Unreachable
1	0	Covered	T11,T12,T13

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T11,T12,T13
0	0	1	Covered	T11,T12,T13
0	0	0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T11,T12,T13
0	0	1	Covered	T11,T12,T13
0	0	0	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	22678979	82574	0	0
DstReqKnown_A	241561	206720	0	0
SrcAckBusyChk_A	22678979	205	0	0
SrcBusyKnown_A	22678979	22539838	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22678979	82574	0	0
T11	49951	390	0	0
T12	42379	344	0	0
T13	50369	475	0	0
T19	309259	3023	0	0
T31	330497	331	0	0
T32	87324	767	0	0
T35	156496	845	0	0
T38	323644	1531	0	0
T41	88782	0	0	0
T46	0	4760	0	0
T57	76125	688	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241561	206720	0	0
T11	715	490	0	0
T12	690	466	0	0
T13	677	451	0	0
T19	2822	2599	0	0
T20	603	377	0	0
T31	3024	2803	0	0
T32	949	724	0	0
T39	561	336	0	0
T47	438	214	0	0
T62	534	310	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22678979	205	0	0
T11	49951	1	0	0
T12	42379	1	0	0
T13	50369	1	0	0
T19	309259	7	0	0
T31	330497	1	0	0
T32	87324	2	0	0
T35	156496	2	0	0
T38	323644	4	0	0
T41	88782	0	0	0
T46	0	12	0	0
T57	76125	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22678979	22539838	0	0
T11	49951	49293	0	0
T12	42379	41781	0	0
T13	50369	49318	0	0
T19	309259	308113	0	0
T20	30481	29901	0	0
T31	330497	329673	0	0
T32	87324	85975	0	0
T39	35864	34991	0	0
T47	21476	20644	0	0
T62	30774	29981	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	20	90.91
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	0	1
145	0	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc

	Total	Covered	Percent
Conditions	13	11	84.62
Logical	13	11	84.62
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Unreachable
1	0	Covered	T11,T12,T13

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T11,T12,T13
1	-	Not Covered

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T13
0	1	Unreachable
1	0	Covered	T11,T12,T13

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T11,T12,T13
0	0	1	Covered	T11,T12,T13
0	0	0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T11,T12,T13
0	0	1	Covered	T11,T12,T13
0	0	0	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	22678979	85381	0	0
DstReqKnown_A	241561	206720	0	0
SrcAckBusyChk_A	22678979	211	0	0
SrcBusyKnown_A	22678979	22539838	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22678979	85381	0	0
T11	49951	393	0	0
T12	42379	314	0	0
T13	50369	438	0	0
T19	309259	2059	0	0
T31	330497	2796	0	0
T32	87324	727	0	0
T35	156496	939	0	0
T38	323644	2817	0	0
T41	88782	0	0	0
T46	0	5617	0	0
T57	76125	749	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241561	206720	0	0
T11	715	490	0	0
T12	690	466	0	0
T13	677	451	0	0
T19	2822	2599	0	0
T20	603	377	0	0
T31	3024	2803	0	0
T32	949	724	0	0
T39	561	336	0	0
T47	438	214	0	0
T62	534	310	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22678979	211	0	0
T11	49951	1	0	0
T12	42379	1	0	0
T13	50369	1	0	0
T19	309259	5	0	0
T31	330497	7	0	0
T32	87324	2	0	0
T35	156496	2	0	0
T38	323644	7	0	0
T41	88782	0	0	0
T46	0	14	0	0
T57	76125	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22678979	22539838	0	0
T11	49951	49293	0	0
T12	42379	41781	0	0
T13	50369	49318	0	0
T19	309259	308113	0	0
T20	30481	29901	0	0
T31	330497	329673	0	0
T32	87324	85975	0	0
T39	35864	34991	0	0
T47	21476	20644	0	0
T62	30774	29981	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	20	90.91
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	0	1
145	0	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc

	Total	Covered	Percent
Conditions	13	11	84.62
Logical	13	11	84.62
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Unreachable
1	0	Covered	T11,T12,T13

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T11,T12,T13
1	-	Not Covered

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T13
0	1	Unreachable
1	0	Covered	T11,T12,T13

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T11,T12,T13
0	0	1	Covered	T11,T12,T13
0	0	0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T11,T12,T13
0	0	1	Covered	T11,T12,T13
0	0	0	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	22678979	78800	0	0
DstReqKnown_A	241561	206720	0	0
SrcAckBusyChk_A	22678979	197	0	0
SrcBusyKnown_A	22678979	22539838	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22678979	78800	0	0
T11	49951	384	0	0
T12	42379	244	0	0
T13	50369	366	0	0
T19	309259	1117	0	0
T31	330497	2776	0	0
T32	87324	721	0	0
T35	156496	921	0	0
T38	323644	2250	0	0
T41	88782	0	0	0
T46	0	5695	0	0
T57	76125	751	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241561	206720	0	0
T11	715	490	0	0
T12	690	466	0	0
T13	677	451	0	0
T19	2822	2599	0	0
T20	603	377	0	0
T31	3024	2803	0	0
T32	949	724	0	0
T39	561	336	0	0
T47	438	214	0	0
T62	534	310	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22678979	197	0	0
T11	49951	1	0	0
T12	42379	1	0	0
T13	50369	1	0	0
T19	309259	3	0	0
T31	330497	7	0	0
T32	87324	2	0	0
T35	156496	2	0	0
T38	323644	6	0	0
T41	88782	0	0	0
T46	0	14	0	0
T57	76125	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22678979	22539838	0	0
T11	49951	49293	0	0
T12	42379	41781	0	0
T13	50369	49318	0	0
T19	309259	308113	0	0
T20	30481	29901	0	0
T31	330497	329673	0	0
T32	87324	85975	0	0
T39	35864	34991	0	0
T47	21476	20644	0	0
T62	30774	29981	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	20	90.91
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	0	1
145	0	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc

	Total	Covered	Percent
Conditions	13	11	84.62
Logical	13	11	84.62
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Unreachable
1	0	Covered	T11,T12,T13

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T11,T12,T13
1	-	Not Covered

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T13
0	1	Unreachable
1	0	Covered	T11,T12,T13

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T11,T12,T13
0	0	1	Covered	T11,T12,T13
0	0	0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T11,T12,T13
0	0	1	Covered	T11,T12,T13
0	0	0	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	22678979	97740	0	0
DstReqKnown_A	241561	206720	0	0
SrcAckBusyChk_A	22678979	240	0	0
SrcBusyKnown_A	22678979	22539838	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22678979	97740	0	0
T11	49951	421	0	0
T12	42379	346	0	0
T13	50369	430	0	0
T19	309259	2066	0	0
T31	330497	1509	0	0
T32	87324	651	0	0
T35	156496	875	0	0
T38	323644	3609	0	0
T41	88782	0	0	0
T46	0	10206	0	0
T57	76125	765	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241561	206720	0	0
T11	715	490	0	0
T12	690	466	0	0
T13	677	451	0	0
T19	2822	2599	0	0
T20	603	377	0	0
T31	3024	2803	0	0
T32	949	724	0	0
T39	561	336	0	0
T47	438	214	0	0
T62	534	310	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22678979	240	0	0
T11	49951	1	0	0
T12	42379	1	0	0
T13	50369	1	0	0
T19	309259	5	0	0
T31	330497	4	0	0
T32	87324	2	0	0
T35	156496	2	0	0
T38	323644	9	0	0
T41	88782	0	0	0
T46	0	24	0	0
T57	76125	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22678979	22539838	0	0
T11	49951	49293	0	0
T12	42379	41781	0	0
T13	50369	49318	0	0
T19	309259	308113	0	0
T20	30481	29901	0	0
T31	330497	329673	0	0
T32	87324	85975	0	0
T39	35864	34991	0	0
T47	21476	20644	0	0
T62	30774	29981	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	20	90.91
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	0	1
145	0	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc

	Total	Covered	Percent
Conditions	13	11	84.62
Logical	13	11	84.62
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Unreachable
1	0	Covered	T11,T12,T13

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T11,T12,T13
1	-	Not Covered

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T13
0	1	Unreachable
1	0	Covered	T11,T12,T13

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T11,T12,T13
0	0	1	Covered	T11,T12,T13
0	0	0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T11,T12,T13
0	0	1	Covered	T11,T12,T13
0	0	0	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	22678979	75036	0	0
DstReqKnown_A	241561	206720	0	0
SrcAckBusyChk_A	22678979	188	0	0
SrcBusyKnown_A	22678979	22539838	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22678979	75036	0	0
T11	49951	389	0	0
T12	42379	243	0	0
T13	50369	413	0	0
T19	309259	1644	0	0
T31	330497	2005	0	0
T32	87324	774	0	0
T35	156496	812	0	0
T38	323644	1458	0	0
T41	88782	0	0	0
T46	0	2401	0	0
T57	76125	826	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241561	206720	0	0
T11	715	490	0	0
T12	690	466	0	0
T13	677	451	0	0
T19	2822	2599	0	0
T20	603	377	0	0
T31	3024	2803	0	0
T32	949	724	0	0
T39	561	336	0	0
T47	438	214	0	0
T62	534	310	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22678979	188	0	0
T11	49951	1	0	0
T12	42379	1	0	0
T13	50369	1	0	0
T19	309259	4	0	0
T31	330497	5	0	0
T32	87324	2	0	0
T35	156496	2	0	0
T38	323644	4	0	0
T41	88782	0	0	0
T46	0	7	0	0
T57	76125	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22678979	22539838	0	0
T11	49951	49293	0	0
T12	42379	41781	0	0
T13	50369	49318	0	0
T19	309259	308113	0	0
T20	30481	29901	0	0
T31	330497	329673	0	0
T32	87324	85975	0	0
T39	35864	34991	0	0
T47	21476	20644	0	0
T62	30774	29981	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	20	90.91
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	0	1
145	0	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc

	Total	Covered	Percent
Conditions	13	11	84.62
Logical	13	11	84.62
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Unreachable
1	0	Covered	T11,T61,T12

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T11,T12,T13
1	-	Not Covered

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T13
0	1	Unreachable
1	0	Covered	T11,T12,T13

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T11,T12,T13
0	0	1	Covered	T11,T12,T13
0	0	0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T11,T12,T13
0	0	1	Covered	T11,T12,T13
0	0	0	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	22678979	76042	0	0
DstReqKnown_A	241561	206720	0	0
SrcAckBusyChk_A	22678979	192	0	0
SrcBusyKnown_A	22678979	22539838	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22678979	76042	0	0
T11	49951	385	0	0
T12	42379	250	0	0
T13	50369	404	0	0
T19	309259	2042	0	0
T32	87324	719	0	0
T35	156496	891	0	0
T38	323644	3107	0	0
T41	88782	0	0	0
T46	628007	1856	0	0
T48	0	5108	0	0
T57	76125	740	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241561	206720	0	0
T11	715	490	0	0
T12	690	466	0	0
T13	677	451	0	0
T19	2822	2599	0	0
T20	603	377	0	0
T31	3024	2803	0	0
T32	949	724	0	0
T39	561	336	0	0
T47	438	214	0	0
T62	534	310	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22678979	192	0	0
T11	49951	1	0	0
T12	42379	1	0	0
T13	50369	1	0	0
T19	309259	5	0	0
T32	87324	2	0	0
T35	156496	2	0	0
T38	323644	8	0	0
T41	88782	0	0	0
T46	628007	5	0	0
T48	0	13	0	0
T57	76125	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22678979	22539838	0	0
T11	49951	49293	0	0
T12	42379	41781	0	0
T13	50369	49318	0	0
T19	309259	308113	0	0
T20	30481	29901	0	0
T31	330497	329673	0	0
T32	87324	85975	0	0
T39	35864	34991	0	0
T47	21476	20644	0	0
T62	30774	29981	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	20	90.91
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	0	1
145	0	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc

	Total	Covered	Percent
Conditions	13	11	84.62
Logical	13	11	84.62
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Unreachable
1	0	Covered	T11,T12,T13

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T11,T12,T13
1	-	Not Covered

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T13
0	1	Unreachable
1	0	Covered	T11,T12,T13

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T11,T12,T13
0	0	1	Covered	T11,T12,T13
0	0	0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T11,T12,T13
0	0	1	Covered	T11,T12,T13
0	0	0	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	22678979	77222	0	0
DstReqKnown_A	241561	206720	0	0
SrcAckBusyChk_A	22678979	193	0	0
SrcBusyKnown_A	22678979	22539838	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22678979	77222	0	0
T11	49951	376	0	0
T12	42379	294	0	0
T13	50369	416	0	0
T19	309259	2575	0	0
T31	330497	1859	0	0
T32	87324	650	0	0
T35	156496	850	0	0
T38	323644	1156	0	0
T41	88782	0	0	0
T46	0	4207	0	0
T57	76125	665	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241561	206720	0	0
T11	715	490	0	0
T12	690	466	0	0
T13	677	451	0	0
T19	2822	2599	0	0
T20	603	377	0	0
T31	3024	2803	0	0
T32	949	724	0	0
T39	561	336	0	0
T47	438	214	0	0
T62	534	310	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22678979	193	0	0
T11	49951	1	0	0
T12	42379	1	0	0
T13	50369	1	0	0
T19	309259	6	0	0
T31	330497	4	0	0
T32	87324	2	0	0
T35	156496	2	0	0
T38	323644	3	0	0
T41	88782	0	0	0
T46	0	11	0	0
T57	76125	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22678979	22539838	0	0
T11	49951	49293	0	0
T12	42379	41781	0	0
T13	50369	49318	0	0
T19	309259	308113	0	0
T20	30481	29901	0	0
T31	330497	329673	0	0
T32	87324	85975	0	0
T39	35864	34991	0	0
T47	21476	20644	0	0
T62	30774	29981	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Unreachable
1	0	Covered	T11,T63,T12

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T13
0	1	Unreachable
1	0	Covered	T11,T12,T13

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T11,T12,T13
0	0	1	Covered	T11,T12,T13
0	0	0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T11,T12,T13
0	0	1	Covered	T11,T12,T13
0	0	0	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	22678979	91085	0	0
DstReqKnown_A	241561	206720	0	0
SrcAckBusyChk_A	22678979	224	0	0
SrcBusyKnown_A	22678979	22539838	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22678979	91085	0	0
T11	49951	478	0	0
T12	42379	317	0	0
T13	50369	392	0	0
T19	309259	4206	0	0
T31	330497	2314	0	0
T32	87324	728	0	0
T35	156496	800	0	0
T38	323644	2352	0	0
T41	88782	0	0	0
T46	0	5751	0	0
T57	76125	702	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241561	206720	0	0
T11	715	490	0	0
T12	690	466	0	0
T13	677	451	0	0
T19	2822	2599	0	0
T20	603	377	0	0
T31	3024	2803	0	0
T32	949	724	0	0
T39	561	336	0	0
T47	438	214	0	0
T62	534	310	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22678979	224	0	0
T11	49951	1	0	0
T12	42379	1	0	0
T13	50369	1	0	0
T19	309259	10	0	0
T31	330497	6	0	0
T32	87324	2	0	0
T35	156496	2	0	0
T38	323644	6	0	0
T41	88782	0	0	0
T46	0	14	0	0
T57	76125	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22678979	22539838	0	0
T11	49951	49293	0	0
T12	42379	41781	0	0
T13	50369	49318	0	0
T19	309259	308113	0	0
T20	30481	29901	0	0
T31	330497	329673	0	0
T32	87324	85975	0	0
T39	35864	34991	0	0
T47	21476	20644	0	0
T62	30774	29981	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Unreachable
1	0	Covered	T11,T12,T13

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T13
0	1	Unreachable
1	0	Covered	T11,T12,T13

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T11,T12,T13
0	0	1	Covered	T11,T12,T13
0	0	0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T11,T12,T13
0	0	1	Covered	T11,T12,T13
0	0	0	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	22678979	84695	0	0
DstReqKnown_A	241561	206720	0	0
SrcAckBusyChk_A	22678979	212	0	0
SrcBusyKnown_A	22678979	22539838	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22678979	84695	0	0
T11	49951	415	0	0
T12	42379	349	0	0
T13	50369	384	0	0
T19	309259	1102	0	0
T31	330497	1010	0	0
T32	87324	764	0	0
T35	156496	787	0	0
T38	323644	5764	0	0
T41	88782	0	0	0
T46	0	2519	0	0
T57	76125	752	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241561	206720	0	0
T11	715	490	0	0
T12	690	466	0	0
T13	677	451	0	0
T19	2822	2599	0	0
T20	603	377	0	0
T31	3024	2803	0	0
T32	949	724	0	0
T39	561	336	0	0
T47	438	214	0	0
T62	534	310	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22678979	212	0	0
T11	49951	1	0	0
T12	42379	1	0	0
T13	50369	1	0	0
T19	309259	3	0	0
T31	330497	3	0	0
T32	87324	2	0	0
T35	156496	2	0	0
T38	323644	14	0	0
T41	88782	0	0	0
T46	0	7	0	0
T57	76125	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22678979	22539838	0	0
T11	49951	49293	0	0
T12	42379	41781	0	0
T13	50369	49318	0	0
T19	309259	308113	0	0
T20	30481	29901	0	0
T31	330497	329673	0	0
T32	87324	85975	0	0
T39	35864	34991	0	0
T47	21476	20644	0	0
T62	30774	29981	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Unreachable
1	0	Covered	T11,T12,T13

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T13
0	1	Unreachable
1	0	Covered	T11,T12,T13

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T11,T12,T13
0	0	1	Covered	T11,T12,T13
0	0	0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T11,T12,T13
0	0	1	Covered	T11,T12,T13
0	0	0	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	22678979	91057	0	0
DstReqKnown_A	241561	206720	0	0
SrcAckBusyChk_A	22678979	227	0	0
SrcBusyKnown_A	22678979	22539838	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22678979	91057	0	0
T11	49951	441	0	0
T12	42379	317	0	0
T13	50369	443	0	0
T19	309259	3846	0	0
T31	330497	1493	0	0
T32	87324	729	0	0
T35	156496	857	0	0
T38	323644	354	0	0
T41	88782	0	0	0
T46	0	3458	0	0
T57	76125	655	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241561	206720	0	0
T11	715	490	0	0
T12	690	466	0	0
T13	677	451	0	0
T19	2822	2599	0	0
T20	603	377	0	0
T31	3024	2803	0	0
T32	949	724	0	0
T39	561	336	0	0
T47	438	214	0	0
T62	534	310	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22678979	227	0	0
T11	49951	1	0	0
T12	42379	1	0	0
T13	50369	1	0	0
T19	309259	9	0	0
T31	330497	4	0	0
T32	87324	2	0	0
T35	156496	2	0	0
T38	323644	1	0	0
T41	88782	0	0	0
T46	0	9	0	0
T57	76125	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22678979	22539838	0	0
T11	49951	49293	0	0
T12	42379	41781	0	0
T13	50369	49318	0	0
T19	309259	308113	0	0
T20	30481	29901	0	0
T31	330497	329673	0	0
T32	87324	85975	0	0
T39	35864	34991	0	0
T47	21476	20644	0	0
T62	30774	29981	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Unreachable
1	0	Covered	T11,T12,T13

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T13
0	1	Unreachable
1	0	Covered	T11,T12,T13

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T11,T12,T13
0	0	1	Covered	T11,T12,T13
0	0	0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T11,T12,T13
0	0	1	Covered	T11,T12,T13
0	0	0	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	22678979	90395	0	0
DstReqKnown_A	241561	206720	0	0
SrcAckBusyChk_A	22678979	225	0	0
SrcBusyKnown_A	22678979	22539838	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22678979	90395	0	0
T11	49951	452	0	0
T12	42379	331	0	0
T13	50369	457	0	0
T19	309259	1169	0	0
T31	330497	4764	0	0
T32	87324	800	0	0
T35	156496	840	0	0
T38	323644	5751	0	0
T41	88782	0	0	0
T46	0	6153	0	0
T57	76125	712	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241561	206720	0	0
T11	715	490	0	0
T12	690	466	0	0
T13	677	451	0	0
T19	2822	2599	0	0
T20	603	377	0	0
T31	3024	2803	0	0
T32	949	724	0	0
T39	561	336	0	0
T47	438	214	0	0
T62	534	310	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22678979	225	0	0
T11	49951	1	0	0
T12	42379	1	0	0
T13	50369	1	0	0
T19	309259	3	0	0
T31	330497	12	0	0
T32	87324	2	0	0
T35	156496	2	0	0
T38	323644	14	0	0
T41	88782	0	0	0
T46	0	15	0	0
T57	76125	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22678979	22539838	0	0
T11	49951	49293	0	0
T12	42379	41781	0	0
T13	50369	49318	0	0
T19	309259	308113	0	0
T20	30481	29901	0	0
T31	330497	329673	0	0
T32	87324	85975	0	0
T39	35864	34991	0	0
T47	21476	20644	0	0
T62	30774	29981	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Unreachable
1	0	Covered	T11,T12,T13

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T13
0	1	Unreachable
1	0	Covered	T11,T12,T13

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T11,T12,T13
0	0	1	Covered	T11,T12,T13
0	0	0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T11,T12,T13
0	0	1	Covered	T11,T12,T13
0	0	0	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	22678979	74204	0	0
DstReqKnown_A	241561	206720	0	0
SrcAckBusyChk_A	22678979	188	0	0
SrcBusyKnown_A	22678979	22539838	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22678979	74204	0	0
T11	49951	434	0	0
T12	42379	334	0	0
T13	50369	445	0	0
T19	309259	265	0	0
T31	330497	2832	0	0
T32	87324	749	0	0
T35	156496	829	0	0
T38	323644	2783	0	0
T41	88782	0	0	0
T46	0	2944	0	0
T57	76125	784	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241561	206720	0	0
T11	715	490	0	0
T12	690	466	0	0
T13	677	451	0	0
T19	2822	2599	0	0
T20	603	377	0	0
T31	3024	2803	0	0
T32	949	724	0	0
T39	561	336	0	0
T47	438	214	0	0
T62	534	310	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22678979	188	0	0
T11	49951	1	0	0
T12	42379	1	0	0
T13	50369	1	0	0
T19	309259	1	0	0
T31	330497	7	0	0
T32	87324	2	0	0
T35	156496	2	0	0
T38	323644	7	0	0
T41	88782	0	0	0
T46	0	8	0	0
T57	76125	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22678979	22539838	0	0
T11	49951	49293	0	0
T12	42379	41781	0	0
T13	50369	49318	0	0
T19	309259	308113	0	0
T20	30481	29901	0	0
T31	330497	329673	0	0
T32	87324	85975	0	0
T39	35864	34991	0	0
T47	21476	20644	0	0
T62	30774	29981	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Unreachable
1	0	Covered	T11,T12,T13

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T13
0	1	Unreachable
1	0	Covered	T11,T12,T13

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T11,T12,T13
0	0	1	Covered	T11,T12,T13
0	0	0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T11,T12,T13
0	0	1	Covered	T11,T12,T13
0	0	0	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	22678979	72152	0	0
DstReqKnown_A	241561	206720	0	0
SrcAckBusyChk_A	22678979	181	0	0
SrcBusyKnown_A	22678979	22539838	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22678979	72152	0	0
T11	49951	391	0	0
T12	42379	314	0	0
T13	50369	478	0	0
T19	309259	2558	0	0
T31	330497	329	0	0
T32	87324	756	0	0
T35	156496	878	0	0
T38	323644	3580	0	0
T41	88782	0	0	0
T46	0	4375	0	0
T57	76125	781	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241561	206720	0	0
T11	715	490	0	0
T12	690	466	0	0
T13	677	451	0	0
T19	2822	2599	0	0
T20	603	377	0	0
T31	3024	2803	0	0
T32	949	724	0	0
T39	561	336	0	0
T47	438	214	0	0
T62	534	310	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22678979	181	0	0
T11	49951	1	0	0
T12	42379	1	0	0
T13	50369	1	0	0
T19	309259	6	0	0
T31	330497	1	0	0
T32	87324	2	0	0
T35	156496	2	0	0
T38	323644	9	0	0
T41	88782	0	0	0
T46	0	11	0	0
T57	76125	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22678979	22539838	0	0
T11	49951	49293	0	0
T12	42379	41781	0	0
T13	50369	49318	0	0
T19	309259	308113	0	0
T20	30481	29901	0	0
T31	330497	329673	0	0
T32	87324	85975	0	0
T39	35864	34991	0	0
T47	21476	20644	0	0
T62	30774	29981	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Unreachable
1	0	Covered	T11,T12,T13

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T13
0	1	Unreachable
1	0	Covered	T11,T12,T13

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T11,T12,T13
0	0	1	Covered	T11,T12,T13
0	0	0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T11,T12,T13
0	0	1	Covered	T11,T12,T13
0	0	0	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	22678979	75402	0	0
DstReqKnown_A	241561	206720	0	0
SrcAckBusyChk_A	22678979	189	0	0
SrcBusyKnown_A	22678979	22539838	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22678979	75402	0	0
T11	49951	471	0	0
T12	42379	342	0	0
T13	50369	454	0	0
T19	309259	4168	0	0
T32	87324	620	0	0
T35	156496	831	0	0
T38	323644	3935	0	0
T41	88782	0	0	0
T46	628007	2039	0	0
T48	0	7152	0	0
T57	76125	727	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241561	206720	0	0
T11	715	490	0	0
T12	690	466	0	0
T13	677	451	0	0
T19	2822	2599	0	0
T20	603	377	0	0
T31	3024	2803	0	0
T32	949	724	0	0
T39	561	336	0	0
T47	438	214	0	0
T62	534	310	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22678979	189	0	0
T11	49951	1	0	0
T12	42379	1	0	0
T13	50369	1	0	0
T19	309259	10	0	0
T32	87324	2	0	0
T35	156496	2	0	0
T38	323644	10	0	0
T41	88782	0	0	0
T46	628007	6	0	0
T48	0	18	0	0
T57	76125	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22678979	22539838	0	0
T11	49951	49293	0	0
T12	42379	41781	0	0
T13	50369	49318	0	0
T19	309259	308113	0	0
T20	30481	29901	0	0
T31	330497	329673	0	0
T32	87324	85975	0	0
T39	35864	34991	0	0
T47	21476	20644	0	0
T62	30774	29981	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Unreachable
1	0	Covered	T11,T12,T13

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T13
0	1	Unreachable
1	0	Covered	T11,T12,T13

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T11,T12,T13
0	0	1	Covered	T11,T12,T13
0	0	0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T11,T12,T13
0	0	1	Covered	T11,T12,T13
0	0	0	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	22678979	85319	0	0
DstReqKnown_A	241561	206720	0	0
SrcAckBusyChk_A	22678979	210	0	0
SrcBusyKnown_A	22678979	22539838	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22678979	85319	0	0
T11	49951	371	0	0
T12	42379	253	0	0
T13	50369	441	0	0
T19	309259	2513	0	0
T31	330497	3711	0	0
T32	87324	759	0	0
T35	156496	856	0	0
T38	323644	794	0	0
T41	88782	0	0	0
T46	0	3496	0	0
T57	76125	777	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241561	206720	0	0
T11	715	490	0	0
T12	690	466	0	0
T13	677	451	0	0
T19	2822	2599	0	0
T20	603	377	0	0
T31	3024	2803	0	0
T32	949	724	0	0
T39	561	336	0	0
T47	438	214	0	0
T62	534	310	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22678979	210	0	0
T11	49951	1	0	0
T12	42379	1	0	0
T13	50369	1	0	0
T19	309259	6	0	0
T31	330497	9	0	0
T32	87324	2	0	0
T35	156496	2	0	0
T38	323644	2	0	0
T41	88782	0	0	0
T46	0	9	0	0
T57	76125	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22678979	22539838	0	0
T11	49951	49293	0	0
T12	42379	41781	0	0
T13	50369	49318	0	0
T19	309259	308113	0	0
T20	30481	29901	0	0
T31	330497	329673	0	0
T32	87324	85975	0	0
T39	35864	34991	0	0
T47	21476	20644	0	0
T62	30774	29981	0	0