Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.i2c2_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	132450	1			T32	10		T33	286		T34	1
values[2]	9632	1			T33	4		T101	151		T230	4
values[3]	3981	1			T101	78		T395	137		T396	7
values[4]	2270	1			T101	27		T395	82		T396	5
values[5]	1427	1			T101	13		T395	74		T396	7
values[6]	987	1			T101	8		T395	71		T396	15
values[7]	807	1			T101	4		T395	77		T396	12
values[8]	597	1			T395	66		T396	7		T771	2
values[9]	507	1			T395	40		T396	3		T346	11
values[10]	448	1			T395	41		T396	13		T346	3
values[11]	433	1			T395	49		T396	7		T537	16
values[12]	340	1			T395	4		T396	15		T537	10
values[13]	323	1			T396	3		T537	7		T772	2
values[14]	332	1			T396	5		T537	5		T772	2
values[15]	282	1			T396	3		T537	4		T772	2
values[16]	276	1			T396	4		T537	4		T772	3
values[17]	292	1			T396	3		T537	6		T772	2
values[18]	248	1			T396	6		T537	4		T772	2
values[19]	269	1			T396	26		T537	4		T772	2
values[20]	296	1			T396	7		T537	6		T772	2
values[21]	260	1			T396	4		T537	5		T772	2
values[22]	274	1			T396	4		T537	1		T772	2
values[23]	235	1			T396	5		T772	2		T781	2
values[24]	261	1			T396	3		T772	2		T781	2
values[25]	265	1			T396	20		T772	2		T781	2
values[26]	280	1			T396	6		T772	2		T781	2
values[27]	261	1			T396	4		T772	2		T781	2
values[28]	249	1			T396	7		T772	2		T781	2
values[29]	253	1			T396	7		T772	2		T781	2
values[30]	227	1			T396	4		T772	2		T781	2
values[31]	258	1			T396	9		T772	2		T781	2
values[32]	242	1			T396	7		T772	2		T781	2
values[33]	239	1			T396	4		T772	2		T781	2
values[34]	254	1			T396	4		T772	2		T781	2
values[35]	261	1			T396	17		T772	2		T781	2
values[36]	273	1			T396	8		T772	2		T781	2
values[37]	225	1			T396	5		T772	2		T781	2
values[38]	244	1			T396	6		T772	2		T781	2
values[39]	271	1			T396	5		T772	2		T781	2
values[40]	235	1			T396	5		T772	2		T781	2
values[41]	223	1			T396	9		T772	2		T781	2
values[42]	206	1			T396	5		T772	2		T781	2
values[43]	250	1			T396	20		T772	2		T781	2
values[44]	231	1			T396	7		T772	2		T781	2
values[45]	227	1			T396	6		T772	2		T781	2
values[46]	251	1			T396	7		T772	2		T781	2
values[47]	231	1			T396	12		T772	2		T781	2
values[48]	240	1			T396	20		T772	2		T781	2
values[49]	261	1			T396	15		T772	2		T781	2
values[50]	243	1			T396	5		T772	2		T781	2
values[51]	221	1			T396	3		T772	2		T781	2
values[52]	240	1			T396	6		T772	2		T781	2
values[53]	247	1			T396	7		T772	2		T781	2
values[54]	238	1			T396	4		T772	2		T781	2
values[55]	271	1			T396	17		T772	2		T781	2
values[56]	206	1			T396	5		T772	2		T781	2
values[57]	214	1			T396	5		T772	2		T781	2
values[58]	234	1			T396	9		T772	2		T781	2
values[59]	198	1			T396	8		T772	2		T781	2
values[60]	222	1			T396	7		T772	2		T781	2
values[61]	235	1			T396	3		T772	2		T781	2
values[62]	196	1			T396	10		T772	2		T781	2
values[63]	222	1			T396	6		T772	2		T781	2
values[64]	193	1			T396	2		T772	2		T781	2
values[65]	138	1			T396	4		T772	2		T781	2
values[66]	170	1			T396	4		T772	2		T781	2
values[67]	127	1			T396	7		T772	2		T781	2
values[68]	162	1			T396	9		T772	2		T781	2
values[69]	175	1			T396	6		T772	2		T781	2
values[70]	161	1			T396	12		T772	2		T781	2
values[71]	119	1			T396	2		T772	2		T781	3
values[72]	110	1			T772	2		T781	4		T420	1
values[73]	104	1			T772	2		T781	4		T420	1
values[74]	114	1			T772	2		T781	2		T420	1
values[75]	110	1			T772	2		T781	5		T420	1
values[76]	126	1			T772	2		T781	22		T420	1
values[77]	77	1			T772	2		T781	3		T420	7
values[78]	65	1			T772	3		T781	3		T420	2
values[79]	94	1			T772	5		T781	5		T420	11
values[80]	101	1			T772	3		T781	12		T420	3
values[81]	108	1			T772	4		T781	6		T420	2
values[82]	122	1			T772	13		T781	6		T420	5
values[83]	104	1			T772	3		T781	11		T420	1
values[84]	88	1			T772	5		T781	3		T420	4
values[85]	83	1			T772	3		T781	2		T420	6
values[86]	82	1			T772	7		T781	6		T420	1
values[87]	101	1			T772	2		T781	5		T420	2
values[88]	96	1			T772	7		T781	2		T420	5
values[89]	104	1			T772	5		T781	2		T420	2
values[90]	106	1			T772	4		T781	2		T420	7
values[91]	95	1			T772	9		T781	2		T420	1
values[92]	79	1			T772	2		T781	4		T420	1
values[93]	84	1			T772	3		T781	3		T420	2
values[94]	85	1			T772	6		T781	9		T420	3
values[95]	82	1			T772	7		T781	4		T420	7
values[96]	77	1			T772	4		T781	4		T420	1
values[97]	96	1			T772	3		T781	2		T420	1
values[98]	86	1			T772	4		T781	5		T420	5
values[99]	87	1			T772	4		T781	6		T420	3
values[100]	98	1			T772	3		T781	2		T420	1
values[101]	82	1			T772	3		T781	3		T420	1
values[102]	90	1			T772	5		T781	2		T420	1
values[103]	77	1			T772	3		T781	2		T420	3
values[104]	75	1			T772	2		T781	3		T420	1
values[105]	74	1			T772	5		T781	2		T420	1
values[106]	81	1			T772	15		T781	2		T420	2
values[107]	83	1			T772	10		T781	2		T420	3
values[108]	77	1			T772	7		T781	2		T420	4
values[109]	69	1			T772	6		T781	2		T420	2
values[110]	67	1			T772	2		T781	3		T420	1
values[111]	86	1			T772	7		T781	3		T420	2
values[112]	84	1			T772	2		T781	3		T420	2
values[113]	79	1			T772	2		T781	6		T420	1
values[114]	65	1			T772	4		T781	5		T420	1
values[115]	66	1			T772	6		T781	5		T420	1
values[116]	79	1			T772	2		T781	4		T420	3
values[117]	60	1			T772	3		T781	5		T420	1
values[118]	66	1			T772	3		T781	3		T420	1
values[119]	85	1			T772	3		T781	6		T420	2
values[120]	88	1			T772	5		T781	5		T420	3
values[121]	86	1			T772	3		T781	4		T420	9
values[122]	77	1			T772	4		T781	3		T420	1
values[123]	77	1			T772	5		T781	2		T420	2
values[124]	65	1			T772	2		T781	3		T420	6
values[125]	57	1			T772	4		T781	2		T420	5
values[126]	79	1			T772	4		T781	9		T420	1
values[127]	831	1			T772	65		T781	59		T420	20
values[128]	7726	1			T772	546		T781	498		T420	246