Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.69	95.42	94.23	98.00		94.87	97.93	99.69

Total tests in report: 2873

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
27.25	27.25	26.80	26.80	22.96	22.96	21.92	21.92			44.66	44.66	43.68	43.68	3.49	3.49	/workspace/coverage/cover_reg_top/19.chip_same_csr_outstanding.3041088092
54.05	26.80	70.30	43.49	59.33	36.37	56.36	34.44			66.45	21.78	49.44	5.76	22.45	18.96	/workspace/coverage/cover_reg_top/68.xbar_stress_all.313755197
69.38	15.33	81.88	11.59	77.58	18.25	63.82	7.46			84.30	17.86	86.25	36.80	22.45	0.00	/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.2349278514
73.94	4.56	81.88	0.00	77.74	0.16	63.82	0.00			84.35	0.05	86.25	0.00	49.58	27.13	/workspace/coverage/cover_reg_top/48.xbar_access_same_device_slow_rsp.1504405151
77.97	4.04	83.47	1.58	78.19	0.44	80.57	16.75			84.78	0.43	91.26	5.02	49.58	0.00	/workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.472587330
80.73	2.75	83.47	0.00	78.19	0.00	80.57	0.00			84.78	0.00	91.26	0.00	66.09	16.51	/workspace/coverage/cover_reg_top/85.xbar_access_same_device_slow_rsp.3088833263
82.69	1.96	83.55	0.08	78.51	0.33	80.57	0.00			84.91	0.12	91.26	0.00	77.33	11.24	/workspace/coverage/cover_reg_top/25.xbar_access_same_device_slow_rsp.1115202742
84.21	1.52	87.80	4.25	80.62	2.10	80.88	0.31			87.36	2.45	91.26	0.00	77.33	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_0.2783273539
85.34	1.13	87.80	0.00	80.62	0.00	80.88	0.00			87.36	0.00	91.26	0.00	84.14	6.81	/workspace/coverage/cover_reg_top/65.xbar_access_same_device_slow_rsp.3603962019
86.25	0.91	87.80	0.00	80.91	0.29	80.88	0.00			87.46	0.11	91.26	0.00	89.17	5.03	/workspace/coverage/cover_reg_top/80.xbar_stress_all.191607960
87.11	0.87	88.54	0.74	81.08	0.17	80.90	0.02			87.64	0.18	95.35	4.09	89.17	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.1918312888
87.93	0.81	89.19	0.64	83.17	2.09	80.92	0.03			89.77	2.13	95.35	0.00	89.17	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1824243094
88.74	0.81	89.26	0.07	84.05	0.88	81.70	0.77			89.90	0.13	95.35	0.00	92.20	3.03	/workspace/coverage/cover_reg_top/5.xbar_stress_all_with_error.2090176630
89.54	0.79	89.26	0.00	84.05	0.00	86.44	4.75			89.90	0.00	95.35	0.00	92.20	0.00	/workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.120526008
90.31	0.78	91.38	2.13	85.11	1.06	86.68	0.24			91.14	1.24	95.35	0.00	92.20	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_20.3992191382
90.99	0.68	92.09	0.71	85.75	0.64	88.43	1.74			91.96	0.82	95.54	0.19	92.20	0.00	/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.3260394301
91.51	0.52	92.13	0.04	88.40	2.65	88.43	0.00			91.96	0.00	95.54	0.00	92.62	0.41	/workspace/coverage/cover_reg_top/12.chip_tl_errors.261177697
92.03	0.52	92.15	0.01	88.41	0.01	91.51	3.09			91.96	0.00	95.54	0.00	92.62	0.00	/workspace/coverage/default/1.chip_sw_edn_entropy_reqs.236873925
92.47	0.44	93.05	0.91	89.19	0.79	91.64	0.13			92.77	0.82	95.54	0.00	92.62	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_10.2963413049
92.81	0.34	93.08	0.03	89.39	0.20	91.66	0.02			92.86	0.08	95.54	0.00	94.36	1.74	/workspace/coverage/cover_reg_top/35.xbar_access_same_device_slow_rsp.3416886256
93.15	0.33	93.08	0.00	89.39	0.00	91.66	0.00			92.86	0.00	95.54	0.00	96.34	1.99	/workspace/coverage/cover_reg_top/70.xbar_access_same_device_slow_rsp.4219212512
93.46	0.31	93.43	0.35	90.12	0.73	91.68	0.02			93.62	0.76	95.54	0.00	96.35	0.01	/workspace/coverage/default/0.chip_jtag_csr_rw.3788736566
93.71	0.25	93.71	0.28	90.25	0.13	91.74	0.07			93.73	0.12	96.47	0.93	96.35	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.658420738
93.91	0.20	93.74	0.03	90.62	0.37	92.37	0.62			93.78	0.05	96.47	0.00	96.48	0.13	/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.3383631814
94.06	0.15	93.94	0.20	90.91	0.29	92.76	0.40			93.78	0.00	96.47	0.00	96.48	0.00	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3247505940
94.21	0.15	93.94	0.00	90.91	0.00	93.65	0.89			93.78	0.00	96.47	0.00	96.48	0.00	/workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.33556498
94.33	0.12	93.98	0.04	90.97	0.05	93.65	0.00			93.81	0.02	96.47	0.00	97.11	0.62	/workspace/coverage/cover_reg_top/59.xbar_random_large_delays.1400116828
94.45	0.12	94.15	0.17	91.02	0.05	93.93	0.29			93.83	0.02	96.65	0.19	97.11	0.00	/workspace/coverage/default/2.chip_sw_data_integrity_escalation.3015740146
94.57	0.12	94.15	0.00	91.10	0.09	93.93	0.00			93.83	0.00	96.65	0.00	97.73	0.62	/workspace/coverage/cover_reg_top/87.xbar_access_same_device_slow_rsp.2629365821
94.68	0.11	94.15	0.00	91.10	0.00	94.62	0.68			93.83	0.00	96.65	0.00	97.73	0.00	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.3865455392
94.79	0.11	94.18	0.03	91.12	0.02	95.23	0.61			93.86	0.02	96.65	0.00	97.73	0.00	/workspace/coverage/default/90.chip_sw_all_escalation_resets.3223094929
94.90	0.11	94.18	0.00	91.77	0.65	95.23	0.00			93.86	0.00	96.65	0.00	97.73	0.00	/workspace/coverage/cover_reg_top/16.chip_tl_errors.230442759
95.01	0.11	94.19	0.01	91.95	0.17	95.24	0.01			93.87	0.02	96.65	0.00	98.15	0.42	/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.1060084682
95.11	0.10	94.19	0.01	92.23	0.29	95.24	0.00			94.20	0.33	96.65	0.00	98.15	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.559643965
95.19	0.08	94.19	0.00	92.23	0.00	95.72	0.49			94.20	0.00	96.65	0.00	98.15	0.00	/workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.1857507718
95.27	0.08	94.31	0.12	92.43	0.20	95.73	0.01			94.35	0.15	96.65	0.00	98.15	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_retention.1348139901
95.34	0.07	94.43	0.12	92.52	0.08	95.83	0.11			94.45	0.10	96.65	0.00	98.15	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.3994685001
95.40	0.07	94.48	0.06	92.52	0.00	95.97	0.14			94.46	0.01	96.84	0.19	98.15	0.00	/workspace/coverage/default/0.rom_raw_unlock.1859867802
95.47	0.06	94.48	0.00	92.52	0.00	96.34	0.37			94.46	0.00	96.84	0.00	98.15	0.00	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3882474806
95.52	0.06	94.49	0.01	92.68	0.16	96.34	0.00			94.64	0.18	96.84	0.00	98.15	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.662194498
95.58	0.05	94.49	0.00	92.68	0.00	96.65	0.31			94.64	0.00	96.84	0.00	98.15	0.00	/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.4178509702
95.62	0.05	94.49	0.00	92.97	0.30	96.65	0.00			94.64	0.00	96.84	0.00	98.15	0.00	/workspace/coverage/cover_reg_top/28.chip_tl_errors.3865660949
95.67	0.05	94.51	0.02	92.98	0.01	96.90	0.25			94.64	0.00	96.84	0.00	98.15	0.00	/workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.2744235679
95.71	0.04	94.54	0.03	92.99	0.01	96.90	0.01			94.65	0.01	97.03	0.19	98.17	0.01	/workspace/coverage/default/39.chip_sw_all_escalation_resets.3848664148
95.75	0.04	94.55	0.01	93.00	0.01	96.90	0.00			94.67	0.02	97.21	0.19	98.18	0.01	/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.3488052792
95.79	0.04	94.55	0.01	93.01	0.01	96.92	0.01			94.68	0.01	97.40	0.19	98.19	0.01	/workspace/coverage/default/69.chip_sw_all_escalation_resets.103873213
95.83	0.04	94.56	0.01	93.03	0.01	96.92	0.01			94.69	0.01	97.58	0.19	98.20	0.01	/workspace/coverage/default/6.chip_sw_all_escalation_resets.138825366
95.87	0.04	94.56	0.01	93.04	0.01	96.92	0.00			94.70	0.01	97.77	0.19	98.21	0.01	/workspace/coverage/default/32.chip_sw_all_escalation_resets.4009096611
95.91	0.04	94.74	0.17	93.09	0.05	96.92	0.00			94.70	0.00	97.77	0.00	98.21	0.00	/workspace/coverage/default/0.chip_sw_gpio.320893614
95.94	0.03	94.74	0.00	93.13	0.04	97.07	0.14			94.72	0.02	97.77	0.00	98.21	0.00	/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.1714340717
95.97	0.03	94.74	0.00	93.13	0.00	97.07	0.00			94.72	0.00	97.96	0.19	98.21	0.00	/workspace/coverage/default/4.chip_sw_data_integrity_escalation.2584177
96.00	0.03	94.74	0.00	93.13	0.00	97.24	0.17			94.72	0.00	97.96	0.00	98.21	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.3209214035
96.03	0.03	94.74	0.00	93.15	0.01	97.24	0.00			94.72	0.00	97.96	0.00	98.35	0.14	/workspace/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.3449654245
96.05	0.02	94.74	0.00	93.29	0.14	97.24	0.00			94.72	0.00	97.96	0.00	98.35	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_0.4218699364
96.07	0.02	94.79	0.06	93.35	0.05	97.24	0.00			94.75	0.02	97.96	0.00	98.35	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.2377362077
96.09	0.02	94.87	0.08	93.35	0.00	97.28	0.05			94.75	0.01	97.96	0.00	98.35	0.00	/workspace/coverage/default/0.chip_tap_straps_rma.1960557793
96.11	0.02	94.87	0.00	93.47	0.12	97.28	0.00			94.75	0.00	97.96	0.00	98.35	0.00	/workspace/coverage/cover_reg_top/19.chip_tl_errors.513524587
96.13	0.02	94.87	0.00	93.47	0.00	97.40	0.12			94.75	0.00	97.96	0.00	98.35	0.00	/workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.902595147
96.15	0.02	94.87	0.00	93.47	0.00	97.40	0.00			94.75	0.00	97.96	0.00	98.46	0.11	/workspace/coverage/cover_reg_top/22.xbar_stress_all_with_reset_error.3733385793
96.17	0.02	94.89	0.02	93.50	0.03	97.44	0.04			94.75	0.00	97.96	0.00	98.47	0.01	/workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.560722315
96.19	0.02	94.90	0.01	93.50	0.00	97.53	0.09			94.76	0.01	97.96	0.00	98.47	0.00	/workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.3815398942
96.20	0.02	94.94	0.04	93.52	0.02	97.53	0.00			94.80	0.03	97.96	0.00	98.47	0.00	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.2934687152
96.22	0.01	94.98	0.04	93.54	0.02	97.55	0.02			94.80	0.00	97.96	0.00	98.47	0.00	/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.835542947
96.23	0.01	94.98	0.01	93.56	0.02	97.58	0.03			94.82	0.02	97.96	0.00	98.47	0.00	/workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.2193033683
96.24	0.01	94.98	0.00	93.56	0.00	97.58	0.00			94.82	0.00	97.96	0.00	98.54	0.07	/workspace/coverage/cover_reg_top/28.xbar_stress_all_with_reset_error.1371968673
96.25	0.01	94.98	0.00	93.63	0.07	97.58	0.00			94.82	0.00	97.96	0.00	98.54	0.00	/workspace/coverage/cover_reg_top/17.chip_tl_errors.1479867508
96.26	0.01	94.98	0.00	93.70	0.07	97.58	0.00			94.82	0.00	97.96	0.00	98.54	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_20.449086468
96.27	0.01	95.02	0.04	93.72	0.02	97.58	0.00			94.83	0.01	97.96	0.00	98.54	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_wake.2880239488
96.29	0.01	95.02	0.00	93.79	0.07	97.58	0.00			94.83	0.00	97.96	0.00	98.54	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_0.2702948143
96.30	0.01	95.03	0.01	93.80	0.02	97.60	0.02			94.84	0.02	97.96	0.00	98.54	0.00	/workspace/coverage/default/0.chip_sw_usbdev_pincfg.3771312198
96.31	0.01	95.03	0.01	93.84	0.03	97.62	0.02			94.85	0.01	97.96	0.00	98.54	0.00	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.297618714
96.32	0.01	95.06	0.03	93.84	0.00	97.65	0.03			94.85	0.00	97.96	0.00	98.54	0.00	/workspace/coverage/default/0.chip_sw_spi_device_pass_through.2420659670
96.33	0.01	95.06	0.00	93.84	0.00	97.65	0.00			94.85	0.00	97.96	0.00	98.60	0.06	/workspace/coverage/cover_reg_top/25.xbar_stress_all_with_rand_reset.3582238435
96.34	0.01	95.07	0.01	93.89	0.05	97.65	0.00			94.85	0.00	97.96	0.00	98.60	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.481708061
96.35	0.01	95.07	0.00	93.89	0.01	97.65	0.00			94.85	0.00	97.96	0.00	98.65	0.05	/workspace/coverage/cover_reg_top/12.xbar_stress_all.444322223
96.35	0.01	95.07	0.00	93.89	0.00	97.65	0.00			94.85	0.00	97.96	0.00	98.69	0.05	/workspace/coverage/cover_reg_top/41.xbar_stress_all_with_reset_error.1908921488
96.36	0.01	95.07	0.00	93.89	0.00	97.70	0.05			94.85	0.00	97.96	0.00	98.69	0.00	/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.1236353597
96.37	0.01	95.07	0.00	93.94	0.04	97.70	0.00			94.85	0.00	97.96	0.00	98.69	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_10.298863629
96.37	0.01	95.07	0.01	93.97	0.04	97.70	0.00			94.85	0.00	97.96	0.00	98.69	0.00	/workspace/coverage/default/16.chip_sw_uart_rand_baudrate.2127371464
96.38	0.01	95.07	0.00	93.97	0.00	97.74	0.04			94.85	0.00	97.96	0.00	98.69	0.00	/workspace/coverage/cover_reg_top/7.chip_csr_mem_rw_with_rand_reset.2164231485
96.39	0.01	95.07	0.00	93.97	0.00	97.74	0.00			94.85	0.00	97.96	0.00	98.73	0.04	/workspace/coverage/cover_reg_top/6.xbar_stress_all_with_rand_reset.2167133312
96.39	0.01	95.09	0.02	93.97	0.00	97.75	0.01			94.85	0.00	97.96	0.00	98.73	0.00	/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.1284889271
96.40	0.01	95.10	0.01	93.97	0.00	97.77	0.02			94.85	0.00	97.96	0.00	98.73	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.223956681
96.40	0.01	95.10	0.00	93.97	0.00	97.79	0.03			94.85	0.00	97.96	0.00	98.73	0.00	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1176272106
96.41	0.01	95.10	0.00	93.97	0.00	97.82	0.03			94.85	0.00	97.96	0.00	98.73	0.00	/workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.315096468
96.41	0.01	95.10	0.00	94.00	0.03	97.82	0.00			94.85	0.00	97.96	0.00	98.73	0.00	/workspace/coverage/cover_reg_top/22.chip_tl_errors.3569420132
96.42	0.01	95.10	0.00	94.02	0.02	97.83	0.01			94.85	0.00	97.96	0.00	98.73	0.00	/workspace/coverage/default/0.chip_sw_alert_test.1241723213
96.42	0.01	95.10	0.00	94.02	0.00	97.83	0.00			94.85	0.00	97.96	0.00	98.75	0.02	/workspace/coverage/cover_reg_top/18.xbar_stress_all_with_reset_error.1117324120
96.42	0.01	95.10	0.00	94.02	0.00	97.83	0.00			94.85	0.00	97.96	0.00	98.78	0.02	/workspace/coverage/cover_reg_top/27.xbar_stress_all_with_reset_error.3837064032
96.43	0.01	95.10	0.00	94.04	0.02	97.83	0.00			94.85	0.00	97.96	0.00	98.78	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_20.1928388121
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96.61	0.01	95.13	0.00	94.10	0.00	97.93	0.00			94.85	0.00	97.96	0.00	99.68	0.01	/workspace/coverage/default/94.chip_sw_all_escalation_resets.2410702427
96.61	0.01	95.13	0.00	94.10	0.00	97.93	0.00			94.85	0.00	97.96	0.00	99.69	0.01	/workspace/coverage/default/98.chip_sw_all_escalation_resets.3240565620
96.61	0.01	95.14	0.01	94.10	0.00	97.94	0.01			94.85	0.00	97.96	0.00	99.69	0.00	/workspace/coverage/default/27.chip_sw_all_escalation_resets.2646591213
96.61	0.01	95.14	0.00	94.11	0.01	97.94	0.00			94.85	0.00	97.96	0.00	99.69	0.00	/workspace/coverage/cover_reg_top/10.chip_tl_errors.604955947
96.62	0.01	95.14	0.00	94.12	0.01	97.94	0.00			94.85	0.00	97.96	0.00	99.69	0.00	/workspace/coverage/cover_reg_top/15.chip_tl_errors.118165475
96.62	0.01	95.14	0.00	94.13	0.01	97.94	0.00			94.85	0.00	97.96	0.00	99.69	0.00	/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.4091426588
96.62	0.01	95.14	0.00	94.13	0.00	97.95	0.01			94.85	0.00	97.96	0.00	99.69	0.00	/workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.4172033869
96.62	0.01	95.14	0.00	94.13	0.00	97.96	0.01			94.85	0.00	97.96	0.00	99.69	0.00	/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.85094425
96.62	0.01	95.14	0.00	94.13	0.00	97.96	0.00			94.86	0.01	97.96	0.00	99.69	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.1832828920
96.62	0.01	95.14	0.00	94.13	0.00	97.96	0.00			94.87	0.01	97.96	0.00	99.69	0.00	/workspace/coverage/default/0.chip_tap_straps_dev.3624171000
96.62	0.01	95.14	0.00	94.13	0.00	97.97	0.01			94.87	0.00	97.96	0.00	99.69	0.00	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1484761787
96.63	0.01	95.14	0.00	94.14	0.01	97.97	0.00			94.87	0.00	97.96	0.00	99.69	0.00	/workspace/coverage/cover_reg_top/14.chip_tl_errors.1758757362
96.63	0.01	95.14	0.00	94.14	0.01	97.97	0.00			94.87	0.00	97.96	0.00	99.69	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_10.91853521
96.63	0.01	95.14	0.00	94.15	0.01	97.97	0.00			94.87	0.00	97.96	0.00	99.69	0.00	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.75047412
96.63	0.01	95.14	0.00	94.16	0.01	97.97	0.00			94.87	0.00	97.96	0.00	99.69	0.00	/workspace/coverage/default/0.chip_sw_uart_rand_baudrate.1083836468
96.63	0.01	95.14	0.01	94.16	0.00	97.97	0.00			94.87	0.00	97.96	0.00	99.69	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.3566433380
96.63	0.01	95.15	0.01	94.16	0.00	97.97	0.00			94.87	0.00	97.96	0.00	99.69	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.2094885198
96.63	0.01	95.16	0.01	94.16	0.00	97.97	0.00			94.87	0.00	97.96	0.00	99.69	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.1237625889
96.63	0.01	95.16	0.00	94.16	0.00	97.97	0.01			94.87	0.00	97.96	0.00	99.69	0.00	/workspace/coverage/default/0.chip_sw_edn_boot_mode.1957740213
96.63	0.01	95.16	0.00	94.16	0.00	97.97	0.01			94.87	0.00	97.96	0.00	99.69	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.51664237
96.64	0.01	95.16	0.00	94.16	0.00	97.98	0.01			94.87	0.00	97.96	0.00	99.69	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.1443165523
96.64	0.01	95.16	0.00	94.16	0.00	97.98	0.01			94.87	0.00	97.96	0.00	99.69	0.00	/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.1049087909
96.64	0.01	95.16	0.00	94.16	0.01	97.98	0.00			94.87	0.00	97.96	0.00	99.69	0.00	/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.3908046668
96.64	0.01	95.16	0.00	94.17	0.01	97.98	0.00			94.87	0.00	97.96	0.00	99.69	0.00	/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.62746630
96.64	0.01	95.16	0.00	94.17	0.01	97.98	0.00			94.87	0.00	97.96	0.00	99.69	0.00	/workspace/coverage/cover_reg_top/11.chip_csr_rw.1688071958
96.64	0.01	95.16	0.00	94.17	0.01	97.98	0.00			94.87	0.00	97.96	0.00	99.69	0.00	/workspace/coverage/cover_reg_top/15.xbar_random_slow_rsp.2058728861
96.64	0.01	95.16	0.00	94.18	0.01	97.98	0.00			94.87	0.00	97.96	0.00	99.69	0.00	/workspace/coverage/cover_reg_top/24.chip_tl_errors.3235055723
96.64	0.01	95.16	0.00	94.18	0.01	97.98	0.00			94.87	0.00	97.96	0.00	99.69	0.00	/workspace/coverage/cover_reg_top/35.xbar_stress_all_with_error.1911796149
96.64	0.01	95.16	0.00	94.18	0.01	97.98	0.00			94.87	0.00	97.96	0.00	99.69	0.00	/workspace/coverage/cover_reg_top/39.xbar_stress_all_with_error.567893599
96.64	0.01	95.16	0.00	94.19	0.01	97.98	0.00			94.87	0.00	97.96	0.00	99.69	0.00	/workspace/coverage/cover_reg_top/4.xbar_stress_all_with_error.2582012676
96.64	0.01	95.16	0.00	94.19	0.01	97.98	0.00			94.87	0.00	97.96	0.00	99.69	0.00	/workspace/coverage/cover_reg_top/51.xbar_stress_all_with_reset_error.4233407863
96.64	0.01	95.16	0.00	94.19	0.01	97.98	0.00			94.87	0.00	97.96	0.00	99.69	0.00	/workspace/coverage/cover_reg_top/75.xbar_stress_all_with_error.1789836580
96.64	0.01	95.16	0.00	94.20	0.01	97.98	0.00			94.87	0.00	97.96	0.00	99.69	0.00	/workspace/coverage/cover_reg_top/92.xbar_stress_all_with_reset_error.911590787
96.64	0.01	95.16	0.00	94.20	0.01	97.98	0.00			94.87	0.00	97.96	0.00	99.69	0.00	/workspace/coverage/cover_reg_top/95.xbar_stress_all_with_error.1751911439
96.64	0.01	95.16	0.00	94.20	0.01	97.98	0.00			94.87	0.00	97.96	0.00	99.69	0.00	/workspace/coverage/default/0.chip_sival_flash_info_access.3123330799
96.64	0.01	95.16	0.00	94.21	0.01	97.98	0.00			94.87	0.00	97.96	0.00	99.69	0.00	/workspace/coverage/default/0.chip_sw_pattgen_ios.2421982732
96.65	0.01	95.16	0.00	94.21	0.01	97.98	0.00			94.87	0.00	97.96	0.00	99.69	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.1310449132
96.65	0.01	95.16	0.00	94.22	0.01	97.98	0.00			94.87	0.00	97.96	0.00	99.69	0.00	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.2073064310
96.65	0.01	95.16	0.00	94.22	0.01	97.98	0.00			94.87	0.00	97.96	0.00	99.69	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx.2601000931
96.65	0.01	95.16	0.00	94.22	0.01	97.98	0.00			94.87	0.00	97.96	0.00	99.69	0.00	/workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.2565340040
96.65	0.01	95.16	0.00	94.23	0.01	97.98	0.00			94.87	0.00	97.96	0.00	99.69	0.00	/workspace/coverage/default/2.chip_sw_gpio.651668047
96.65	0.01	95.16	0.01	94.23	0.00	97.98	0.00			94.87	0.00	97.96	0.00	99.69	0.00	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.1954866387
96.65	0.01	95.16	0.00	94.23	0.00	97.99	0.01			94.87	0.00	97.96	0.00	99.69	0.00	/workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.2293641596
96.65	0.01	95.16	0.00	94.23	0.00	97.99	0.01			94.87	0.00	97.96	0.00	99.69	0.00	/workspace/coverage/default/0.chip_sw_edn_auto_mode.264558167
96.65	0.01	95.16	0.00	94.23	0.00	97.99	0.01			94.87	0.00	97.96	0.00	99.69	0.00	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.1667390900
96.65	0.01	95.16	0.00	94.23	0.00	97.99	0.01			94.87	0.00	97.96	0.00	99.69	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.384883123
96.65	0.01	95.16	0.00	94.23	0.00	98.00	0.01			94.87	0.00	97.96	0.00	99.69	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.2885808607
96.65	0.01	95.16	0.00	94.23	0.00	98.00	0.01			94.87	0.00	97.96	0.00	99.69	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.3065518026
96.65	0.01	95.16	0.00	94.23	0.00	98.00	0.01			94.87	0.00	97.96	0.00	99.69	0.00	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1542346163
96.65	0.01	95.16	0.00	94.23	0.00	98.00	0.01			94.87	0.00	97.96	0.00	99.69	0.00	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.514994066

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.1958573668
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.101969899
/workspace/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.583651497
/workspace/coverage/cover_reg_top/0.chip_csr_rw.94561387
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.1733430755
/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.3461924596
/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.1401130899
/workspace/coverage/cover_reg_top/0.chip_tl_errors.1050073114
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.874748902
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.2591009575
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.1836790817
/workspace/coverage/cover_reg_top/0.xbar_error_random.2209108059
/workspace/coverage/cover_reg_top/0.xbar_random.1835499059
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.666489091
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.548791026
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.1347215363
/workspace/coverage/cover_reg_top/0.xbar_same_source.1083955856
/workspace/coverage/cover_reg_top/0.xbar_smoke.663517820
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.2404357183
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.1421462013
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.2528390167
/workspace/coverage/cover_reg_top/0.xbar_stress_all.1472605789
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.1798935898
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.2389786135
/workspace/coverage/cover_reg_top/1.chip_csr_aliasing.2088473384
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.2246685530
/workspace/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.3387155714
/workspace/coverage/cover_reg_top/1.chip_csr_rw.2066663200
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.3547697188
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.1974157715
/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.1214767550
/workspace/coverage/cover_reg_top/1.chip_tl_errors.1053305557
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.2586636420
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.576906982
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.2982541234
/workspace/coverage/cover_reg_top/1.xbar_error_random.3647460213
/workspace/coverage/cover_reg_top/1.xbar_random.1086342056
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.3780032667
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.2929063268
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.2430282390
/workspace/coverage/cover_reg_top/1.xbar_same_source.931046444
/workspace/coverage/cover_reg_top/1.xbar_smoke.3425409019
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.2576618907
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.2902729155
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.345336143
/workspace/coverage/cover_reg_top/1.xbar_stress_all.1225654822
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.387515548
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.2845668217
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.3404932859
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.1656600056
/workspace/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.1477968148
/workspace/coverage/cover_reg_top/10.chip_csr_rw.2089393754
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.1036620150
/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.1863061210
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.3607598840
/workspace/coverage/cover_reg_top/10.xbar_error_random.2529932015
/workspace/coverage/cover_reg_top/10.xbar_random.1034284323
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.1528564664
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.1599588865
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.4050560892
/workspace/coverage/cover_reg_top/10.xbar_same_source.2021096674
/workspace/coverage/cover_reg_top/10.xbar_smoke.566562402
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.155537242
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.2259297840
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.4246528454
/workspace/coverage/cover_reg_top/10.xbar_stress_all.364103211
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.2612536673
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.237664509
/workspace/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.2862120319
/workspace/coverage/cover_reg_top/11.chip_tl_errors.3009573196
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.700320542
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.337835076
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.3167392272
/workspace/coverage/cover_reg_top/11.xbar_error_random.81772390
/workspace/coverage/cover_reg_top/11.xbar_random.3915847686
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.2868954675
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.614230882
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.3955376080
/workspace/coverage/cover_reg_top/11.xbar_same_source.1086171885
/workspace/coverage/cover_reg_top/11.xbar_smoke.785746531
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.3276838655
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.2229618048
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.3759302092
/workspace/coverage/cover_reg_top/11.xbar_stress_all.395436468
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.2952107394
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.1548683023
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.208809675
/workspace/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.4264341156
/workspace/coverage/cover_reg_top/12.chip_csr_rw.4093662328
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.695851111
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.3407747586
/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.1548312582
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.2908347394
/workspace/coverage/cover_reg_top/12.xbar_error_random.2689429705
/workspace/coverage/cover_reg_top/12.xbar_random.824302316
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.3481023775
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.3255802402
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.2025027846
/workspace/coverage/cover_reg_top/12.xbar_same_source.3165587788
/workspace/coverage/cover_reg_top/12.xbar_smoke.2485852107
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.3323590072
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.2884328969
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.4152797284
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.4002652412
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.4022390558
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.1775924285
/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.2374353190
/workspace/coverage/cover_reg_top/13.chip_csr_mem_rw_with_rand_reset.878325676
/workspace/coverage/cover_reg_top/13.chip_csr_rw.2872200311
/workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.24590086
/workspace/coverage/cover_reg_top/13.chip_tl_errors.2492863021
/workspace/coverage/cover_reg_top/13.xbar_access_same_device.2008264864
/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.2836132934
/workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.3685703248
/workspace/coverage/cover_reg_top/13.xbar_error_random.645484110
/workspace/coverage/cover_reg_top/13.xbar_random.2957716724
/workspace/coverage/cover_reg_top/13.xbar_random_large_delays.1128745369
/workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.1856352275
/workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.337780661
/workspace/coverage/cover_reg_top/13.xbar_same_source.3139231694
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/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.4283249370
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/workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.53335977
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/workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.325380828
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3242879019
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/workspace/coverage/default/2.chip_sw_uart_smoketest_signed.263950069
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/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.1444031358
/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.2845502458
/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.4134007157
/workspace/coverage/default/3.chip_sw_data_integrity_escalation.4158749364
/workspace/coverage/default/3.chip_sw_lc_ctrl_transition.1576820268
/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.3741109920
/workspace/coverage/default/3.chip_sw_uart_rand_baudrate.3762857446
/workspace/coverage/default/3.chip_sw_uart_tx_rx.1950732315
/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.3852327294
/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.4151037947
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.3887959582
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/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.2074781750
/workspace/coverage/default/3.chip_tap_straps_dev.1317371872
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/workspace/coverage/default/3.chip_tap_straps_testunlock0.1686839752
/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.1941403715
/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.4187959050
/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.2561005783
/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.2909382617
/workspace/coverage/default/36.chip_sw_all_escalation_resets.882428515
/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.1287508698
/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.3631050121
/workspace/coverage/default/4.chip_sw_all_escalation_resets.3420495476
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.3801849970
/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.3568838698
/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.2746336452
/workspace/coverage/default/4.chip_sw_uart_tx_rx.1111268376
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.2500327116
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1833337371
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.695064618
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.856192236
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.1971670840
/workspace/coverage/default/4.chip_tap_straps_dev.2063856068
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/workspace/coverage/default/4.chip_tap_straps_rma.1690515688
/workspace/coverage/default/4.chip_tap_straps_testunlock0.2047990813
/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.2017504024
/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.1911061398
/workspace/coverage/default/41.chip_sw_all_escalation_resets.2587260671
/workspace/coverage/default/42.chip_sw_all_escalation_resets.2658929120
/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.112020731
/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.209612087
/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.666716348
/workspace/coverage/default/45.chip_sw_all_escalation_resets.3697255573
/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.1695626004
/workspace/coverage/default/47.chip_sw_all_escalation_resets.2385027804
/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.65794958
/workspace/coverage/default/48.chip_sw_all_escalation_resets.3237337122
/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.1863578714
/workspace/coverage/default/49.chip_sw_all_escalation_resets.4173062422
/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.2205841302
/workspace/coverage/default/5.chip_sw_all_escalation_resets.2540537871
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.1283464249
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.3232995889
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.3638074538
/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.2951528749
/workspace/coverage/default/51.chip_sw_all_escalation_resets.2331615811
/workspace/coverage/default/52.chip_sw_all_escalation_resets.943126244
/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.2383684836
/workspace/coverage/default/53.chip_sw_all_escalation_resets.707018085
/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.508057308
/workspace/coverage/default/54.chip_sw_all_escalation_resets.932199917
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.3407012107
/workspace/coverage/default/55.chip_sw_all_escalation_resets.3284456670
/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.952527005
/workspace/coverage/default/57.chip_sw_all_escalation_resets.3699301460
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.4099890333
/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.2798326136
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.2343092892
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.1812623677
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.2718519503
/workspace/coverage/default/60.chip_sw_all_escalation_resets.1441410952
/workspace/coverage/default/63.chip_sw_all_escalation_resets.3264216078
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.2800871349
/workspace/coverage/default/64.chip_sw_all_escalation_resets.4226260601
/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.1593681401
/workspace/coverage/default/66.chip_sw_all_escalation_resets.905887909
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.1455645042
/workspace/coverage/default/67.chip_sw_all_escalation_resets.2281541371
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.2182453823
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.2551046564
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.3067509940
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.1930497578
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.2081830164
/workspace/coverage/default/71.chip_sw_all_escalation_resets.3423183961
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.2052508595
/workspace/coverage/default/72.chip_sw_all_escalation_resets.1075504240
/workspace/coverage/default/73.chip_sw_all_escalation_resets.4187923161
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.669255902
/workspace/coverage/default/74.chip_sw_all_escalation_resets.2477744673
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.510142304
/workspace/coverage/default/75.chip_sw_all_escalation_resets.2671924335
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.3704122390
/workspace/coverage/default/76.chip_sw_all_escalation_resets.1595710958
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.3307499950
/workspace/coverage/default/77.chip_sw_all_escalation_resets.1305619639
/workspace/coverage/default/78.chip_sw_all_escalation_resets.756571218
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.4131484111
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.3606662552
/workspace/coverage/default/8.chip_sw_all_escalation_resets.3171742368
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.3884360437
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.3161005120
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.4110639602
/workspace/coverage/default/81.chip_sw_all_escalation_resets.1123324651
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.1146902521
/workspace/coverage/default/82.chip_sw_all_escalation_resets.4166176520
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.2913692241
/workspace/coverage/default/83.chip_sw_all_escalation_resets.4139310227
/workspace/coverage/default/84.chip_sw_all_escalation_resets.4203565777
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.758803092
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.3625799091
/workspace/coverage/default/86.chip_sw_all_escalation_resets.901688124
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.2157289589
/workspace/coverage/default/87.chip_sw_all_escalation_resets.3791855414
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.1697380657
/workspace/coverage/default/88.chip_sw_all_escalation_resets.749444189
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.1601939113
/workspace/coverage/default/89.chip_sw_all_escalation_resets.2743520614
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.2759325887
/workspace/coverage/default/9.chip_sw_all_escalation_resets.2897432172
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.2247481194
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.3934593963
/workspace/coverage/default/91.chip_sw_all_escalation_resets.1769027135
/workspace/coverage/default/92.chip_sw_all_escalation_resets.2283271106
/workspace/coverage/default/93.chip_sw_all_escalation_resets.839731654
/workspace/coverage/default/96.chip_sw_all_escalation_resets.1014288319
/workspace/coverage/default/97.chip_sw_all_escalation_resets.1733231074
/workspace/coverage/default/99.chip_sw_all_escalation_resets.1406187302
/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.1678040822
/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.2416125383
/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.2497588686
/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.1527266314
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.3428476304
/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.1736231198
/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.3633895954
/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.1013248740

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Total test records in report: 2873

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T32	/workspace/coverage/cover_reg_top/97.xbar_error_and_unmapped_addr.3233058318			Jan 10 01:45:48 PM PST 24	Jan 10 01:46:11 PM PST 24	394446571 ps
T33	/workspace/coverage/cover_reg_top/12.xbar_stress_all.444322223			Jan 10 01:36:45 PM PST 24	Jan 10 01:44:36 PM PST 24	12345088871 ps
T34	/workspace/coverage/cover_reg_top/54.xbar_smoke.1150652687			Jan 10 01:42:19 PM PST 24	Jan 10 01:42:29 PM PST 24	175254779 ps
T100	/workspace/coverage/cover_reg_top/25.xbar_access_same_device_slow_rsp.1115202742			Jan 10 01:38:04 PM PST 24	Jan 10 01:59:24 PM PST 24	77107775349 ps
T58	/workspace/coverage/cover_reg_top/57.xbar_smoke.1727043113			Jan 10 01:42:40 PM PST 24	Jan 10 01:42:51 PM PST 24	195613398 ps
T101	/workspace/coverage/cover_reg_top/68.xbar_stress_all.313755197			Jan 10 01:43:23 PM PST 24	Jan 10 01:49:20 PM PST 24	8974518772 ps
T230	/workspace/coverage/cover_reg_top/41.xbar_random_slow_rsp.404485025			Jan 10 01:40:19 PM PST 24	Jan 10 01:48:19 PM PST 24	27471594350 ps
T231	/workspace/coverage/cover_reg_top/35.xbar_access_same_device_slow_rsp.3416886256			Jan 10 01:38:55 PM PST 24	Jan 10 02:17:41 PM PST 24	135080853258 ps
T123	/workspace/coverage/cover_reg_top/9.xbar_stress_all_with_rand_reset.1701276491			Jan 10 01:36:39 PM PST 24	Jan 10 01:39:39 PM PST 24	4433748308 ps
T232	/workspace/coverage/cover_reg_top/99.xbar_access_same_device.362641911			Jan 10 01:46:06 PM PST 24	Jan 10 01:46:45 PM PST 24	353472131 ps
T394	/workspace/coverage/cover_reg_top/60.xbar_smoke_zero_delays.34934124			Jan 10 01:42:56 PM PST 24	Jan 10 01:43:03 PM PST 24	45078478 ps
T393	/workspace/coverage/cover_reg_top/65.xbar_smoke_large_delays.2008537314			Jan 10 01:43:15 PM PST 24	Jan 10 01:44:48 PM PST 24	9002000145 ps
T392	/workspace/coverage/cover_reg_top/69.xbar_random_large_delays.3567533106			Jan 10 01:43:45 PM PST 24	Jan 10 01:45:13 PM PST 24	7596407446 ps
T107	/workspace/coverage/cover_reg_top/19.xbar_stress_all_with_error.1773717922			Jan 10 01:37:48 PM PST 24	Jan 10 01:39:19 PM PST 24	1108880546 ps
T380	/workspace/coverage/cover_reg_top/36.xbar_random_zero_delays.1854210342			Jan 10 01:40:05 PM PST 24	Jan 10 01:40:33 PM PST 24	329290264 ps
T382	/workspace/coverage/cover_reg_top/94.xbar_random_slow_rsp.3812593714			Jan 10 01:46:02 PM PST 24	Jan 10 02:02:00 PM PST 24	49383037303 ps
T29	/workspace/coverage/cover_reg_top/2.chip_csr_mem_rw_with_rand_reset.3555530576			Jan 10 01:36:02 PM PST 24	Jan 10 01:39:46 PM PST 24	5040631314 ps
T374	/workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.3003666056			Jan 10 01:37:16 PM PST 24	Jan 10 01:37:44 PM PST 24	74224627 ps
T383	/workspace/coverage/cover_reg_top/59.xbar_random_large_delays.1400116828			Jan 10 01:42:47 PM PST 24	Jan 10 01:51:25 PM PST 24	47330304458 ps
T328	/workspace/coverage/cover_reg_top/3.xbar_random_zero_delays.2160823150			Jan 10 01:35:52 PM PST 24	Jan 10 01:36:27 PM PST 24	231288408 ps
T375	/workspace/coverage/cover_reg_top/70.xbar_random.1873569627			Jan 10 01:43:49 PM PST 24	Jan 10 01:45:22 PM PST 24	2340859302 ps
T780	/workspace/coverage/cover_reg_top/59.xbar_access_same_device.1887619628			Jan 10 01:42:45 PM PST 24	Jan 10 01:43:10 PM PST 24	695188581 ps
T782	/workspace/coverage/cover_reg_top/83.xbar_access_same_device_slow_rsp.2838877415			Jan 10 01:44:47 PM PST 24	Jan 10 02:03:11 PM PST 24	56291692013 ps
T30	/workspace/coverage/cover_reg_top/7.chip_csr_mem_rw_with_rand_reset.2164231485			Jan 10 01:36:22 PM PST 24	Jan 10 01:42:35 PM PST 24	7258412310 ps
T31	/workspace/coverage/cover_reg_top/19.chip_csr_mem_rw_with_rand_reset.1632309121			Jan 10 01:37:48 PM PST 24	Jan 10 01:41:47 PM PST 24	6504802275 ps
T395	/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.1060084682			Jan 10 01:36:38 PM PST 24	Jan 10 01:43:21 PM PST 24	8595644992 ps
T347	/workspace/coverage/cover_reg_top/84.xbar_same_source.193022898			Jan 10 01:44:45 PM PST 24	Jan 10 01:45:44 PM PST 24	1780936606 ps
T396	/workspace/coverage/cover_reg_top/5.xbar_stress_all_with_error.2090176630			Jan 10 01:36:00 PM PST 24	Jan 10 01:39:24 PM PST 24	2659685306 ps
T351	/workspace/coverage/cover_reg_top/2.xbar_stress_all_with_rand_reset.3501822671			Jan 10 01:35:51 PM PST 24	Jan 10 01:38:33 PM PST 24	885918651 ps
T388	/workspace/coverage/cover_reg_top/50.xbar_random_slow_rsp.633484269			Jan 10 01:41:02 PM PST 24	Jan 10 01:42:49 PM PST 24	6103228788 ps
T399	/workspace/coverage/cover_reg_top/77.xbar_error_and_unmapped_addr.4119085425			Jan 10 01:44:39 PM PST 24	Jan 10 01:45:01 PM PST 24	171739844 ps
T397	/workspace/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.3449654245			Jan 10 01:37:31 PM PST 24	Jan 10 01:57:10 PM PST 24	23478982108 ps
T398	/workspace/coverage/cover_reg_top/23.xbar_stress_all_with_error.2678115365			Jan 10 01:37:47 PM PST 24	Jan 10 01:42:08 PM PST 24	7276585828 ps
T387	/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.2528390167			Jan 10 01:35:53 PM PST 24	Jan 10 01:36:13 PM PST 24	44814192 ps
T59	/workspace/coverage/cover_reg_top/4.chip_csr_rw.552409964			Jan 10 01:36:12 PM PST 24	Jan 10 01:45:33 PM PST 24	5931488770 ps
T376	/workspace/coverage/cover_reg_top/30.xbar_random_large_delays.2640083544			Jan 10 01:38:35 PM PST 24	Jan 10 01:49:24 PM PST 24	63950891305 ps
T829	/workspace/coverage/cover_reg_top/81.xbar_smoke.2760629315			Jan 10 01:44:44 PM PST 24	Jan 10 01:44:52 PM PST 24	37493438 ps
T349	/workspace/coverage/cover_reg_top/70.xbar_random_slow_rsp.441538393			Jan 10 01:43:43 PM PST 24	Jan 10 01:52:25 PM PST 24	30144294765 ps
T337	/workspace/coverage/cover_reg_top/48.xbar_stress_all.3617104437			Jan 10 01:41:01 PM PST 24	Jan 10 01:44:30 PM PST 24	2887054665 ps
T348	/workspace/coverage/cover_reg_top/92.xbar_stress_all.1319594290			Jan 10 01:45:53 PM PST 24	Jan 10 01:47:58 PM PST 24	1331032983 ps
T390	/workspace/coverage/cover_reg_top/87.xbar_unmapped_addr.311539458			Jan 10 01:45:09 PM PST 24	Jan 10 01:45:47 PM PST 24	324475380 ps
T378	/workspace/coverage/cover_reg_top/65.xbar_random_slow_rsp.907932418			Jan 10 01:43:07 PM PST 24	Jan 10 01:52:06 PM PST 24	30502256746 ps
T771	/workspace/coverage/cover_reg_top/15.xbar_access_same_device.2940512093			Jan 10 01:38:11 PM PST 24	Jan 10 01:40:08 PM PST 24	2607857987 ps
T346	/workspace/coverage/cover_reg_top/62.xbar_access_same_device.86639506			Jan 10 01:42:50 PM PST 24	Jan 10 01:44:53 PM PST 24	3160554495 ps
T830	/workspace/coverage/cover_reg_top/20.xbar_smoke.3714099431			Jan 10 01:37:34 PM PST 24	Jan 10 01:37:52 PM PST 24	197333113 ps
T385	/workspace/coverage/cover_reg_top/85.xbar_random_slow_rsp.1199134321			Jan 10 01:44:58 PM PST 24	Jan 10 02:01:00 PM PST 24	52539192274 ps
T831	/workspace/coverage/cover_reg_top/54.xbar_error_random.3439574825			Jan 10 01:42:41 PM PST 24	Jan 10 01:43:14 PM PST 24	970292452 ps
T56	/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.3383631814			Jan 10 01:36:44 PM PST 24	Jan 10 02:43:12 PM PST 24	30370297412 ps
T384	/workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.3165562240			Jan 10 01:37:47 PM PST 24	Jan 10 01:52:30 PM PST 24	56998369516 ps
T604	/workspace/coverage/cover_reg_top/41.xbar_stress_all_with_error.3250869250			Jan 10 01:40:26 PM PST 24	Jan 10 01:43:37 PM PST 24	5082859763 ps
T675	/workspace/coverage/cover_reg_top/24.xbar_stress_all_with_error.2100903210			Jan 10 01:38:14 PM PST 24	Jan 10 01:45:01 PM PST 24	11956486702 ps
T391	/workspace/coverage/cover_reg_top/94.xbar_random.2854886206			Jan 10 01:46:00 PM PST 24	Jan 10 01:46:24 PM PST 24	228895607 ps
T389	/workspace/coverage/cover_reg_top/86.xbar_unmapped_addr.769854303			Jan 10 01:45:09 PM PST 24	Jan 10 01:45:47 PM PST 24	116758020 ps
T832	/workspace/coverage/cover_reg_top/76.xbar_smoke.2352893538			Jan 10 01:43:59 PM PST 24	Jan 10 01:44:06 PM PST 24	45661364 ps
T386	/workspace/coverage/cover_reg_top/93.xbar_random_slow_rsp.3144113510			Jan 10 01:45:59 PM PST 24	Jan 10 02:01:08 PM PST 24	54491114425 ps
T833	/workspace/coverage/cover_reg_top/27.xbar_smoke_large_delays.2612218165			Jan 10 01:38:10 PM PST 24	Jan 10 01:39:36 PM PST 24	8202680438 ps
T338	/workspace/coverage/cover_reg_top/35.xbar_stress_all.2241081106			Jan 10 01:40:05 PM PST 24	Jan 10 01:41:16 PM PST 24	1682399612 ps
T57	/workspace/coverage/cover_reg_top/19.chip_same_csr_outstanding.3041088092			Jan 10 01:37:51 PM PST 24	Jan 10 02:37:13 PM PST 24	31316839837 ps
T834	/workspace/coverage/cover_reg_top/85.xbar_smoke_large_delays.3453980315			Jan 10 01:44:59 PM PST 24	Jan 10 01:46:54 PM PST 24	8904857469 ps
T377	/workspace/coverage/cover_reg_top/14.xbar_stress_all.1043545026			Jan 10 01:37:55 PM PST 24	Jan 10 01:41:34 PM PST 24	2828511606 ps
T412	/workspace/coverage/cover_reg_top/81.xbar_smoke_slow_rsp.197351834			Jan 10 01:45:00 PM PST 24	Jan 10 01:46:39 PM PST 24	4657261049 ps
T381	/workspace/coverage/cover_reg_top/94.xbar_stress_all_with_rand_reset.2508815937			Jan 10 01:45:53 PM PST 24	Jan 10 01:55:28 PM PST 24	9241125473 ps
T379	/workspace/coverage/cover_reg_top/98.xbar_stress_all.2589660174			Jan 10 01:46:05 PM PST 24	Jan 10 01:48:29 PM PST 24	1441184080 ps
T1	/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.1714340717			Jan 10 01:47:08 PM PST 24	Jan 10 01:51:37 PM PST 24	5338579789 ps
T2	/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.2497588686			Jan 10 01:47:14 PM PST 24	Jan 10 01:50:06 PM PST 24	4534844480 ps
T3	/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.2349278514			Jan 10 01:46:41 PM PST 24	Jan 10 01:52:21 PM PST 24	4928339499 ps
T63	/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.1013248740			Jan 10 01:47:23 PM PST 24	Jan 10 01:51:42 PM PST 24	5367555434 ps
T64	/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.1736231198			Jan 10 01:47:05 PM PST 24	Jan 10 01:50:39 PM PST 24	4502007112 ps
T65	/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.1527266314			Jan 10 01:47:10 PM PST 24	Jan 10 01:51:05 PM PST 24	4247963574 ps
T66	/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.3633895954			Jan 10 01:47:16 PM PST 24	Jan 10 01:50:06 PM PST 24	3411976492 ps
T67	/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.2416125383			Jan 10 01:47:06 PM PST 24	Jan 10 01:51:32 PM PST 24	5153780713 ps
T68	/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.3428476304			Jan 10 01:47:01 PM PST 24	Jan 10 01:50:43 PM PST 24	4392436284 ps
T69	/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.1678040822			Jan 10 01:46:46 PM PST 24	Jan 10 01:50:34 PM PST 24	5093790828 ps
T19	/workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.472587330			Jan 10 01:54:00 PM PST 24	Jan 10 02:08:10 PM PST 24	10226092786 ps
T20	/workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.560722315			Jan 10 01:58:00 PM PST 24	Jan 10 05:13:30 PM PST 24	72284061160 ps
T21	/workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.3562007380			Jan 10 01:57:38 PM PST 24	Jan 10 02:03:45 PM PST 24	3499841708 ps
T22	/workspace/coverage/default/1.chip_sw_uart_rand_baudrate.521825875			Jan 10 01:59:01 PM PST 24	Jan 10 03:01:56 PM PST 24	22905614256 ps
T136	/workspace/coverage/default/10.chip_sw_uart_rand_baudrate.4024159539			Jan 10 02:02:38 PM PST 24	Jan 10 02:59:26 PM PST 24	22942001994 ps
T104	/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.3260394301			Jan 10 02:00:23 PM PST 24	Jan 10 02:09:23 PM PST 24	6260865064 ps
T90	/workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.2744235679			Jan 10 01:56:57 PM PST 24	Jan 10 02:15:24 PM PST 24	7850503166 ps
T137	/workspace/coverage/default/2.chip_sw_aes_entropy.2329423211			Jan 10 02:00:09 PM PST 24	Jan 10 02:03:54 PM PST 24	2932736292 ps
T38	/workspace/coverage/default/87.chip_sw_all_escalation_resets.3791855414			Jan 10 02:08:16 PM PST 24	Jan 10 02:17:31 PM PST 24	4484573948 ps
T106	/workspace/coverage/default/1.chip_sw_edn_entropy_reqs.236873925			Jan 10 01:56:53 PM PST 24	Jan 10 02:09:42 PM PST 24	4778229812 ps
T229	/workspace/coverage/default/1.chip_sw_rv_timer_irq.4275068747			Jan 10 01:55:16 PM PST 24	Jan 10 01:58:55 PM PST 24	3022809560 ps
T309	/workspace/coverage/default/1.chip_sw_spi_host_tx_rx.1026132211			Jan 10 01:57:48 PM PST 24	Jan 10 02:02:44 PM PST 24	3453358956 ps
T172	/workspace/coverage/default/0.chip_sw_uart_rand_baudrate.1083836468			Jan 10 01:56:28 PM PST 24	Jan 10 03:05:01 PM PST 24	22669906816 ps
T7	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.658420738			Jan 10 01:57:06 PM PST 24	Jan 10 02:01:51 PM PST 24	3867777112 ps
T81	/workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.22974475			Jan 10 01:55:13 PM PST 24	Jan 10 01:59:14 PM PST 24	3245123550 ps
T39	/workspace/coverage/default/86.chip_sw_all_escalation_resets.901688124			Jan 10 02:06:48 PM PST 24	Jan 10 02:15:53 PM PST 24	6106199700 ps
T82	/workspace/coverage/default/0.rom_e2e_asm_init_prod_end.370187642			Jan 10 01:59:24 PM PST 24	Jan 10 02:25:18 PM PST 24	8525630910 ps
T40	/workspace/coverage/default/91.chip_sw_all_escalation_resets.1769027135			Jan 10 02:09:13 PM PST 24	Jan 10 02:19:04 PM PST 24	5031401014 ps
T83	/workspace/coverage/default/58.chip_sw_all_escalation_resets.3275182748			Jan 10 02:06:27 PM PST 24	Jan 10 02:16:03 PM PST 24	5073618188 ps
T84	/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.962024143			Jan 10 02:06:02 PM PST 24	Jan 10 02:11:53 PM PST 24	4216469552 ps
T622	/workspace/coverage/default/24.chip_sw_all_escalation_resets.3208882009			Jan 10 02:02:38 PM PST 24	Jan 10 02:11:22 PM PST 24	4501668424 ps
T134	/workspace/coverage/default/2.chip_sw_data_integrity_escalation.3015740146			Jan 10 02:00:30 PM PST 24	Jan 10 02:09:33 PM PST 24	5959101160 ps
T11	/workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.2424546707			Jan 10 01:56:10 PM PST 24	Jan 10 02:02:51 PM PST 24	3753732640 ps
T181	/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.3230805629			Jan 10 02:06:00 PM PST 24	Jan 10 02:10:45 PM PST 24	3496972630 ps
T36	/workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.33556498			Jan 10 02:04:10 PM PST 24	Jan 10 02:16:00 PM PST 24	7027624706 ps
T247	/workspace/coverage/default/0.chip_sw_uart_smoketest_signed.1482059171			Jan 10 01:59:03 PM PST 24	Jan 10 02:29:59 PM PST 24	8868429608 ps
T233	/workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.373913871			Jan 10 01:58:06 PM PST 24	Jan 10 02:02:30 PM PST 24	2888876405 ps
T154	/workspace/coverage/default/2.chip_sw_flash_init.1273368448			Jan 10 02:03:26 PM PST 24	Jan 10 02:29:57 PM PST 24	25303300100 ps
T239	/workspace/coverage/default/2.chip_sw_aes_idle.1677946071			Jan 10 01:59:56 PM PST 24	Jan 10 02:03:21 PM PST 24	2102575962 ps
T173	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.695064618			Jan 10 02:00:43 PM PST 24	Jan 10 02:16:45 PM PST 24	5074756950 ps
T240	/workspace/coverage/default/1.rom_e2e_asm_init_dev.858186680			Jan 10 02:05:19 PM PST 24	Jan 10 02:33:02 PM PST 24	9493344855 ps
T241	/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.3606662552			Jan 10 02:01:37 PM PST 24	Jan 10 02:07:39 PM PST 24	3913049246 ps
T242	/workspace/coverage/default/1.chip_sw_aes_idle.1899605308			Jan 10 01:56:22 PM PST 24	Jan 10 01:59:44 PM PST 24	2454231840 ps
T102	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.223956681			Jan 10 01:54:18 PM PST 24	Jan 10 02:28:50 PM PST 24	18941352997 ps
T96	/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.2965646633			Jan 10 01:59:34 PM PST 24	Jan 10 02:03:40 PM PST 24	2837555477 ps
T243	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.3097267029			Jan 10 01:58:11 PM PST 24	Jan 10 02:04:51 PM PST 24	6035805897 ps
T135	/workspace/coverage/default/40.chip_sw_all_escalation_resets.981994609			Jan 10 02:05:40 PM PST 24	Jan 10 02:12:29 PM PST 24	5176714424 ps
T8	/workspace/coverage/default/0.chip_sw_sleep_pin_retention.1348139901			Jan 10 01:55:37 PM PST 24	Jan 10 02:00:45 PM PST 24	4489035120 ps
T85	/workspace/coverage/default/70.chip_sw_all_escalation_resets.724755247			Jan 10 02:05:54 PM PST 24	Jan 10 02:14:32 PM PST 24	5671350900 ps
T86	/workspace/coverage/default/0.chip_sw_edn_boot_mode.1957740213			Jan 10 01:55:20 PM PST 24	Jan 10 02:05:57 PM PST 24	2707406966 ps
T629	/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.3161005120			Jan 10 02:06:35 PM PST 24	Jan 10 02:12:06 PM PST 24	3487633598 ps
T666	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.1310449132			Jan 10 01:55:32 PM PST 24	Jan 10 02:07:10 PM PST 24	4519659900 ps
T207	/workspace/coverage/default/1.chip_sw_pattgen_ios.3035442488			Jan 10 01:55:39 PM PST 24	Jan 10 02:00:26 PM PST 24	2757303812 ps
T129	/workspace/coverage/default/2.chip_plic_all_irqs_10.2963413049			Jan 10 01:59:00 PM PST 24	Jan 10 02:07:07 PM PST 24	4374325164 ps
T835	/workspace/coverage/default/1.chip_sw_kmac_idle.1313319258			Jan 10 02:02:04 PM PST 24	Jan 10 02:06:48 PM PST 24	2717910526 ps
T103	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.1760890998			Jan 10 01:57:42 PM PST 24	Jan 10 02:48:49 PM PST 24	42665463804 ps
T125	/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.3595006295			Jan 10 02:02:24 PM PST 24	Jan 10 02:13:12 PM PST 24	4534528595 ps
T836	/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.299983310			Jan 10 01:59:37 PM PST 24	Jan 10 02:09:50 PM PST 24	7463367880 ps
T169	/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.745119737			Jan 10 02:02:24 PM PST 24	Jan 10 02:07:30 PM PST 24	3278761898 ps
T671	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3242879019			Jan 10 02:04:36 PM PST 24	Jan 10 02:14:51 PM PST 24	6150287856 ps
T37	/workspace/coverage/default/14.chip_sw_lc_ctrl_transition.1525932021			Jan 10 02:01:06 PM PST 24	Jan 10 02:14:08 PM PST 24	12106200078 ps
T70	/workspace/coverage/default/69.chip_sw_all_escalation_resets.103873213			Jan 10 02:06:48 PM PST 24	Jan 10 02:16:24 PM PST 24	5248628320 ps
T9	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.2377362077			Jan 10 02:00:18 PM PST 24	Jan 10 02:05:26 PM PST 24	2818411980 ps
T72	/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.1863578714			Jan 10 02:06:22 PM PST 24	Jan 10 02:11:08 PM PST 24	3429455510 ps
T73	/workspace/coverage/default/2.rom_e2e_shutdown_exception_c.3633859101			Jan 10 02:04:37 PM PST 24	Jan 10 02:30:57 PM PST 24	8534465812 ps
T74	/workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.3453174258			Jan 10 01:55:05 PM PST 24	Jan 10 02:12:33 PM PST 24	4911812056 ps
T75	/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.1146902521			Jan 10 02:06:56 PM PST 24	Jan 10 02:13:07 PM PST 24	4279918320 ps
T76	/workspace/coverage/default/15.chip_sw_all_escalation_resets.569959942			Jan 10 02:06:44 PM PST 24	Jan 10 02:16:34 PM PST 24	5329962904 ps
T77	/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.1236353597			Jan 10 02:03:11 PM PST 24	Jan 10 02:05:15 PM PST 24	2353558141 ps
T78	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.223380087			Jan 10 02:00:04 PM PST 24	Jan 10 02:25:15 PM PST 24	8392421651 ps
T657	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.1219647156			Jan 10 02:03:36 PM PST 24	Jan 10 02:17:50 PM PST 24	9629150552 ps
T210	/workspace/coverage/default/61.chip_sw_all_escalation_resets.1877262397			Jan 10 02:06:03 PM PST 24	Jan 10 02:13:49 PM PST 24	5073317230 ps
T163	/workspace/coverage/default/17.chip_sw_uart_rand_baudrate.3289694999			Jan 10 02:07:23 PM PST 24	Jan 10 02:50:11 PM PST 24	14107841144 ps
T118	/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.3884360437			Jan 10 02:01:33 PM PST 24	Jan 10 02:06:54 PM PST 24	4642791777 ps
T119	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.3798133053			Jan 10 01:56:30 PM PST 24	Jan 10 02:05:46 PM PST 24	6325414948 ps
T748	/workspace/coverage/default/62.chip_sw_all_escalation_resets.2831019015			Jan 10 02:05:29 PM PST 24	Jan 10 02:14:00 PM PST 24	4871518066 ps
T130	/workspace/coverage/default/1.chip_sw_spi_device_tx_rx.1133947614			Jan 10 01:58:18 PM PST 24	Jan 10 02:04:31 PM PST 24	2453820768 ps
T221	/workspace/coverage/default/20.chip_sw_all_escalation_resets.2759372961			Jan 10 02:02:50 PM PST 24	Jan 10 02:12:45 PM PST 24	5593174840 ps
T837	/workspace/coverage/default/2.chip_sw_kmac_app_rom.1943115480			Jan 10 02:01:22 PM PST 24	Jan 10 02:05:50 PM PST 24	2342358530 ps
T97	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1176272106			Jan 10 01:53:49 PM PST 24	Jan 10 02:02:17 PM PST 24	4104332438 ps
T616	/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.85215465			Jan 10 02:00:54 PM PST 24	Jan 10 02:07:02 PM PST 24	3853756894 ps
T198	/workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.4066215600			Jan 10 01:58:41 PM PST 24	Jan 10 02:09:05 PM PST 24	3377332878 ps
T44	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.2728463976			Jan 10 01:56:39 PM PST 24	Jan 10 02:03:56 PM PST 24	4678123064 ps
T838	/workspace/coverage/default/0.chip_sw_aes_idle.1479584438			Jan 10 01:54:57 PM PST 24	Jan 10 01:58:25 PM PST 24	2998341970 ps
T45	/workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2880295475			Jan 10 01:59:33 PM PST 24	Jan 10 02:06:01 PM PST 24	3787233590 ps
T170	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.345614157			Jan 10 01:58:37 PM PST 24	Jan 10 02:45:52 PM PST 24	16988849882 ps
T150	/workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.2145971099			Jan 10 01:57:28 PM PST 24	Jan 10 02:19:03 PM PST 24	6773688581 ps
T87	/workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.2193033683			Jan 10 01:58:45 PM PST 24	Jan 10 02:11:19 PM PST 24	11247332135 ps
T839	/workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg.2204789107			Jan 10 01:53:59 PM PST 24	Jan 10 01:57:40 PM PST 24	2371279180 ps
T840	/workspace/coverage/default/0.chip_sw_ast_clk_outputs.1883046362			Jan 10 01:56:04 PM PST 24	Jan 10 02:12:32 PM PST 24	7523116160 ps
T841	/workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.2253804101			Jan 10 01:58:32 PM PST 24	Jan 10 02:07:45 PM PST 24	4873885560 ps
T842	/workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.359754193			Jan 10 02:04:48 PM PST 24	Jan 10 02:16:03 PM PST 24	8834936950 ps
T843	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2444370109			Jan 10 02:04:21 PM PST 24	Jan 10 02:08:46 PM PST 24	3339843926 ps
T758	/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.302660264			Jan 10 02:02:07 PM PST 24	Jan 10 02:07:40 PM PST 24	3325967378 ps
T248	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.4283249370			Jan 10 02:01:48 PM PST 24	Jan 10 02:11:50 PM PST 24	5185547615 ps
T626	/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.2547776347			Jan 10 02:02:00 PM PST 24	Jan 10 02:08:54 PM PST 24	3870951856 ps
T844	/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.1276395822			Jan 10 01:56:36 PM PST 24	Jan 10 02:08:04 PM PST 24	6672828588 ps
T355	/workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.1459860532			Jan 10 01:59:47 PM PST 24	Jan 10 02:07:59 PM PST 24	4050294508 ps
T4	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1824243094			Jan 10 01:55:05 PM PST 24	Jan 10 01:59:43 PM PST 24	3244659608 ps
T133	/workspace/coverage/default/0.chip_sw_spi_device_tpm.526650949			Jan 10 01:54:16 PM PST 24	Jan 10 01:59:59 PM PST 24	2844055493 ps
T658	/workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.2813291768			Jan 10 02:04:52 PM PST 24	Jan 10 02:19:33 PM PST 24	7800138310 ps
T684	/workspace/coverage/default/50.chip_sw_all_escalation_resets.2351909884			Jan 10 02:05:00 PM PST 24	Jan 10 02:13:13 PM PST 24	4470452040 ps
T108	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.633612642			Jan 10 01:54:02 PM PST 24	Jan 10 02:01:05 PM PST 24	8588080300 ps
T120	/workspace/coverage/default/1.chip_sw_gpio.3292735295			Jan 10 02:03:03 PM PST 24	Jan 10 02:10:11 PM PST 24	3347758920 ps
T678	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.165438680			Jan 10 01:59:30 PM PST 24	Jan 10 02:04:44 PM PST 24	3498212352 ps
T46	/workspace/coverage/default/0.rom_raw_unlock.1859867802			Jan 10 01:56:05 PM PST 24	Jan 10 02:21:24 PM PST 24	16159610372 ps
T845	/workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.2494527406			Jan 10 02:03:46 PM PST 24	Jan 10 02:12:42 PM PST 24	4689814122 ps
T192	/workspace/coverage/default/2.chip_sw_otbn_randomness.2368633908			Jan 10 02:00:01 PM PST 24	Jan 10 02:08:48 PM PST 24	5831205672 ps
T765	/workspace/coverage/default/23.chip_sw_all_escalation_resets.3202743103			Jan 10 02:09:29 PM PST 24	Jan 10 02:19:12 PM PST 24	4476581850 ps
T667	/workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.2584913211			Jan 10 01:55:36 PM PST 24	Jan 10 02:07:42 PM PST 24	4524697448 ps
T124	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.1029650009			Jan 10 01:54:01 PM PST 24	Jan 10 02:18:53 PM PST 24	7795986656 ps
T846	/workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.4207206275			Jan 10 01:57:54 PM PST 24	Jan 10 02:04:26 PM PST 24	4611973172 ps
T254	/workspace/coverage/default/2.chip_sw_alert_handler_escalation.68658791			Jan 10 02:03:01 PM PST 24	Jan 10 02:09:10 PM PST 24	4465777800 ps
T847	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac.2258756245			Jan 10 02:02:12 PM PST 24	Jan 10 02:06:57 PM PST 24	2829876040 ps
T848	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1777152703			Jan 10 01:54:15 PM PST 24	Jan 10 02:05:51 PM PST 24	4768669216 ps
T717	/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.2007988778			Jan 10 02:10:17 PM PST 24	Jan 10 02:17:12 PM PST 24	4305841266 ps
T208	/workspace/coverage/default/2.chip_sw_pattgen_ios.2645585805			Jan 10 01:57:00 PM PST 24	Jan 10 02:00:59 PM PST 24	2666286880 ps
T121	/workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.3209214035			Jan 10 01:53:40 PM PST 24	Jan 10 01:55:57 PM PST 24	3155807561 ps
T849	/workspace/coverage/default/0.chip_sw_inject_scramble_seed.2256290305			Jan 10 01:53:57 PM PST 24	Jan 10 04:47:07 PM PST 24	66744270918 ps
T164	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.469652124			Jan 10 01:58:55 PM PST 24	Jan 10 02:13:08 PM PST 24	5692861982 ps
T219	/workspace/coverage/default/97.chip_sw_all_escalation_resets.1733231074			Jan 10 02:06:54 PM PST 24	Jan 10 02:16:38 PM PST 24	6424815290 ps
T850	/workspace/coverage/default/1.chip_sw_csrng_kat_test.797334494			Jan 10 01:55:14 PM PST 24	Jan 10 01:58:50 PM PST 24	2301622224 ps
T851	/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.2725812330			Jan 10 02:02:00 PM PST 24	Jan 10 02:16:27 PM PST 24	5474695729 ps
T10	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.3994685001			Jan 10 01:56:24 PM PST 24	Jan 10 02:22:46 PM PST 24	24238010924 ps
T105	/workspace/coverage/default/2.chip_sw_edn_kat.3872705852			Jan 10 01:59:12 PM PST 24	Jan 10 02:09:41 PM PST 24	3515568438 ps
T214	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.237371450			Jan 10 02:00:07 PM PST 24	Jan 10 02:05:14 PM PST 24	2875309800 ps
T211	/workspace/coverage/default/0.chip_sw_data_integrity_escalation.4225115063			Jan 10 01:56:33 PM PST 24	Jan 10 02:07:08 PM PST 24	6214795272 ps
T88	/workspace/coverage/default/2.chip_sw_power_sleep_load.2552361466			Jan 10 02:01:38 PM PST 24	Jan 10 02:09:32 PM PST 24	4662770608 ps
T94	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.1854679799			Jan 10 01:55:15 PM PST 24	Jan 10 02:48:51 PM PST 24	18858770308 ps
T199	/workspace/coverage/default/0.chip_sw_aon_timer_irq.4271806440			Jan 10 01:53:24 PM PST 24	Jan 10 01:59:19 PM PST 24	3463259416 ps
T356	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.2636016346			Jan 10 01:54:48 PM PST 24	Jan 10 02:13:57 PM PST 24	9283181160 ps
T193	/workspace/coverage/default/0.chip_sw_rv_plic_smoketest.3560357705			Jan 10 01:56:34 PM PST 24	Jan 10 01:59:48 PM PST 24	2710913750 ps
T852	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1498366528			Jan 10 01:54:37 PM PST 24	Jan 10 02:04:40 PM PST 24	4743597720 ps
T225	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.3684740050			Jan 10 01:55:47 PM PST 24	Jan 10 02:00:26 PM PST 24	2758093950 ps
T246	/workspace/coverage/default/57.chip_sw_all_escalation_resets.3699301460			Jan 10 02:05:31 PM PST 24	Jan 10 02:12:59 PM PST 24	5431811272 ps
T122	/workspace/coverage/default/3.chip_sw_lc_ctrl_transition.1576820268			Jan 10 02:00:58 PM PST 24	Jan 10 02:10:30 PM PST 24	8611179023 ps
T853	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3577995627			Jan 10 02:03:22 PM PST 24	Jan 10 02:13:17 PM PST 24	5533869426 ps
T161	/workspace/coverage/default/4.chip_sw_data_integrity_escalation.2584177			Jan 10 02:05:58 PM PST 24	Jan 10 02:20:51 PM PST 24	5450678602 ps
T47	/workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.1382095195			Jan 10 02:02:12 PM PST 24	Jan 10 04:45:18 PM PST 24	60711327561 ps
T109	/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.4157280623			Jan 10 01:56:43 PM PST 24	Jan 10 02:12:13 PM PST 24	9383213864 ps
T276	/workspace/coverage/default/12.chip_sw_all_escalation_resets.3180497948			Jan 10 02:02:43 PM PST 24	Jan 10 02:12:50 PM PST 24	4975901688 ps
T277	/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.1284889271			Jan 10 01:53:53 PM PST 24	Jan 10 01:58:15 PM PST 24	2844060544 ps
T278	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.2843109345			Jan 10 02:00:23 PM PST 24	Jan 10 02:25:05 PM PST 24	8687765178 ps
T279	/workspace/coverage/default/1.chip_sw_example_manufacturer.2342047020			Jan 10 02:00:21 PM PST 24	Jan 10 02:03:43 PM PST 24	2251009122 ps
T259	/workspace/coverage/default/0.chip_sw_rv_timer_irq.2985412830			Jan 10 01:55:01 PM PST 24	Jan 10 02:00:47 PM PST 24	2889501840 ps
T16	/workspace/coverage/default/1.chip_sw_sleep_pin_retention.1449460917			Jan 10 02:00:13 PM PST 24	Jan 10 02:05:46 PM PST 24	4101042900 ps
T110	/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.3741109920			Jan 10 02:00:28 PM PST 24	Jan 10 02:15:37 PM PST 24	6644120200 ps
T201	/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.2684381940			Jan 10 01:56:52 PM PST 24	Jan 10 02:01:04 PM PST 24	3360780514 ps
T331	/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.2317923867			Jan 10 02:05:03 PM PST 24	Jan 10 02:13:39 PM PST 24	3803947500 ps
T854	/workspace/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.3514300032			Jan 10 01:59:33 PM PST 24	Jan 10 02:05:37 PM PST 24	6082599480 ps
T126	/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.3336779603			Jan 10 01:53:57 PM PST 24	Jan 10 02:05:26 PM PST 24	4881010826 ps
T189	/workspace/coverage/default/12.chip_sw_uart_rand_baudrate.3722534855			Jan 10 02:02:17 PM PST 24	Jan 10 03:00:42 PM PST 24	23751901750 ps
T98	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3380376328			Jan 10 01:58:50 PM PST 24	Jan 10 02:07:52 PM PST 24	4164475364 ps
T855	/workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.939271122			Jan 10 02:04:10 PM PST 24	Jan 10 02:09:03 PM PST 24	3068649495 ps
T856	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac.2581794770			Jan 10 01:54:59 PM PST 24	Jan 10 02:00:08 PM PST 24	3709189680 ps
T669	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.297618714			Jan 10 01:59:25 PM PST 24	Jan 10 02:37:45 PM PST 24	12190990251 ps
T857	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.2773039671			Jan 10 02:00:31 PM PST 24	Jan 10 02:11:55 PM PST 24	7898397470 ps
T858	/workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.584041641			Jan 10 01:55:20 PM PST 24	Jan 10 01:58:33 PM PST 24	2938831048 ps
T256	/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.2050587787			Jan 10 02:06:33 PM PST 24	Jan 10 02:12:38 PM PST 24	3112198580 ps
T166	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops.3852519995			Jan 10 01:57:04 PM PST 24	Jan 10 02:10:18 PM PST 24	5589312404 ps
T127	/workspace/coverage/default/0.chip_sw_spi_device_pass_through.2420659670			Jan 10 01:54:15 PM PST 24	Jan 10 02:04:43 PM PST 24	7151336314 ps
T138	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.131502761			Jan 10 01:58:55 PM PST 24	Jan 10 02:27:52 PM PST 24	8870854616 ps
T286	/workspace/coverage/default/0.chip_sw_example_rom.728424504			Jan 10 01:54:02 PM PST 24	Jan 10 01:56:18 PM PST 24	2010767068 ps
T99	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.73889416			Jan 10 01:55:23 PM PST 24	Jan 10 02:05:46 PM PST 24	4069504772 ps
T144	/workspace/coverage/default/90.chip_sw_all_escalation_resets.3223094929			Jan 10 02:07:29 PM PST 24	Jan 10 02:16:02 PM PST 24	4036202260 ps
T287	/workspace/coverage/default/78.chip_sw_all_escalation_resets.756571218			Jan 10 02:06:21 PM PST 24	Jan 10 02:15:27 PM PST 24	6103747052 ps
T288	/workspace/coverage/default/2.chip_tap_straps_dev.2520174085			Jan 10 01:58:57 PM PST 24	Jan 10 02:01:25 PM PST 24	2520235603 ps
T289	/workspace/coverage/default/0.chip_jtag_mem_access.865149981			Jan 10 01:47:24 PM PST 24	Jan 10 02:09:35 PM PST 24	13428694572 ps
T360	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.1383461993			Jan 10 01:53:18 PM PST 24	Jan 10 02:08:39 PM PST 24	8085587720 ps
T234	/workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.63194839			Jan 10 01:56:22 PM PST 24	Jan 10 02:00:29 PM PST 24	2561396256 ps
T155	/workspace/coverage/default/0.chip_sw_flash_init.1724299591			Jan 10 01:53:45 PM PST 24	Jan 10 02:26:26 PM PST 24	16413454512 ps
T859	/workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.3907877884			Jan 10 01:55:34 PM PST 24	Jan 10 02:13:19 PM PST 24	8671077512 ps
T860	/workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.15068373			Jan 10 02:02:25 PM PST 24	Jan 10 02:06:25 PM PST 24	2195460620 ps
T861	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3051335295			Jan 10 01:59:02 PM PST 24	Jan 10 02:09:46 PM PST 24	5313920134 ps
T701	/workspace/coverage/default/92.chip_sw_all_escalation_resets.2283271106			Jan 10 02:06:10 PM PST 24	Jan 10 02:15:52 PM PST 24	5455929888 ps
T235	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.1918312888			Jan 10 01:56:35 PM PST 24	Jan 10 02:01:58 PM PST 24	3350148796 ps
T322	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.94396813			Jan 10 01:58:02 PM PST 24	Jan 10 02:13:15 PM PST 24	6203699956 ps
T323	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2923806422			Jan 10 01:59:52 PM PST 24	Jan 10 02:10:59 PM PST 24	3964062472 ps
T324	/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.1983254087			Jan 10 02:03:06 PM PST 24	Jan 10 02:09:43 PM PST 24	3021175278 ps
T148	/workspace/coverage/default/63.chip_sw_all_escalation_resets.3264216078			Jan 10 02:06:16 PM PST 24	Jan 10 02:16:11 PM PST 24	4774241258 ps
T310	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.2347901094			Jan 10 01:59:17 PM PST 24	Jan 10 02:40:53 PM PST 24	12145534344 ps
T325	/workspace/coverage/default/1.chip_sw_uart_smoketest.3428037793			Jan 10 01:59:06 PM PST 24	Jan 10 02:03:38 PM PST 24	2711497976 ps
T244	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.3989169589			Jan 10 01:53:30 PM PST 24	Jan 10 02:05:58 PM PST 24	5267119816 ps
T326	/workspace/coverage/default/2.chip_sw_hmac_enc_idle.2397112609			Jan 10 02:00:23 PM PST 24	Jan 10 02:03:34 PM PST 24	2980097800 ps
T327	/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1540579646			Jan 10 01:56:28 PM PST 24	Jan 10 02:15:48 PM PST 24	13404165038 ps
T862	/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3676578635			Jan 10 01:57:11 PM PST 24	Jan 10 02:14:40 PM PST 24	8052819289 ps
T863	/workspace/coverage/default/0.chip_sw_lc_ctrl_transition.3490857141			Jan 10 01:53:18 PM PST 24	Jan 10 02:10:48 PM PST 24	9279179441 ps