Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.spi_device_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	138031	1			T32	23		T33	284		T34	2
values[2]	10380	1			T33	1		T100	1		T101	8
values[3]	4312	1			T100	1		T101	4		T231	1
values[4]	2520	1			T100	1		T101	4		T231	1
values[5]	1499	1			T100	1		T101	3		T231	1
values[6]	1120	1			T100	1		T101	4		T231	1
values[7]	778	1			T100	1		T101	6		T231	1
values[8]	598	1			T100	1		T101	3		T231	1
values[9]	454	1			T100	1		T101	4		T231	1
values[10]	413	1			T100	1		T101	6		T231	1
values[11]	398	1			T100	1		T101	10		T231	1
values[12]	385	1			T100	1		T101	3		T231	1
values[13]	333	1			T100	1		T101	5		T231	1
values[14]	301	1			T100	1		T101	9		T231	1
values[15]	273	1			T100	1		T101	3		T231	1
values[16]	338	1			T100	1		T101	5		T231	1
values[17]	274	1			T100	1		T101	3		T231	1
values[18]	260	1			T100	1		T101	3		T231	1
values[19]	250	1			T100	1		T101	4		T231	1
values[20]	336	1			T100	1		T101	5		T231	1
values[21]	295	1			T100	1		T101	4		T231	1
values[22]	363	1			T100	1		T101	3		T231	1
values[23]	304	1			T100	1		T101	10		T231	1
values[24]	276	1			T100	1		T101	21		T231	1
values[25]	237	1			T100	1		T101	4		T231	1
values[26]	271	1			T100	1		T101	4		T231	1
values[27]	269	1			T100	1		T101	8		T231	1
values[28]	261	1			T100	1		T101	7		T231	1
values[29]	237	1			T100	1		T101	4		T231	1
values[30]	269	1			T100	1		T101	5		T231	1
values[31]	257	1			T100	1		T101	7		T231	1
values[32]	230	1			T100	1		T101	5		T231	1
values[33]	247	1			T100	1		T101	10		T231	1
values[34]	260	1			T100	1		T101	5		T231	1
values[35]	218	1			T100	1		T101	6		T231	1
values[36]	262	1			T100	1		T101	5		T231	1
values[37]	312	1			T100	1		T101	3		T231	1
values[38]	286	1			T100	1		T101	4		T231	1
values[39]	266	1			T100	1		T101	4		T231	1
values[40]	225	1			T100	1		T101	3		T231	1
values[41]	228	1			T100	1		T101	6		T231	1
values[42]	200	1			T100	1		T101	9		T231	1
values[43]	237	1			T100	1		T101	5		T231	1
values[44]	261	1			T100	1		T101	4		T231	1
values[45]	199	1			T100	1		T101	5		T231	1
values[46]	239	1			T100	1		T101	10		T231	1
values[47]	191	1			T100	1		T101	7		T231	1
values[48]	173	1			T100	1		T101	5		T231	1
values[49]	235	1			T100	1		T101	12		T231	1
values[50]	219	1			T100	1		T101	16		T231	1
values[51]	178	1			T100	1		T101	7		T231	1
values[52]	181	1			T100	1		T101	5		T231	1
values[53]	192	1			T100	1		T101	3		T231	1
values[54]	153	1			T100	1		T101	4		T231	1
values[55]	156	1			T100	1		T101	8		T231	1
values[56]	205	1			T100	1		T101	3		T231	1
values[57]	192	1			T100	1		T101	3		T231	1
values[58]	174	1			T100	1		T101	6		T231	1
values[59]	172	1			T100	1		T101	2		T231	1
values[60]	142	1			T100	1		T101	3		T231	1
values[61]	153	1			T100	1		T101	8		T231	1
values[62]	144	1			T100	1		T101	6		T231	1
values[63]	128	1			T100	1		T101	6		T231	1
values[64]	149	1			T100	1		T101	5		T231	1
values[65]	118	1			T100	1		T101	7		T231	1
values[66]	168	1			T100	1		T101	11		T231	1
values[67]	184	1			T100	1		T101	7		T231	1
values[68]	152	1			T100	1		T101	6		T231	1
values[69]	145	1			T100	1		T101	6		T231	2
values[70]	124	1			T100	1		T101	4		T231	1
values[71]	133	1			T100	1		T101	3		T231	1
values[72]	99	1			T100	1		T101	2		T231	1
values[73]	98	1			T100	1		T101	3		T231	1
values[74]	91	1			T100	1		T101	6		T231	1
values[75]	111	1			T100	1		T101	7		T231	1
values[76]	80	1			T100	1		T101	5		T231	1
values[77]	77	1			T100	1		T101	4		T231	1
values[78]	78	1			T100	1		T101	6		T231	1
values[79]	53	1			T100	2		T101	2		T231	1
values[80]	73	1			T100	2		T101	3		T231	1
values[81]	80	1			T100	8		T101	7		T231	1
values[82]	92	1			T100	2		T101	12		T231	1
values[83]	76	1			T100	1		T101	11		T231	1
values[84]	84	1			T100	3		T101	12		T231	1
values[85]	96	1			T100	5		T101	12		T231	1
values[86]	89	1			T100	4		T101	3		T231	1
values[87]	74	1			T100	4		T101	3		T231	1
values[88]	94	1			T100	3		T101	4		T231	1
values[89]	100	1			T100	2		T101	8		T231	1
values[90]	114	1			T100	3		T101	3		T231	1
values[91]	94	1			T100	4		T101	7		T231	1
values[92]	82	1			T100	2		T101	17		T231	1
values[93]	102	1			T100	5		T101	12		T231	1
values[94]	97	1			T100	4		T101	15		T231	1
values[95]	84	1			T100	3		T101	3		T231	1
values[96]	85	1			T100	4		T101	8		T231	1
values[97]	99	1			T100	5		T101	15		T231	1
values[98]	94	1			T100	2		T101	12		T231	1
values[99]	73	1			T100	1		T101	6		T231	1
values[100]	73	1			T100	8		T101	4		T231	1
values[101]	81	1			T100	1		T101	7		T231	1
values[102]	74	1			T100	1		T101	7		T231	1
values[103]	85	1			T100	2		T101	10		T231	1
values[104]	63	1			T100	1		T101	9		T231	1
values[105]	68	1			T100	2		T101	4		T231	1
values[106]	58	1			T100	3		T101	4		T231	1
values[107]	67	1			T100	1		T101	3		T231	1
values[108]	75	1			T100	2		T101	4		T231	1
values[109]	69	1			T100	3		T101	9		T231	1
values[110]	67	1			T100	3		T101	6		T231	3
values[111]	66	1			T100	2		T101	3		T231	3
values[112]	75	1			T100	2		T101	10		T231	3
values[113]	68	1			T100	3		T101	4		T231	1
values[114]	88	1			T100	2		T101	2		T231	2
values[115]	97	1			T100	3		T101	3		T231	1
values[116]	77	1			T100	1		T101	7		T231	1
values[117]	74	1			T100	1		T101	7		T231	2
values[118]	74	1			T100	3		T101	2		T231	2
values[119]	66	1			T100	1		T101	4		T231	5
values[120]	73	1			T100	1		T101	6		T231	1
values[121]	70	1			T100	2		T101	3		T231	1
values[122]	84	1			T100	1		T101	4		T231	1
values[123]	99	1			T100	1		T101	8		T231	1
values[124]	64	1			T100	2		T101	5		T231	1
values[125]	108	1			T100	2		T101	10		T231	2
values[126]	200	1			T100	4		T101	20		T231	7
values[127]	898	1			T100	35		T101	66		T231	32
values[128]	6192	1			T100	286		T101	29		T231	347