Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.spi_host0_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	151967	1			T32	14		T33	267		T34	7
values[2]	14980	1			T33	8		T100	1		T101	394
values[3]	7128	1			T100	1		T101	161		T382	1
values[4]	3071	1			T100	1		T101	62		T782	1
values[5]	1431	1			T100	1		T101	26		T782	1
values[6]	659	1			T100	1		T101	4		T782	1
values[7]	405	1			T100	1		T782	1		T771	13
values[8]	291	1			T100	1		T782	1		T771	18
values[9]	182	1			T100	1		T782	1		T792	4
values[10]	144	1			T100	2		T782	1		T792	5
values[11]	152	1			T100	1		T782	1		T792	6
values[12]	138	1			T100	1		T782	1		T792	2
values[13]	111	1			T100	1		T782	1		T792	4
values[14]	137	1			T100	1		T782	1		T792	4
values[15]	194	1			T100	1		T782	1		T792	2
values[16]	190	1			T100	1		T782	1		T792	3
values[17]	155	1			T100	1		T782	1		T792	3
values[18]	132	1			T100	1		T782	1		T792	4
values[19]	192	1			T100	1		T782	1		T792	12
values[20]	136	1			T100	1		T782	1		T792	4
values[21]	168	1			T100	1		T782	1		T792	4
values[22]	137	1			T100	1		T782	1		T792	4
values[23]	145	1			T100	1		T782	1		T792	6
values[24]	132	1			T100	1		T782	1		T792	5
values[25]	115	1			T100	1		T782	1		T792	9
values[26]	97	1			T100	1		T782	1		T792	6
values[27]	129	1			T100	1		T782	1		T792	2
values[28]	98	1			T100	1		T782	1		T792	2
values[29]	85	1			T100	1		T782	1		T792	8
values[30]	105	1			T100	1		T782	1		T792	8
values[31]	103	1			T100	1		T782	1		T792	7
values[32]	102	1			T100	1		T782	1		T792	3
values[33]	103	1			T100	1		T782	1		T792	14
values[34]	129	1			T100	1		T782	2		T792	15
values[35]	139	1			T100	1		T782	1		T792	17
values[36]	134	1			T100	1		T782	1		T792	12
values[37]	123	1			T100	1		T782	1		T792	7
values[38]	90	1			T100	1		T782	1		T792	2
values[39]	103	1			T100	1		T782	1		T792	4
values[40]	132	1			T100	1		T782	1		T792	6
values[41]	133	1			T100	1		T782	1		T792	13
values[42]	125	1			T100	1		T782	1		T792	11
values[43]	118	1			T100	1		T782	1		T792	11
values[44]	143	1			T100	1		T782	1		T792	5
values[45]	160	1			T100	1		T782	1		T792	7
values[46]	110	1			T100	1		T782	1		T792	8
values[47]	128	1			T100	1		T782	1		T792	6
values[48]	134	1			T100	1		T782	1		T792	17
values[49]	92	1			T100	1		T782	1		T792	7
values[50]	99	1			T100	1		T782	1		T792	17
values[51]	97	1			T100	1		T782	1		T792	7
values[52]	93	1			T100	1		T782	1		T792	5
values[53]	128	1			T100	1		T782	1		T792	16
values[54]	131	1			T100	1		T782	1		T792	31
values[55]	106	1			T100	1		T782	1		T792	27
values[56]	105	1			T100	1		T782	1		T792	37
values[57]	128	1			T100	1		T782	1		T792	22
values[58]	110	1			T100	1		T782	1		T792	7
values[59]	92	1			T100	1		T782	1		T792	1
values[60]	81	1			T100	1		T782	1		T775	4
values[61]	49	1			T100	1		T782	1		T778	1
values[62]	48	1			T100	1		T782	1		T778	1
values[63]	41	1			T100	1		T782	1		T778	1
values[64]	47	1			T100	1		T782	1		T778	1
values[65]	53	1			T100	1		T782	1		T778	1
values[66]	34	1			T100	1		T782	1		T778	1
values[67]	36	1			T100	1		T782	1		T778	1
values[68]	46	1			T100	1		T782	1		T778	1
values[69]	36	1			T100	1		T782	1		T778	1
values[70]	39	1			T100	1		T782	1		T778	1
values[71]	46	1			T100	1		T782	1		T778	1
values[72]	56	1			T100	1		T782	1		T778	1
values[73]	87	1			T100	1		T782	1		T778	1
values[74]	71	1			T100	1		T782	1		T778	1
values[75]	58	1			T100	1		T782	1		T778	1
values[76]	40	1			T100	1		T782	1		T778	1
values[77]	38	1			T100	1		T782	1		T778	1
values[78]	38	1			T100	1		T782	1		T778	1
values[79]	53	1			T100	1		T782	1		T778	1
values[80]	48	1			T100	1		T782	1		T778	1
values[81]	35	1			T100	1		T782	1		T778	1
values[82]	27	1			T100	1		T782	1		T778	1
values[83]	34	1			T100	1		T782	1		T778	1
values[84]	36	1			T100	2		T782	1		T778	1
values[85]	26	1			T100	1		T782	1		T778	1
values[86]	41	1			T100	1		T782	1		T778	1
values[87]	40	1			T100	1		T782	1		T778	1
values[88]	40	1			T100	1		T782	1		T778	1
values[89]	48	1			T100	1		T782	1		T778	1
values[90]	45	1			T100	1		T782	1		T778	1
values[91]	41	1			T100	1		T782	1		T778	1
values[92]	41	1			T100	1		T782	1		T778	1
values[93]	31	1			T100	1		T782	1		T778	1
values[94]	39	1			T100	1		T782	1		T778	1
values[95]	48	1			T100	1		T782	1		T778	1
values[96]	38	1			T100	1		T782	2		T778	2
values[97]	42	1			T100	1		T782	1		T778	1
values[98]	38	1			T100	1		T782	1		T778	1
values[99]	36	1			T100	1		T782	1		T778	1
values[100]	38	1			T100	1		T782	1		T778	1
values[101]	36	1			T100	1		T782	1		T778	1
values[102]	37	1			T100	1		T782	1		T778	1
values[103]	34	1			T100	1		T782	1		T778	1
values[104]	33	1			T100	1		T782	1		T778	1
values[105]	29	1			T100	1		T782	1		T778	1
values[106]	33	1			T100	1		T782	1		T778	1
values[107]	44	1			T100	1		T782	1		T778	1
values[108]	50	1			T100	1		T782	6		T778	3
values[109]	40	1			T100	1		T782	1		T778	3
values[110]	47	1			T100	1		T782	2		T778	3
values[111]	33	1			T100	1		T782	2		T778	1
values[112]	44	1			T100	2		T782	5		T778	4
values[113]	46	1			T100	3		T782	3		T778	2
values[114]	57	1			T100	5		T782	1		T778	4
values[115]	42	1			T100	1		T782	1		T778	3
values[116]	54	1			T100	2		T782	1		T778	7
values[117]	50	1			T100	2		T782	2		T778	1
values[118]	48	1			T100	3		T782	2		T778	3
values[119]	50	1			T100	1		T782	3		T778	3
values[120]	43	1			T100	2		T782	1		T778	1
values[121]	44	1			T100	4		T782	1		T778	1
values[122]	41	1			T100	2		T782	1		T778	2
values[123]	43	1			T100	3		T782	1		T778	3
values[124]	42	1			T100	2		T782	3		T778	1
values[125]	39	1			T100	1		T782	2		T778	1
values[126]	291	1			T100	15		T782	22		T778	17
values[127]	2583	1			T100	132		T782	146		T778	95
values[128]	5192	1			T100	239		T782	253		T778	202