Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_ret_aon__regs_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	133647	1			T32	12		T33	288		T34	3
values[2]	9352	1			T32	1		T33	3		T100	1
values[3]	3634	1			T100	1		T382	1		T782	1
values[4]	2184	1			T100	1		T782	1		T397	49
values[5]	1617	1			T100	1		T782	1		T397	13
values[6]	1189	1			T100	1		T782	1		T397	7
values[7]	923	1			T100	1		T782	1		T537	4
values[8]	674	1			T100	1		T782	1		T537	14
values[9]	525	1			T100	1		T782	1		T537	4
values[10]	439	1			T100	1		T782	1		T537	4
values[11]	357	1			T100	1		T782	1		T537	2
values[12]	357	1			T100	1		T782	1		T537	8
values[13]	410	1			T100	1		T782	1		T537	13
values[14]	396	1			T100	1		T782	1		T537	3
values[15]	327	1			T100	1		T782	1		T537	7
values[16]	353	1			T100	1		T782	1		T537	11
values[17]	333	1			T100	1		T782	1		T537	10
values[18]	320	1			T100	1		T782	1		T537	11
values[19]	301	1			T100	1		T782	1		T537	3
values[20]	307	1			T100	1		T782	1		T537	6
values[21]	303	1			T100	1		T782	1		T537	10
values[22]	288	1			T100	1		T782	1		T537	8
values[23]	270	1			T100	1		T782	1		T537	7
values[24]	285	1			T100	1		T782	1		T537	17
values[25]	300	1			T100	1		T782	1		T537	7
values[26]	290	1			T100	1		T782	1		T537	6
values[27]	274	1			T100	1		T782	1		T537	6
values[28]	279	1			T100	1		T782	1		T537	5
values[29]	289	1			T100	1		T782	1		T537	4
values[30]	279	1			T100	1		T782	1		T537	7
values[31]	301	1			T100	1		T782	1		T537	7
values[32]	300	1			T100	1		T782	1		T537	14
values[33]	303	1			T100	1		T782	1		T537	10
values[34]	296	1			T100	1		T782	1		T537	5
values[35]	302	1			T100	1		T782	1		T537	9
values[36]	240	1			T100	1		T782	1		T537	5
values[37]	267	1			T100	1		T782	1		T537	8
values[38]	286	1			T100	1		T782	1		T537	3
values[39]	265	1			T100	1		T782	1		T537	5
values[40]	244	1			T100	1		T782	1		T537	11
values[41]	234	1			T100	1		T782	1		T537	12
values[42]	256	1			T100	1		T782	1		T537	7
values[43]	275	1			T100	1		T782	1		T537	3
values[44]	250	1			T100	1		T782	1		T537	9
values[45]	233	1			T100	1		T782	1		T537	15
values[46]	261	1			T100	1		T782	1		T537	5
values[47]	275	1			T100	1		T782	1		T537	23
values[48]	249	1			T100	1		T782	1		T537	6
values[49]	278	1			T100	1		T782	1		T537	10
values[50]	286	1			T100	1		T782	1		T537	7
values[51]	225	1			T100	1		T782	1		T537	3
values[52]	219	1			T100	1		T782	1		T537	7
values[53]	207	1			T100	1		T782	1		T537	8
values[54]	253	1			T100	1		T782	1		T537	5
values[55]	276	1			T100	1		T782	1		T537	3
values[56]	260	1			T100	1		T782	1		T537	4
values[57]	238	1			T100	1		T782	1		T537	8
values[58]	214	1			T100	1		T782	1		T537	8
values[59]	202	1			T100	1		T782	1		T537	4
values[60]	187	1			T100	1		T782	1		T537	7
values[61]	196	1			T100	1		T782	1		T537	3
values[62]	202	1			T100	1		T782	1		T537	12
values[63]	191	1			T100	1		T782	1		T537	13
values[64]	171	1			T100	1		T782	1		T535	9
values[65]	173	1			T100	1		T782	2		T535	7
values[66]	173	1			T100	1		T782	1		T535	7
values[67]	196	1			T100	1		T782	1		T535	2
values[68]	165	1			T100	1		T782	1		T792	12
values[69]	131	1			T100	1		T782	1		T792	5
values[70]	154	1			T100	1		T782	1		T792	8
values[71]	147	1			T100	1		T782	1		T792	10
values[72]	120	1			T100	1		T782	1		T792	8
values[73]	135	1			T100	1		T782	1		T792	12
values[74]	110	1			T100	1		T782	1		T792	5
values[75]	107	1			T100	1		T782	1		T792	12
values[76]	115	1			T100	1		T782	1		T792	13
values[77]	97	1			T100	1		T782	1		T792	10
values[78]	120	1			T100	1		T782	1		T792	5
values[79]	130	1			T100	1		T782	1		T792	9
values[80]	103	1			T100	1		T782	1		T792	7
values[81]	134	1			T100	1		T782	1		T792	4
values[82]	99	1			T100	1		T782	2		T792	3
values[83]	86	1			T100	1		T782	4		T792	2
values[84]	88	1			T100	1		T782	1		T792	2
values[85]	109	1			T100	1		T782	4		T792	6
values[86]	93	1			T100	1		T782	1		T792	2
values[87]	94	1			T100	1		T782	4		T792	4
values[88]	109	1			T100	1		T782	2		T792	8
values[89]	98	1			T100	1		T782	4		T792	2
values[90]	78	1			T100	1		T782	3		T769	1
values[91]	69	1			T100	1		T782	3		T769	1
values[92]	87	1			T100	1		T782	4		T769	1
values[93]	100	1			T100	1		T782	8		T769	1
values[94]	94	1			T100	2		T782	4		T769	1
values[95]	98	1			T100	1		T782	6		T769	1
values[96]	85	1			T100	1		T782	3		T769	1
values[97]	84	1			T100	1		T782	3		T769	1
values[98]	88	1			T100	1		T782	3		T769	1
values[99]	84	1			T100	1		T782	3		T769	1
values[100]	63	1			T100	1		T782	3		T769	1
values[101]	55	1			T100	1		T782	2		T769	1
values[102]	64	1			T100	1		T782	1		T769	1
values[103]	82	1			T100	3		T782	3		T769	1
values[104]	64	1			T100	3		T782	2		T769	1
values[105]	61	1			T100	2		T782	4		T769	1
values[106]	72	1			T100	4		T782	3		T769	1
values[107]	73	1			T100	3		T782	4		T769	1
values[108]	61	1			T100	3		T782	1		T769	1
values[109]	67	1			T100	1		T782	2		T769	1
values[110]	59	1			T100	1		T782	2		T769	1
values[111]	56	1			T100	3		T782	1		T769	1
values[112]	68	1			T100	2		T782	1		T769	3
values[113]	55	1			T100	2		T782	3		T769	1
values[114]	71	1			T100	6		T782	1		T769	2
values[115]	70	1			T100	1		T782	1		T769	4
values[116]	74	1			T100	1		T782	2		T769	2
values[117]	55	1			T100	4		T782	4		T769	1
values[118]	57	1			T100	4		T782	4		T769	1
values[119]	61	1			T100	1		T782	6		T769	1
values[120]	62	1			T100	1		T782	1		T769	2
values[121]	73	1			T100	1		T782	6		T769	4
values[122]	53	1			T100	2		T782	1		T769	1
values[123]	54	1			T100	1		T782	1		T769	8
values[124]	62	1			T100	1		T782	1		T769	1
values[125]	80	1			T100	1		T782	1		T769	2
values[126]	180	1			T100	1		T782	1		T769	1
values[127]	860	1			T100	45		T782	30		T769	31
values[128]	5009	1			T100	341		T782	287		T769	267