Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.sysrst_ctrl_aon_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	134756	1			T32	13		T33	338		T34	16
values[2]	9331	1			T33	92		T100	1		T101	3
values[3]	3367	1			T33	53		T100	1		T123	4
values[4]	1877	1			T33	34		T100	1		T123	1
values[5]	1075	1			T33	25		T100	1		T123	2
values[6]	716	1			T33	10		T100	1		T123	4
values[7]	591	1			T33	4		T100	1		T123	5
values[8]	447	1			T33	1		T100	1		T123	8
values[9]	392	1			T100	1		T123	3		T397	3
values[10]	350	1			T100	1		T123	1		T675	4
values[11]	326	1			T100	2		T123	2		T675	10
values[12]	276	1			T100	1		T123	2		T675	3
values[13]	261	1			T100	1		T123	6		T381	2
values[14]	232	1			T100	1		T123	3		T405	10
values[15]	249	1			T100	1		T123	3		T405	3
values[16]	272	1			T100	1		T123	3		T405	10
values[17]	230	1			T100	1		T123	1		T405	12
values[18]	219	1			T100	1		T123	3		T405	8
values[19]	237	1			T100	1		T123	4		T405	10
values[20]	243	1			T100	1		T123	2		T405	10
values[21]	227	1			T100	1		T123	1		T405	6
values[22]	221	1			T100	1		T123	1		T553	11
values[23]	235	1			T100	1		T123	3		T553	9
values[24]	182	1			T100	1		T123	1		T553	4
values[25]	216	1			T100	1		T123	11		T553	5
values[26]	226	1			T100	1		T123	8		T553	2
values[27]	191	1			T100	1		T123	14		T553	7
values[28]	156	1			T100	1		T123	7		T553	4
values[29]	238	1			T100	1		T123	6		T553	6
values[30]	226	1			T100	1		T123	4		T553	16
values[31]	188	1			T100	1		T123	4		T553	6
values[32]	209	1			T100	1		T123	2		T553	14
values[33]	149	1			T100	1		T123	2		T553	5
values[34]	172	1			T100	1		T123	1		T553	7
values[35]	209	1			T100	1		T123	2		T553	8
values[36]	203	1			T100	1		T123	4		T553	7
values[37]	169	1			T100	1		T123	1		T553	4
values[38]	232	1			T100	1		T123	1		T553	6
values[39]	197	1			T100	1		T123	7		T553	4
values[40]	196	1			T100	1		T123	4		T553	10
values[41]	173	1			T100	1		T123	2		T553	6
values[42]	201	1			T100	1		T123	5		T553	19
values[43]	171	1			T100	1		T123	3		T553	7
values[44]	164	1			T100	1		T123	3		T553	4
values[45]	150	1			T100	1		T123	1		T553	9
values[46]	196	1			T100	1		T123	1		T553	7
values[47]	195	1			T100	1		T123	1		T553	9
values[48]	155	1			T100	1		T123	5		T553	11
values[49]	154	1			T100	1		T123	2		T553	4
values[50]	165	1			T100	1		T123	3		T553	3
values[51]	159	1			T100	2		T123	2		T773	1
values[52]	179	1			T100	1		T123	3		T773	1
values[53]	152	1			T100	1		T123	1		T773	1
values[54]	117	1			T100	1		T123	2		T773	1
values[55]	128	1			T100	1		T123	3		T773	1
values[56]	150	1			T100	1		T123	3		T773	1
values[57]	146	1			T100	1		T123	3		T773	1
values[58]	150	1			T100	1		T123	2		T773	1
values[59]	149	1			T100	1		T123	3		T773	1
values[60]	125	1			T100	1		T123	3		T773	1
values[61]	142	1			T100	1		T123	4		T773	1
values[62]	116	1			T100	1		T123	3		T773	1
values[63]	124	1			T100	1		T123	4		T773	1
values[64]	130	1			T100	1		T123	4		T773	1
values[65]	116	1			T100	1		T123	4		T773	1
values[66]	102	1			T100	1		T123	6		T773	1
values[67]	122	1			T100	1		T123	6		T773	1
values[68]	96	1			T100	1		T123	3		T773	1
values[69]	103	1			T100	1		T123	1		T773	1
values[70]	100	1			T100	1		T123	5		T773	1
values[71]	90	1			T100	1		T123	2		T773	2
values[72]	61	1			T100	1		T123	2		T773	1
values[73]	73	1			T100	2		T123	1		T773	1
values[74]	70	1			T100	1		T123	1		T773	1
values[75]	69	1			T100	1		T123	2		T773	1
values[76]	70	1			T100	1		T123	1		T773	1
values[77]	67	1			T100	1		T123	2		T773	1
values[78]	57	1			T100	1		T123	3		T773	1
values[79]	43	1			T100	1		T123	2		T773	1
values[80]	69	1			T100	1		T123	3		T773	1
values[81]	51	1			T100	1		T123	3		T773	1
values[82]	56	1			T100	1		T123	1		T773	1
values[83]	59	1			T100	1		T123	1		T773	1
values[84]	66	1			T100	1		T123	1		T773	1
values[85]	51	1			T100	1		T123	6		T773	1
values[86]	45	1			T100	1		T123	3		T773	1
values[87]	48	1			T100	1		T123	7		T773	1
values[88]	45	1			T100	1		T123	7		T773	1
values[89]	57	1			T100	1		T123	1		T773	1
values[90]	42	1			T100	1		T123	2		T773	1
values[91]	53	1			T100	1		T123	5		T773	1
values[92]	53	1			T100	1		T123	3		T773	1
values[93]	45	1			T100	1		T123	3		T773	1
values[94]	48	1			T100	1		T123	3		T773	1
values[95]	45	1			T100	1		T123	6		T773	1
values[96]	35	1			T100	1		T123	2		T773	1
values[97]	50	1			T100	1		T123	5		T773	1
values[98]	30	1			T100	1		T123	1		T773	1
values[99]	43	1			T100	1		T123	7		T773	1
values[100]	48	1			T100	1		T123	4		T773	1
values[101]	42	1			T100	1		T123	3		T773	1
values[102]	50	1			T100	1		T123	4		T773	2
values[103]	62	1			T100	1		T123	7		T773	6
values[104]	55	1			T100	1		T123	8		T773	3
values[105]	56	1			T100	1		T123	2		T773	1
values[106]	56	1			T100	1		T123	6		T773	5
values[107]	47	1			T100	1		T123	5		T773	1
values[108]	38	1			T100	1		T123	3		T773	2
values[109]	39	1			T100	1		T123	1		T773	3
values[110]	39	1			T100	1		T123	4		T773	6
values[111]	39	1			T100	1		T123	1		T773	8
values[112]	39	1			T100	1		T123	3		T773	1
values[113]	45	1			T100	1		T123	6		T773	2
values[114]	30	1			T100	1		T123	3		T773	1
values[115]	32	1			T100	1		T123	4		T773	1
values[116]	27	1			T100	1		T123	1		T773	2
values[117]	34	1			T100	1		T123	5		T773	1
values[118]	34	1			T100	1		T123	5		T773	1
values[119]	33	1			T100	3		T123	4		T773	4
values[120]	30	1			T100	1		T123	5		T773	3
values[121]	35	1			T100	5		T123	6		T773	1
values[122]	43	1			T100	4		T123	12		T773	1
values[123]	41	1			T100	7		T123	6		T773	1
values[124]	39	1			T100	6		T123	3		T773	1
values[125]	47	1			T100	6		T123	9		T773	1
values[126]	50	1			T100	3		T123	15		T773	4
values[127]	476	1			T100	33		T123	44		T773	34
values[128]	4301	1			T100	321		T123	21		T773	303