Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	468	1			T101	1		T123	2		T232	1
all_values[1]	493	1			T123	1		T395	2		T396	1
all_values[2]	475	1			T33	1		T395	3		T351	4
all_values[3]	484	1			T33	1		T396	1		T351	1
all_values[4]	470	1			T100	1		T101	2		T782	1
all_values[5]	489	1			T101	2		T231	2		T395	1
all_values[6]	484	1			T101	1		T395	3		T396	1
all_values[7]	499	1			T33	2		T395	2		T396	1
all_values[8]	487	1			T101	1		T123	1		T395	4
all_values[9]	464	1			T101	1		T231	1		T782	1
all_values[10]	445	1			T231	1		T123	2		T395	3
all_values[11]	474	1			T123	2		T782	1		T395	2
all_values[12]	449	1			T101	1		T123	2		T395	1
all_values[13]	480	1			T33	1		T123	2		T395	2
all_values[14]	474	1			T33	1		T100	1		T395	2
all_values[15]	453	1			T33	1		T123	1		T782	1
all_values[16]	437	1			T100	1		T395	3		T397	1
all_values[17]	471	1			T33	2		T397	3		T675	1
all_values[18]	456	1			T232	1		T782	1		T395	4
all_values[19]	471	1			T395	5		T396	1		T397	7
all_values[20]	480	1			T231	1		T395	2		T397	4
all_values[21]	437	1			T395	2		T396	1		T397	2
all_values[22]	458	1			T100	1		T395	1		T351	2
all_values[23]	443	1			T33	2		T232	1		T396	1
all_values[24]	456	1			T231	1		T395	3		T397	1
all_values[25]	467	1			T33	1		T123	2		T395	2
all_values[26]	520	1			T101	1		T231	2		T123	1
all_values[27]	476	1			T231	2		T123	2		T395	3
all_values[28]	436	1			T33	3		T101	1		T123	1
all_values[29]	467	1			T101	1		T395	6		T396	2
all_values[30]	457	1			T33	1		T231	1		T123	1
all_values[31]	443	1			T33	1		T101	1		T123	1
all_values[32]	453	1			T33	2		T101	1		T231	1
all_values[33]	432	1			T100	1		T101	2		T231	1
all_values[34]	447	1			T33	2		T101	1		T782	1
all_values[35]	486	1			T395	3		T396	1		T351	1
all_values[36]	442	1			T123	2		T395	4		T396	1
all_values[37]	471	1			T33	1		T100	1		T231	1
all_values[38]	472	1			T395	1		T396	1		T397	4
all_values[39]	456	1			T395	2		T396	1		T351	1
all_values[40]	452	1			T33	2		T100	1		T101	1
all_values[41]	478	1			T33	2		T231	2		T395	2
all_values[42]	484	1			T100	1		T123	3		T395	3
all_values[43]	490	1			T395	4		T351	1		T397	6
all_values[44]	472	1			T100	1		T123	1		T782	1
all_values[45]	468	1			T395	2		T396	1		T351	4
all_values[46]	489	1			T395	3		T351	2		T397	1
all_values[47]	437	1			T33	1		T100	1		T123	1
all_values[48]	454	1			T33	1		T101	1		T395	1
all_values[49]	510	1			T123	1		T395	5		T351	3