Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3545	1			T33	1		T101	6		T123	5
all_values[1]	3587	1			T33	3		T101	5		T123	4
all_values[2]	3472	1			T33	1		T123	9		T107	1
all_values[3]	3492	1			T101	3		T123	4		T107	3
all_values[4]	3489	1			T33	2		T101	6		T123	2
all_values[5]	3579	1			T33	1		T101	3		T123	5
all_values[6]	3540	1			T33	2		T101	4		T123	2
all_values[7]	3604	1			T101	3		T123	5		T107	1
all_values[8]	3490	1			T33	2		T101	5		T123	4
all_values[9]	3508	1			T33	1		T101	3		T123	4
all_values[10]	3531	1			T33	1		T101	2		T123	2
all_values[11]	3584	1			T33	2		T101	2		T123	4
all_values[12]	3603	1			T33	2		T101	3		T123	6
all_values[13]	3493	1			T101	2		T123	8		T395	9
all_values[14]	3565	1			T33	1		T101	1		T123	9
all_values[15]	3590	1			T101	4		T123	12		T107	2
all_values[16]	3579	1			T33	1		T101	4		T123	4
all_values[17]	3457	1			T101	6		T123	3		T107	3
all_values[18]	3425	1			T33	1		T101	6		T123	4
all_values[19]	3547	1			T101	3		T123	6		T107	1
all_values[20]	3506	1			T101	4		T123	5		T107	2
all_values[21]	3481	1			T101	5		T123	10		T107	2
all_values[22]	3540	1			T101	2		T123	4		T395	14
all_values[23]	3545	1			T33	2		T101	4		T123	3
all_values[24]	3620	1			T33	1		T101	1		T123	6
all_values[25]	3614	1			T33	1		T123	3		T107	1
all_values[26]	3549	1			T33	1		T101	1		T123	4
all_values[27]	3543	1			T101	1		T123	2		T107	1
all_values[28]	3552	1			T33	1		T101	6		T123	2
all_values[29]	3575	1			T101	7		T123	6		T107	2
all_values[30]	3513	1			T33	1		T101	6		T123	4
all_values[31]	3587	1			T101	4		T123	4		T107	1
all_values[32]	3522	1			T33	1		T101	4		T123	8
all_values[33]	3519	1			T33	1		T101	1		T123	7
all_values[34]	3585	1			T33	1		T101	3		T123	6
all_values[35]	3543	1			T101	4		T123	6		T107	5
all_values[36]	3498	1			T101	4		T123	5		T107	1
all_values[37]	3606	1			T101	5		T123	4		T107	1
all_values[38]	3583	1			T101	6		T123	4		T107	1
all_values[39]	3496	1			T33	2		T101	1		T123	6
all_values[40]	3603	1			T101	3		T123	4		T107	4
all_values[41]	3595	1			T33	3		T101	5		T123	5
all_values[42]	3547	1			T33	1		T101	2		T123	4
all_values[43]	3533	1			T101	1		T123	2		T107	4
all_values[44]	3634	1			T101	3		T123	6		T107	2
all_values[45]	3468	1			T33	1		T101	4		T123	2
all_values[46]	3574	1			T101	4		T123	7		T107	4
all_values[47]	3521	1			T33	1		T101	2		T123	5
all_values[48]	3608	1			T33	2		T101	4		T123	2
all_values[49]	3598	1			T101	4		T123	2		T395	14
all_values[50]	3518	1			T33	3		T101	1		T123	4
all_values[51]	3541	1			T33	2		T101	3		T123	1
all_values[52]	3655	1			T101	5		T123	3		T107	1
all_values[53]	3456	1			T33	1		T101	3		T123	1
all_values[54]	3562	1			T33	2		T101	3		T123	5
all_values[55]	3568	1			T101	6		T123	8		T107	2
all_values[56]	3612	1			T33	2		T123	2		T107	1
all_values[57]	3491	1			T33	3		T101	5		T123	6
all_values[58]	3571	1			T33	3		T101	9		T123	6
all_values[59]	3506	1			T33	2		T101	3		T123	5
all_values[60]	3583	1			T101	4		T123	4		T107	1
all_values[61]	3469	1			T101	4		T123	3		T107	3
all_values[62]	3601	1			T33	2		T101	4		T123	3
all_values[63]	3596	1			T33	1		T101	3		T123	7