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 LINE       35417
 EXPRESSION (addr_hit[562] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T33,T101,T230
1	0	1	Covered	T100,T101,T123
1	1	0	Covered	T420,T468,T433
1	1	1	Covered	T101,T59,T385

 LINE       35420
 EXPRESSION (addr_hit[563] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T33,T101,T230
1	0	1	Covered	T33,T101,T107
1	1	0	Covered	T377,T321,T437
1	1	1	Covered	T59,T348,T56

 LINE       35423
 EXPRESSION (addr_hit[564] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T33,T101,T230
1	0	1	Covered	T33,T101,T123
1	1	0	Covered	T380,T552,T321
1	1	1	Covered	T388,T59,T56

 LINE       35426
 EXPRESSION (addr_hit[565] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T33,T101,T230
1	0	1	Covered	T33,T101,T231
1	1	0	Covered	T338,T321,T596
1	1	1	Covered	T59,T337,T56

 LINE       35429
 EXPRESSION (addr_hit[566] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T33,T101,T230
1	0	1	Covered	T33,T101,T231
1	1	0	Covered	T534,T468,T411
1	1	1	Covered	T59,T56,T57

 LINE       35432
 EXPRESSION (addr_hit[567] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T33,T101,T230
1	0	1	Covered	T33,T100,T101
1	1	0	Covered	T432,T457,T437
1	1	1	Covered	T59,T349,T346

 LINE       38842
 EXPRESSION (reg_busy_sel | shadow_busy)
             ------1-----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T32,T33,T34
0	1	Unreachable
1	0	Covered	T59,T56,T57