CHIP Simulation Results

Wednesday January 10 2024 20:03:22 UTC

GitHub Revision: `cf38c1d296`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 55803132295021657086212552594002090640066687299415498461130788370399872772386

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	3.987m	3.207ms	3	3	100.00
		chip_sw_example_rom	2.246m	2.011ms	3	3	100.00
		chip_sw_example_manufacturer	4.728m	2.615ms	3	3	100.00
		chip_sw_example_concurrency	5.318m	3.285ms	3	3	100.00
		chip_sw_uart_smoketest_signed	30.911m	8.868ms	3	3	100.00
V1	csr_hw_reset	chip_csr_hw_reset	6.080m	5.600ms	5	5	100.00
V1	csr_rw	chip_csr_rw	11.743m	6.394ms	20	20	100.00
V1	csr_bit_bash	chip_csr_bit_bash	30.639m	13.976ms	5	5	100.00
V1	csr_aliasing	chip_csr_aliasing	2.722h	57.944ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	6.620m	10.182ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	2.722h	57.944ms	5	5	100.00
		chip_csr_rw	11.743m	6.394ms	20	20	100.00
V1	xbar_smoke	xbar_smoke	10.230s	262.883us	100	100	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	7.373m	3.364ms	3	3	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	7.373m	3.364ms	3	3	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	7.373m	3.364ms	3	3	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	15.199m	5.335ms	5	5	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	15.199m	5.335ms	5	5	100.00
		chip_sw_uart_tx_rx_idx1	16.166m	5.861ms	5	5	100.00
		chip_sw_uart_tx_rx_idx2	14.999m	6.204ms	5	5	100.00
		chip_sw_uart_tx_rx_idx3	16.269m	5.661ms	5	5	100.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	1.142h	22.670ms	20	20	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	59.809m	23.125ms	5	5	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	27.186m	13.206ms	5	5	100.00
V1		TOTAL			223	223	100.00
V2	chip_pin_mux	chip_padctrl_attributes	5.569m	4.928ms	10	10	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	5.569m	4.928ms	10	10	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	4.558m	3.245ms	3	3	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	7.467m	5.132ms	3	3	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	6.022m	3.813ms	3	3	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	19.592m	14.593ms	5	5	100.00
		chip_tap_straps_testunlock0	18.209m	10.151ms	5	5	100.00
		chip_tap_straps_rma	8.822m	6.472ms	5	5	100.00
		chip_tap_straps_prod	21.336m	12.474ms	5	5	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	4.754m	2.757ms	3	3	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	18.433m	7.851ms	3	3	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	14.812m	5.451ms	6	6	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	14.812m	5.451ms	6	6	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	5.552m	2.757ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	8.067m	3.881ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	11.257m	4.857ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	25.149m	21.157ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_sysrst_ctrl_reset	25.149m	21.157ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	25.149m	21.157ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	49.385m	20.758ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	49.385m	20.758ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	10.209m	6.150ms	3	3	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	11.130m	18.454ms	3	3	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	16.439m	7.523ms	3	3	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	12.410m	11.247ms	3	3	100.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	16.509m	5.357ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	16.933m	5.412ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	53.580m	18.859ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	4.097m	2.537ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	19.579m	5.478ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	4.923m	3.279ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	6.545m	4.309ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	5.576m	3.430ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	10.527m	4.125ms	3	3	100.00
		chip_sw_clkmgr_jitter	4.548m	2.642ms	3	3	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	5.383m	3.145ms	1	1	100.00
V2	chip_sw_ast_alerts	chip_sw_sensor_ctrl_alert	15.424m	9.383ms	5	5	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	15.424m	9.383ms	5	5	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	7.237m	5.418ms	3	3	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	5.633m	3.316ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	7.237m	5.418ms	3	3	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	3.268m	2.536ms	3	3	100.00
		chip_sw_aes_smoketest	4.573m	2.336ms	3	3	100.00
		chip_sw_aon_timer_smoketest	5.427m	3.290ms	3	3	100.00
		chip_sw_clkmgr_smoketest	4.175m	2.398ms	3	3	100.00
		chip_sw_csrng_smoketest	3.525m	2.811ms	3	3	100.00
		chip_sw_entropy_src_smoketest	7.090m	2.956ms	3	3	100.00
		chip_sw_gpio_smoketest	4.954m	2.742ms	3	3	100.00
		chip_sw_hmac_smoketest	6.298m	2.786ms	3	3	100.00
		chip_sw_kmac_smoketest	5.225m	3.030ms	3	3	100.00
		chip_sw_otbn_smoketest	32.116m	10.033ms	3	3	100.00
		chip_sw_otp_ctrl_smoketest	5.260m	3.535ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	8.091m	5.567ms	3	3	100.00
		chip_sw_pwrmgr_usbdev_smoketest	6.219m	5.010ms	3	3	100.00
		chip_sw_rv_plic_smoketest	4.985m	2.796ms	3	3	100.00
		chip_sw_rv_timer_smoketest	3.743m	3.362ms	3	3	100.00
		chip_sw_rstmgr_smoketest	3.543m	2.444ms	3	3	100.00
		chip_sw_sram_ctrl_smoketest	5.144m	3.254ms	3	3	100.00
		chip_sw_uart_smoketest	4.506m	2.711ms	3	3	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	8.661m	5.226ms	3	3	100.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	30.911m	8.868ms	3	3	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	3.386h	73.019ms	3	3	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	31.734m	8.562ms	3	3	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	32.594m	15.581ms	3	3	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	10.871m	4.077ms	3	3	100.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	7.834m	4.663ms	3	3	100.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	2.775h	61.812ms	3	3	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	3.103h	67.414ms	3	3	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	8.916m	4.673ms	30	30	100.00
V2	tl_d_illegal_access	chip_tl_errors	8.916m	4.673ms	30	30	100.00
V2	tl_d_outstanding_access	chip_csr_aliasing	2.722h	57.944ms	5	5	100.00
		chip_same_csr_outstanding	1.140h	31.442ms	20	20	100.00
		chip_csr_hw_reset	6.080m	5.600ms	5	5	100.00
		chip_csr_rw	11.743m	6.394ms	20	20	100.00
V2	tl_d_partial_access	chip_csr_aliasing	2.722h	57.944ms	5	5	100.00
		chip_same_csr_outstanding	1.140h	31.442ms	20	20	100.00
		chip_csr_hw_reset	6.080m	5.600ms	5	5	100.00
		chip_csr_rw	11.743m	6.394ms	20	20	100.00
V2	xbar_base_random_sequence	xbar_random	1.567m	2.593ms	100	100	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	6.830s	54.457us	100	100	100.00
		xbar_smoke_large_delays	1.859m	10.321ms	100	100	100.00
		xbar_smoke_slow_rsp	1.945m	6.732ms	100	100	100.00
		xbar_random_zero_delays	53.270s	599.000us	100	100	100.00
		xbar_random_large_delays	23.690m	124.106ms	100	100	100.00
		xbar_random_slow_rsp	22.966m	71.564ms	100	100	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	1.117m	1.560ms	100	100	100.00
		xbar_error_and_unmapped_addr	59.290s	1.486ms	100	100	100.00
V2	xbar_error_cases	xbar_error_random	1.493m	2.562ms	100	100	100.00
		xbar_error_and_unmapped_addr	59.290s	1.486ms	100	100	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	2.300m	3.478ms	100	100	100.00
		xbar_access_same_device_slow_rsp	47.249m	162.796ms	100	100	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	1.397m	2.708ms	100	100	100.00
V2	xbar_stress_all	xbar_stress_all	14.365m	21.476ms	100	100	100.00
		xbar_stress_all_with_error	12.213m	17.539ms	100	100	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	15.718m	7.995ms	100	100	100.00
		xbar_stress_all_with_reset_error	19.457m	23.479ms	100	100	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	31.734m	8.562ms	3	3	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	43.330m	24.534ms	3	3	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	27.924m	9.137ms	3	3	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	22.453m	6.810ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	30.053m	8.939ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	27.193m	8.888ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	26.461m	9.510ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	24.028m	8.797ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	21.134m	7.235ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	26.096m	8.793ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	28.537m	7.940ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	27.514m	9.107ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	27.230m	8.293ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	33.772m	10.157ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	39.954m	12.169ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	42.601m	12.313ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	41.577m	12.146ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	42.040m	11.562ms	1	1	100.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	31.372m	10.220ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	38.295m	12.191ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	38.009m	12.149ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	42.754m	11.634ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	40.452m	11.702ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	21.633m	6.936ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	25.057m	8.392ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	27.635m	8.233ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	24.590m	8.535ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	31.067m	8.515ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	20.130m	7.565ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	24.255m	8.165ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	24.671m	8.688ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	23.444m	8.850ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	23.971m	8.308ms	1	1	100.00
V2	rom_e2e_sigverify_mod_exp	rom_e2e_sigverify_mod_exp_test_unlocked0_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_dev_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_rma_sw			0	3	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	21.562m	6.774ms	3	3	100.00
		rom_e2e_asm_init_dev	27.966m	8.640ms	3	3	100.00
		rom_e2e_asm_init_prod	30.010m	8.619ms	3	3	100.00
		rom_e2e_asm_init_prod_end	30.567m	8.927ms	3	3	100.00
		rom_e2e_asm_init_rma	28.427m	9.244ms	3	3	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas			0	3	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas			0	3	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas			0	3	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	35.789m	10.995ms	3	3	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	4.360m	2.444ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	4.097m	2.537ms	3	3	100.00
V2	chip_sw_aes_multi_block	chip_sw_aes_multi_block			0	0	--
V2	chip_sw_aes_interrupt_encryption	chip_sw_aes_interrupt_encryption			0	0	--
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	5.058m	2.307ms	3	3	100.00
V2	chip_sw_aes_prng_reseed	chip_sw_aes_prng_reseed			0	0	--
V2	chip_sw_aes_force_prng_reseed	chip_sw_aes_force_prng_reseed			0	0	--
V2	chip_sw_aes_idle	chip_sw_aes_idle	3.364m	2.998ms	3	3	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	8.465m	4.239ms	3	3	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	11.130m	18.454ms	3	3	100.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	11.130m	18.454ms	3	3	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	6.583m	3.814ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	8.091m	5.567ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	6.583m	3.814ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	11.083m	8.835ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	11.083m	8.835ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	8.164m	7.780ms	5	5	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	11.296m	4.391ms	3	3	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	9.244m	6.198ms	3	3	100.00
		chip_sw_aes_idle	3.364m	2.998ms	3	3	100.00
		chip_sw_hmac_enc_idle	4.366m	2.863ms	3	3	100.00
		chip_sw_kmac_idle	5.225m	2.973ms	3	3	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	10.065m	5.121ms	3	3	100.00
		chip_sw_clkmgr_off_hmac_trans	10.883m	5.277ms	3	3	100.00
		chip_sw_clkmgr_off_kmac_trans	8.009m	4.372ms	3	3	100.00
		chip_sw_clkmgr_off_otbn_trans	9.352m	6.132ms	3	3	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	21.317m	12.161ms	3	3	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	10.202m	3.741ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	10.787m	5.354ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.020m	3.964ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	10.710m	5.314ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.421m	3.493ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	10.431m	4.840ms	3	3	100.00
		chip_sw_ast_clk_outputs	16.439m	7.523ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	12.819m	10.137ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.020m	3.964ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	10.710m	5.314ms	3	3	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	16.509m	5.357ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	16.933m	5.412ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	53.580m	18.859ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	4.097m	2.537ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	19.579m	5.478ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	4.923m	3.279ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	6.545m	4.309ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	5.576m	3.430ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	10.527m	4.125ms	3	3	100.00
		chip_sw_clkmgr_jitter	4.548m	2.642ms	3	3	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	4.075m	2.571ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	16.588m	6.722ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	17.442m	8.053ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	53.605m	24.259ms	3	3	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	4.493m	2.995ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	5.125m	2.957ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	8.434m	5.703ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	5.820m	3.496ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	10.726m	4.890ms	3	3	100.00
		chip_sw_flash_init_reduced_freq	32.492m	23.369ms	3	3	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	56.955m	22.791ms	3	3	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	16.439m	7.523ms	3	3	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	10.862m	4.702ms	3	3	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	7.808m	3.655ms	3	3	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	12.318m	5.969ms	97	100	97.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	28.878m	8.871ms	3	3	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	23.878m	8.150ms	3	3	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	10.451m	4.828ms	3	3	100.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	11.712m	7.471ms	3	3	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	3.801m	2.590ms	3	3	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	1.043h	18.146ms	3	3	100.00
		chip_sw_entropy_src_ast_rng_req	4.957m	3.028ms	3	3	100.00
		chip_sw_edn_entropy_reqs	12.797m	4.778ms	3	3	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	4.957m	3.028ms	3	3	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	23.878m	8.150ms	3	3	100.00
V2	chip_sw_entropy_src_fuse_en_fw_read	chip_sw_entropy_src_fuse_en_fw_read_test	11.583m	4.865ms	3	3	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	4.363m	2.672ms	3	3	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	32.647m	16.413ms	3	3	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	17.332m	5.674ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	16.933m	5.412ms	3	3	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	13.887m	5.020ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en	16.509m	5.357ms	3	3	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked			0	3	0.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	32.647m	16.413ms	3	3	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	7.018m	3.240ms	3	3	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	8.295m	4.177ms	3	3	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	9.366m	5.644ms	3	3	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked			0	3	0.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	9.366m	5.644ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	9.366m	5.644ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	9.366m	5.644ms	3	3	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	9.366m	5.644ms	3	3	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	12.318m	5.969ms	97	100	97.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	8.342m	13.250ms	3	3	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	18.849m	5.669ms	3	3	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	9.754m	5.407ms	3	3	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	5.260m	2.486ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	4.923m	3.279ms	3	3	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	4.366m	2.863ms	3	3	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	17.246m	6.005ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx1	13.617m	5.134ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx2	14.340m	5.593ms	3	3	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	10.678m	4.051ms	3	3	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	8.295m	4.177ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	6.545m	4.309ms	3	3	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	9.031m	3.912ms	3	3	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	8.465m	4.239ms	3	3	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	59.718m	16.135ms	3	3	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	5.153m	3.114ms	3	3	100.00
		chip_sw_kmac_mode_kmac	6.784m	3.140ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	5.576m	3.430ms	3	3	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	8.295m	4.177ms	3	3	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	17.469m	9.279ms	15	15	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	4.363m	2.342ms	3	3	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	4.908m	3.395ms	3	3	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	5.225m	2.973ms	3	3	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	9.644m	6.333ms	3	3	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	19.592m	14.593ms	5	5	100.00
		chip_tap_straps_rma	8.822m	6.472ms	5	5	100.00
		chip_tap_straps_prod	21.336m	12.474ms	5	5	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	6.631m	2.986ms	3	3	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	17.469m	9.279ms	15	15	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	17.469m	9.279ms	15	15	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	17.469m	9.279ms	15	15	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	10.076m	4.413ms	3	3	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	9.366m	5.644ms	3	3	100.00
		chip_sw_flash_rma_unlocked			0	3	0.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	11.588m	4.769ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	19.134m	9.283ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	20.466m	7.010ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	18.699m	7.743ms	3	3	100.00
		chip_sw_lc_ctrl_transition	17.469m	9.279ms	15	15	100.00
		chip_sw_keymgr_key_derivation	8.295m	4.177ms	3	3	100.00
		chip_sw_rom_ctrl_integrity_check	11.807m	8.135ms	3	3	100.00
		chip_sw_sram_ctrl_execution_main	10.484m	7.783ms	3	3	100.00
		chip_prim_tl_access	8.342m	13.250ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	12.819m	10.137ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	10.202m	3.741ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	10.787m	5.354ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.020m	3.964ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	10.710m	5.314ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.421m	3.493ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	10.431m	4.840ms	3	3	100.00
		chip_tap_straps_dev	19.592m	14.593ms	5	5	100.00
		chip_tap_straps_rma	8.822m	6.472ms	5	5	100.00
		chip_tap_straps_prod	21.336m	12.474ms	5	5	100.00
		chip_rv_dm_lc_disabled	6.807m	11.683ms	3	3	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.597m	3.027ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	2.260m	3.156ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	2.207m	3.007ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	3.093m	3.250ms	3	3	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	39.014m	34.235ms	3	3	100.00
		chip_rv_dm_lc_disabled	6.807m	11.683ms	3	3	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.391h	46.779ms	1	3	33.33
		chip_sw_lc_walkthrough_prod			0	3	0.00
		chip_sw_lc_walkthrough_prodend	14.125m	10.226ms	3	3	100.00
		chip_sw_lc_walkthrough_rma			0	3	0.00
		chip_sw_lc_walkthrough_testunlocks	39.014m	34.235ms	3	3	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	6.093m	4.305ms	3	3	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	5.001m	3.865ms	3	3	100.00
		rom_volatile_raw_unlock	25.330m	9.939ms	3	3	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	17.469m	9.279ms	15	15	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	32.647m	16.413ms	3	3	100.00
		chip_sw_otbn_mem_scramble	7.347m	4.367ms	3	3	100.00
		chip_sw_keymgr_key_derivation	8.295m	4.177ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	10.089m	4.966ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.249m	2.889ms	3	3	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	32.647m	16.413ms	3	3	100.00
		chip_sw_otbn_mem_scramble	7.347m	4.367ms	3	3	100.00
		chip_sw_keymgr_key_derivation	8.295m	4.177ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	10.089m	4.966ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.249m	2.889ms	3	3	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	17.469m	9.279ms	15	15	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	10.155m	4.437ms	3	3	100.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	6.631m	2.986ms	3	3	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	11.588m	4.769ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	19.134m	9.283ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	20.466m	7.010ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	18.699m	7.743ms	3	3	100.00
		chip_sw_lc_ctrl_transition	17.469m	9.279ms	15	15	100.00
		chip_prim_tl_access	8.342m	13.250ms	3	3	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	8.342m	13.250ms	3	3	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	8.528m	7.689ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	27.971m	25.381ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	7.299m	7.090ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	13.840m	9.629ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_sleep_por_reset			0	0	--
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	22.729m	17.578ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	20.500m	16.285ms	3	3	100.00
		chip_sw_aon_timer_wdog_bite_reset	11.083m	8.835ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	21.757m	13.151ms	3	3	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	9.480m	5.160ms	3	3	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	8.528m	7.689ms	3	3	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	5.963m	3.878ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	51.098m	42.665ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	9.377m	5.534ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	7.583m	4.352ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	34.512m	18.941ms	3	3	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	17.574m	8.154ms	3	3	100.00
		chip_sw_pwrmgr_all_reset_reqs	28.259m	12.767ms	3	3	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	38.994m	22.359ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	4.974m	2.875ms	3	3	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	12.318m	5.969ms	97	100	97.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	11.807m	8.135ms	3	3	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	11.807m	8.135ms	3	3	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	28.259m	12.767ms	3	3	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	34.512m	18.941ms	3	3	100.00
		chip_sw_pwrmgr_wdog_reset	9.480m	5.160ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	8.091m	5.567ms	3	3	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	7.789m	5.124ms	3	3	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	9.018m	6.704ms	3	3	100.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	6.801m	3.973ms	3	3	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	23.777m	13.772ms	3	3	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	3.993m	3.245ms	3	3	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	12.318m	5.969ms	97	100	97.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	24.818m	7.796ms	3	3	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	17.679m	6.089ms	3	3	100.00
		chip_plic_all_irqs_10	10.911m	3.776ms	3	3	100.00
		chip_plic_all_irqs_20	12.483m	4.048ms	3	3	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	5.434m	3.182ms	3	3	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	5.644m	2.890ms	3	3	100.00
V2	chip_sw_spi_device_tx_rx	chip_sw_spi_device_tx_rx	6.463m	3.647ms	3	3	100.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	3.386h	73.019ms	3	3	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	10.675m	6.879ms	3	3	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	11.440m	4.881ms	3	3	100.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	6.589m	3.213ms	3	3	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	4.910m	3.453ms	3	3	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	10.089m	4.966ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	10.527m	4.125ms	3	3	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	11.281m	6.673ms	3	3	100.00
		chip_sw_sleep_sram_ret_contents_scramble	11.547m	7.104ms	3	3	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	10.484m	7.783ms	3	3	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	12.318m	5.969ms	97	100	97.00
		chip_sw_data_integrity_escalation	14.812m	5.451ms	6	6	100.00
V2	chip_sw_usbdev_mem	chip_sw_usbdev_mem			0	0	--
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	3.365m	2.869ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	3.391m	2.633ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup			0	0	--
V2	chip_sw_usbdev_sof	chip_sw_usbdev_sof			0	0	--
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	10.486m	4.008ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host			0	0	--
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.734h	31.638ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	36.787m	11.479ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	5.701m	3.490ms	3	3	100.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	9.644m	6.333ms	3	3	100.00
V2	chip_sw_alert_handler_escalation_nmi_reset	chip_sw_alert_handler_escalation_nmi_reset			0	0	--
V2	chip_sw_alert_handler_escalation_methods	chip_sw_alert_handler_escalation_methods			0	0	--
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	12.318m	5.969ms	97	100	97.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs			0	0	--
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	6.081m	3.135ms	3	3	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	23.777m	13.772ms	3	3	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	6.110m	3.500ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	8.512m	3.804ms	85	90	94.44
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	19.278m	11.870ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	28.878m	8.871ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	24.818m	7.796ms	3	3	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	3.492h	254.809ms	3	3	100.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	41.083m	21.625ms	3	3	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	25.046m	13.782ms	3	3	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	7.789m	5.124ms	3	3	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	7.620m	4.134ms	3	3	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	7.297m	5.962ms	3	3	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	8.822m	6.472ms	5	5	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	6.807m	11.683ms	3	3	100.00
V2	chip_rv_dm_jtag	chip_rv_dm_jtag			0	0	--
V2	chip_rv_dm_dtm	chip_rv_dm_dtm			0	0	--
V2	chip_rv_dm_control_status	chip_rv_dm_control_status			0	0	--
V2		TOTAL			2600	2658	97.82
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	5.585m	2.956ms	3	3	100.00
V2S		TOTAL			3	3	100.00
V3	chip_sw_usb_suspend	chip_sw_usb_suspend			0	0	--
V3	chip_usb_wake_debug	chip_usb_wake_debug			0	0	--
V3	chip_sw_coremark	chip_sw_coremark	2.581h	50.253ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	8.443m	4.805ms	0	3	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	1.810m	2.085ms	0	1	0.00
		rom_e2e_jtag_debug_dev	1.752m	2.609ms	0	1	0.00
		rom_e2e_jtag_debug_rma	1.891m	2.678ms	0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	1.085h	50.867ms	0	1	0.00
		rom_e2e_jtag_inject_dev	54.689m	51.182ms	0	1	0.00
		rom_e2e_jtag_inject_rma	43.892m	51.605ms	0	1	0.00
V3	rom_bootstrap_rma	rom_bootstrap_rma			0	0	--
V3	rom_e2e_weak_straps	rom_e2e_weak_straps			0	0	--
V3	rom_e2e_self_hash	rom_e2e_self_hash	32.627m	9.803ms	0	3	0.00
V3	manuf_cp_unlock_raw	manuf_cp_unlock_raw			0	0	--
V3	manuf_scrap	manuf_scrap			0	0	--
V3	manuf_cp_yield_test	manuf_cp_yield_test			0	0	--
V3	manuf_cp_ast_test_execution	manuf_cp_ast_test_execution			0	0	--
V3	manuf_cp_device_info_flash_wr	manuf_cp_device_info_flash_wr			0	0	--
V3	manuf_cp_test_lock	manuf_cp_test_lock			0	0	--
V3	manuf_ft_exit_token	manuf_ft_exit_token			0	0	--
V3	manuf_ft_sku_individualization_preop	manuf_ft_sku_individualization_preop			0	0	--
V3	manuf_ft_sku_individualization	manuf_ft_sku_individualization			0	0	--
V3	manuf_ft_provision_rma_token_and_personalization	manuf_ft_provision_rma_token_and_personalization			0	0	--
V3	manuf_ft_load_transport_image	manuf_ft_load_transport_image			0	0	--
V3	manuf_ft_load_certificates	manuf_ft_load_certificates			0	0	--
V3	manuf_ft_eom	manuf_ft_eom			0	0	--
V3	manuf_rma_entry	manuf_rma_entry			0	0	--
V3	manuf_sram_program_crc_functest	manuf_sram_program_crc_functest			0	0	--
V3	chip_sw_adc_ctrl_normal	chip_sw_adc_ctrl_normal			0	0	--
V3	chip_sw_adc_ctrl_oneshot	chip_sw_adc_ctrl_oneshot			0	0	--
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	7.763m	3.444ms	3	3	100.00
V3	chip_sw_sysrst_ctrl_combo_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	17.574m	8.154ms	3	3	100.00
		chip_sw_sysrst_ctrl_reset	25.149m	21.157ms	3	3	100.00
V3	chip_sw_sysrst_ctrl_input	chip_sw_sysrst_ctrl_inputs	5.552m	2.757ms	3	3	100.00
V3	chip_sw_sysrst_ctrl_input_interrupt	chip_sw_sysrst_ctrl_in_irq	11.257m	4.857ms	3	3	100.00
V3	chip_sw_sysrst_ctrl_ulp_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	10.209m	6.150ms	3	3	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	10.530m	2.707ms	3	3	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	30.325m	8.197ms	3	3	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	22.073m	6.335ms	3	3	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	10.460m	3.516ms	3	3	100.00
V3	chip_sw_entropy_src_bypass_mode_health_tests	chip_sw_entropy_src_bypass_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_fips_mode_health_tests	chip_sw_entropy_src_fips_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_validation	chip_sw_entropy_src_validation			0	0	--
V3	chip_sw_flash_memory_protection	chip_sw_flash_memory_protection			0	0	--
V3	chip_sw_hmac_sha2_stress	chip_sw_hmac_sha2_stress			0	0	--
V3	chip_sw_hmac_stress	chip_sw_hmac_stress			0	0	--
V3	chip_sw_hmac_endianness	chip_sw_hmac_endianness			0	0	--
V3	chip_sw_hmac_secure_wipe	chip_sw_hmac_secure_wipe			0	0	--
V3	chip_sw_hmac_error_conditions	chip_sw_hmac_error_conditions			0	0	--
V3	chip_sw_i2c_speed	chip_sw_i2c_speed			0	0	--
V3	chip_sw_i2c_override	chip_sw_i2c_override			0	0	--
V3	chip_sw_i2c_clockstretching	chip_sw_i2c_clockstretching			0	0	--
V3	chip_sw_i2c_nack	chip_sw_i2c_nack			0	0	--
V3	chip_sw_i2c_repeatedstart	chip_sw_i2c_repeatedstart			0	0	--
V3	chip_sw_keymgr_sideload_kmac_error	chip_sw_keymgr_sideload_kmac_error			0	0	--
V3	chip_sw_keymgr_derive_attestation	chip_sw_keymgr_derive_attestation			0	0	--
V3	chip_sw_keymgr_derive_sealing	chip_sw_keymgr_derive_sealing			0	0	--
V3	chip_sw_kmac_sha3_stress	chip_sw_kmac_sha3_stress			0	0	--
V3	chip_sw_kmac_shake_stress	chip_sw_kmac_shake_stress			0	0	--
V3	chip_sw_kmac_cshake_stress	chip_sw_kmac_cshake_stress			0	0	--
V3	chip_sw_kmac_kmac_stress	chip_sw_kmac_kmac_stress			0	0	--
V3	chip_sw_kmac_kmac_key_sideload	chip_sw_kmac_kmac_key_sideload			0	0	--
V3	chip_sw_kmac_endianess	chip_sw_kmac_endianess			0	0	--
V3	chip_sw_kmac_entropy_stress	chip_sw_kmac_entropy_stress			0	0	--
V3	chip_sw_kmac_error_conditions	chip_sw_kmac_error_conditions			0	0	--
V3	chip_sw_lc_ctrl_kmac_error	chip_sw_lc_ctrl_kmac_error			0	0	--
V3	chip_sw_lc_ctrl_debug_access	chip_sw_lc_ctrl_debug_access			0	0	--
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	3.544m	3.192ms	3	3	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	14.684m	12.853ms	0	1	0.00
V3	otp_ctrl_calibration	otp_ctrl_calibration			0	0	--
V3	otp_ctrl_partition_access_locked	otp_ctrl_partition_access_locked			0	0	--
V3	otp_ctrl_check_timeout	otp_ctrl_check_timeout			0	0	--
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	6.464m	13.181ms	0	3	0.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	7.546m	4.569ms	3	3	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	28.259m	12.767ms	3	3	100.00
V3	chip_sw_rom_ctrl_kmac_error	chip_sw_rom_ctrl_kmac_error			0	0	--
V3	chip_sw_rom_ctrl_digests	chip_sw_rom_ctrl_digests			0	0	--
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	12.318m	5.969ms	97	100	97.00
V3	tick_configuration	chip_sw_rv_timer_systick_test			0	3	0.00
V3	counter_wrap	chip_sw_rv_timer_systick_test			0	3	0.00
V3	chip_sw_spi_device_pass_through_flash_model	chip_sw_spi_device_pass_through_flash_model			0	0	--
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_output_when_disabled_or_sleeping			0	0	--
V3	chip_sw_spi_host_pass_through	chip_sw_spi_host_pass_through			0	0	--
V3	chip_sw_spi_host_configuration	chip_sw_spi_host_configuration			0	0	--
V3	chip_sw_spi_host_events	chip_sw_spi_host_events			0	0	--
V3	chip_sw_sram_memset	chip_sw_sram_memset			0	0	--
V3	chip_sw_sram_subword_access	chip_sw_sram_subword_access			0	0	--
V3	chip_sw_uart_parity	chip_sw_uart_parity			0	0	--
V3	chip_sw_uart_line_loopback	chip_sw_uart_line_loopback			0	0	--
V3	chip_sw_uart_system_loopback	chip_sw_uart_system_loopback			0	0	--
V3	chip_sw_uart_line_break	chip_sw_uart_line_break			0	0	--
V3	chip_sw_uart_watermarks	chip_sw_uart_watermarks			0	0	--
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	1.050h	18.281ms	1	1	100.00
V3	chip_sw_usbdev_iso	chip_sw_usbdev_iso			0	0	--
V3	chip_sw_usbdev_mixed	chip_sw_usbdev_mixed			0	0	--
V3	chip_sw_usbdev_suspend_resume	chip_sw_usbdev_suspend_resume			0	0	--
V3	chip_sw_usbdev_aon_wake_reset	chip_sw_usbdev_aon_wake_reset			0	0	--
V3	chip_sw_usbdev_aon_wake_disconnect	chip_sw_usbdev_aon_wake_disconnect			0	0	--
V3	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore			0	0	--
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	1.810m	2.085ms	0	1	0.00
		rom_e2e_jtag_debug_dev	1.752m	2.609ms	0	1	0.00
		rom_e2e_jtag_debug_rma	1.891m	2.678ms	0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	10.202m	6.283ms	3	3	100.00
V3		TOTAL			26	45	57.78
	Unmapped tests	chip_sival_flash_info_access	8.896m	3.678ms	3	3	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	10.159m	5.915ms	3	3	100.00
		chip_sw_pwrmgr_normal_sleep_por_reset	12.476m	18.014ms	1	3	33.33
		chip_sw_otbn_ecdsa_op_irq	47.054m	16.989ms	3	3	100.00
		chip_sw_rv_core_ibex_rnd	17.389m	4.912ms	3	3	100.00
		chip_sw_rv_core_ibex_nmi_irq	13.619m	5.150ms	3	3	100.00
		chip_sw_rv_core_ibex_address_translation	5.408m	3.427ms	3	3	100.00
		chip_sw_rv_core_ibex_lockstep_glitch	3.684m	2.576ms	2	3	66.67
		TOTAL			2873	2953	97.29

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	8	8	6	75.00
V1	19	19	19	100.00
V2	290	275	256	88.28
V2S	1	1	1	100.00
V3	92	21	10	10.87

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.69	95.42	94.23	98.00	--	94.87	97.93	99.69

Failure Buckets

Exit reason: Error: User command failed Job returned non-zero exit code has 41 failures:

Test rom_e2e_keymgr_init_rom_ext_meas has 3 failures.

0.rom_e2e_keymgr_init_rom_ext_meas.74786386079676553304310827846895460347183833916425324724563604234389248089971
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_meas/latest/run.log

  (13:47:51) Loading:
  (13:47:52) Loading:
  (13:47:52) Loading: 4 packages loaded
  (13:47:52) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (13:47:52) WARNING: Target pattern parsing failed.
  (13:47:52) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (13:47:52) INFO: Elapsed time: 18.871s
  (13:47:52) INFO: 0 processes.
  (13:47:52) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_keymgr_init_rom_ext_meas.81882035034080015826432352189457506719200445753255639561954488285301453593481
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_meas/latest/run.log

  (13:51:56) Loading:
  (13:51:58) Loading:
  (13:51:58) Loading: 4 packages loaded
  (13:51:58) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (13:51:58) WARNING: Target pattern parsing failed.
  (13:51:58) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (13:51:58) INFO: Elapsed time: 125.515s
  (13:51:58) INFO: 0 processes.
  (13:51:58) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_keymgr_init_rom_ext_no_meas has 3 failures.

0.rom_e2e_keymgr_init_rom_ext_no_meas.11736239727775522166681693914696927943192575323539904827779483028966331468678
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_no_meas/latest/run.log

  (13:47:53) Loading:
  (13:47:53) Loading:
  (13:47:53) Loading: 4 packages loaded
  (13:47:54) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (13:47:54) WARNING: Target pattern parsing failed.
  (13:47:54) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (13:47:54) INFO: Elapsed time: 21.032s
  (13:47:54) INFO: 0 processes.
  (13:47:54) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_keymgr_init_rom_ext_no_meas.80111311234388354882953411065414503051959693005155108952818872245797122415661
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_no_meas/latest/run.log

  (13:49:43) Loading:
  (13:49:44) Loading:
  (13:49:44) Loading: 4 packages loaded
  (13:49:44) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (13:49:44) WARNING: Target pattern parsing failed.
  (13:49:44) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (13:49:44) INFO: Elapsed time: 22.593s
  (13:49:44) INFO: 0 processes.
  (13:49:44) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_keymgr_init_rom_ext_invalid_meas has 3 failures.

0.rom_e2e_keymgr_init_rom_ext_invalid_meas.92676121614186156647897109835193308466146820847441219595228748224034468432251
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest/run.log

  (13:47:58) Loading:
  (13:47:58) Loading:
  (13:47:58) Loading: 4 packages loaded
  (13:47:59) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (13:47:59) WARNING: Target pattern parsing failed.
  (13:47:59) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (13:47:59) INFO: Elapsed time: 19.184s
  (13:47:59) INFO: 0 processes.
  (13:47:59) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_keymgr_init_rom_ext_invalid_meas.78021862315755738263572690222576879755041522077077235128888424862574066988100
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest/run.log

  (13:49:47) Loading:
  (13:49:48) Loading:
  (13:49:48) Loading: 4 packages loaded
  (13:49:48) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (13:49:48) WARNING: Target pattern parsing failed.
  (13:49:48) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (13:49:48) INFO: Elapsed time: 28.583s
  (13:49:48) INFO: 0 processes.
  (13:49:48) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_sigverify_mod_exp_test_unlocked0_otbn has 3 failures.

0.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn.105740040974470566505935175411612872766542772689407187652121326018310819750166
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn/latest/run.log

  (13:48:09) Loading:
  (13:48:09) Loading:
  (13:48:09) Loading: 4 packages loaded
  (13:48:10) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (13:48:10) WARNING: Target pattern parsing failed.
  (13:48:10) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (13:48:10) INFO: Elapsed time: 27.093s
  (13:48:10) INFO: 0 processes.
  (13:48:10) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn.21867625338450231031218527453840522295212981682623876816326392833665745594758
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn/latest/run.log

  (13:49:41) Loading:
  (13:49:41) Loading:
  (13:49:41) Loading: 4 packages loaded
  (13:49:41) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (13:49:41) WARNING: Target pattern parsing failed.
  (13:49:41) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (13:49:41) INFO: Elapsed time: 19.279s
  (13:49:41) INFO: 0 processes.
  (13:49:41) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_sigverify_mod_exp_test_unlocked0_sw has 3 failures.

0.rom_e2e_sigverify_mod_exp_test_unlocked0_sw.51095224285779043930379047757001612281574796697430634649231910599801647693784
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_test_unlocked0_sw/latest/run.log

  (13:48:05) Loading:
  (13:48:06) Loading:
  (13:48:06) Loading: 4 packages loaded
  (13:48:06) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (13:48:06) WARNING: Target pattern parsing failed.
  (13:48:06) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (13:48:06) INFO: Elapsed time: 22.344s
  (13:48:06) INFO: 0 processes.
  (13:48:06) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_sigverify_mod_exp_test_unlocked0_sw.83771948585090615741409226872797741816092359539919261471041307453139881271144
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_test_unlocked0_sw/latest/run.log

  (13:52:34) Loading:
  (13:52:35) Loading:
  (13:52:35) Loading: 4 packages loaded
  (13:52:35) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (13:52:35) WARNING: Target pattern parsing failed.
  (13:52:35) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (13:52:35) INFO: Elapsed time: 140.662s
  (13:52:35) INFO: 0 processes.
  (13:52:35) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

... and 10 more tests.

Job chip_earlgrey_asic-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 16 failures:
- Test chip_sw_flash_rma_unlocked has 3 failures.
  - 0.chip_sw_flash_rma_unlocked.54915362480820105075218014962089228542754149921206542957079037578743882711878
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_rma_unlocked/latest/run.log
```
  Job ID: smart:888bb585-4547-4d9f-a797-97c47e2b84ea
```
  - 1.chip_sw_flash_rma_unlocked.54737721916868880042967851822971890486385105235730225169730854017975838604889
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_rma_unlocked/latest/run.log
```
  Job ID: smart:a7ea83ed-1801-4c0a-9494-8c63d44e15ba
```
  - ... and 1 more failures.
- Test chip_sw_lc_walkthrough_dev has 2 failures.
  - 0.chip_sw_lc_walkthrough_dev.101165161498389785549579497758583556694030569089796482007853217612832261919654
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_dev/latest/run.log
```
  Job ID: smart:f1751d8e-29f5-49ed-a9b1-498a4455a2a5
```
  - 2.chip_sw_lc_walkthrough_dev.102552382619956170012893910462125609999963573607754981168002874690456410854748
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_walkthrough_dev/latest/run.log
```
  Job ID: smart:ac769dad-e70f-41c4-8bd8-0e86c1a569f2
```
- Test chip_sw_lc_walkthrough_prod has 3 failures.
  - 0.chip_sw_lc_walkthrough_prod.24288129209722943328511172757851113620464726581132765409573957080056366285462
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_prod/latest/run.log
```
  Job ID: smart:b9c79381-eb3d-48c2-ade7-f1824f6c900a
```
  - 1.chip_sw_lc_walkthrough_prod.66880830634984919632973853237041692316393748310702727962008303496392579526700
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_prod/latest/run.log
```
  Job ID: smart:e4428792-4ff5-4b1f-bd38-6fd4273e9c95
```
  - ... and 1 more failures.
- Test chip_sw_lc_walkthrough_rma has 3 failures.
  - 0.chip_sw_lc_walkthrough_rma.73739400348965087009261762299009560498184669447520847873924954371629826674390
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_rma/latest/run.log
```
  Job ID: smart:bde5f0a8-9302-4a37-a92c-837755bcf443
```
  - 1.chip_sw_lc_walkthrough_rma.38530353402729268251099675145470528961571594487963622757557317709259159184517
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_rma/latest/run.log
```
  Job ID: smart:2925d809-f8f6-4ea5-8c50-099632c69147
```
  - ... and 1 more failures.
- Test chip_sw_rv_timer_systick_test has 3 failures.
  - 0.chip_sw_rv_timer_systick_test.92534007905868820055422249271819291446442103104206922986095723855889611661322
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job ID: smart:cf9c166e-0be4-46e3-923a-b4aad38b57fe
```
  - 1.chip_sw_rv_timer_systick_test.44111059070094283891962050204686760916917218656275286777114324163890041373642
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job ID: smart:4b085cc2-8d66-49c6-952c-bdce20412a00
```
  - ... and 1 more failures.
- ... and 1 more tests.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=* MEPC=* MTVAL=* has 4 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 4 failures.
  - 52.chip_sw_alert_handler_lpg_sleep_mode_alerts.63787019362991766197276095709916062665442739372104413473272810799674717884861
    Line 751, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/52.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3587.667376 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003a12 MTVAL=40600800
  UVM_INFO @ 3587.667376 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 60.chip_sw_alert_handler_lpg_sleep_mode_alerts.74994578241637593166371259769546297563738033663794439259414859816632368204675
    Line 807, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/60.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 4123.974360 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003a12 MTVAL=40600800
  UVM_INFO @ 4123.974360 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_FATAL @ * us: (chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq.sv:20) [chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq] Timed out waiting for wake up sensor_ctrl sleep has 3 failures:
- Test chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up has 3 failures.
  - 0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.62597045671960507386844696234737017907684861565774011359433387811742892842592
    Line 820, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest/run.log
```
  UVM_FATAL @ 13150.852712 us: (chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq.sv:20) [uvm_test_top.env.virtual_sequencer.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq] Timed out waiting for wake up sensor_ctrl sleep
  UVM_INFO @ 13150.852712 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.67866882624316458140482965806232215376475375510225770644398681089669082189719
    Line 790, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest/run.log
```
  UVM_FATAL @ 13736.790744 us: (chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq.sv:20) [uvm_test_top.env.virtual_sequencer.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq] Timed out waiting for wake up sensor_ctrl sleep
  UVM_INFO @ 13736.790744 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (dv_utils_pkg.sv:270) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat" has 3 failures:
- Test rom_e2e_jtag_debug_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_debug_test_unlocked0.89952881250659811388082613588336239949231445504125113835822830046052292360171
    Line 724, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log
```
  UVM_FATAL @ 2084.780500 us: (dv_utils_pkg.sv:270) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 2084.780500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_dev has 1 failures.
  - 0.rom_e2e_jtag_debug_dev.25787088913484184030437412316717464360720187889450777572242404194860954787230
    Line 730, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log
```
  UVM_FATAL @ 2608.995500 us: (dv_utils_pkg.sv:270) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 2608.995500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_rma has 1 failures.
  - 0.rom_e2e_jtag_debug_rma.77499760078454038174366339640270668936455545484588808442852047770022041633248
    Line 711, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log
```
  UVM_FATAL @ 2677.670000 us: (dv_utils_pkg.sv:270) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 2677.670000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred! has 3 failures:
- Test rom_e2e_jtag_inject_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_inject_test_unlocked0.30837606519667912684404557997131438602181253174974360177714251117581957898754
    Line 785, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_test_unlocked0/latest/run.log
```
  UVM_FATAL @ 50867.447784 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 50867.447784 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_inject_dev has 1 failures.
  - 0.rom_e2e_jtag_inject_dev.100508755527303135802596798862275030372527284867734908112854183520139616920844
    Line 815, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_dev/latest/run.log
```
  UVM_FATAL @ 51181.509143 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 51181.509143 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_inject_rma has 1 failures.
  - 0.rom_e2e_jtag_inject_rma.37430406788930460520576482211339940794372502472645362515976744481234878354455
    Line 769, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_rma/latest/run.log
```
  UVM_FATAL @ 51604.613695 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 51604.613695 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_self_hash_sim_dv(sw/device/silicon_creator/rom/e2e/rom_e2e_self_hash_test.c:80)] CHECK-fail: (uint8_t *)output.dataM hash not self-checked for this device type: *x%xmatches (uint8_t *)kSimDvGoldenRomHash has 3 failures:

Test rom_e2e_self_hash has 3 failures.

0.rom_e2e_self_hash.41452761490647531669146984830497062266199676170913918177336428288216497569567
Line 786, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  UVM_ERROR @ 9802.900032 us: (sw_logger_if.sv:526) [rom_e2e_self_hash_sim_dv(sw/device/silicon_creator/rom/e2e/rom_e2e_self_hash_test.c:80)] CHECK-fail: (uint8_t *)output.dataM hash not self-checked for this device type: 0x%xmatches (uint8_t *)kSimDvGoldenRomHash
  UVM_INFO @ 9802.900032 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.rom_e2e_self_hash.94522823514266446905813478699325908478833624807906114942801532639743946534511
Line 800, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_self_hash/latest/run.log

  UVM_ERROR @ 10008.898656 us: (sw_logger_if.sv:526) [rom_e2e_self_hash_sim_dv(sw/device/silicon_creator/rom/e2e/rom_e2e_self_hash_test.c:80)] CHECK-fail: (uint8_t *)output.dataM hash not self-checked for this device type: 0x%xmatches (uint8_t *)kSimDvGoldenRomHash
  UVM_INFO @ 10008.898656 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:303) virtual_sequencer [chip_sw_sleep_por_reset_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 2 failures:
- Test chip_sw_pwrmgr_normal_sleep_por_reset has 2 failures.
  - 0.chip_sw_pwrmgr_normal_sleep_por_reset.97796868124991769648641808117566855247372503053684616228328263009812968989210
    Line 791, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_normal_sleep_por_reset/latest/run.log
```
  UVM_ERROR @ 18014.252921 us: (chip_sw_base_vseq.sv:303) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_por_reset_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 18014.252921 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 1.chip_sw_pwrmgr_normal_sleep_por_reset.68367247079825486953566375583585446057458872463831249808695990317185937325913
    Line 809, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_normal_sleep_por_reset/latest/run.log
```
  UVM_ERROR @ 16495.628669 us: (chip_sw_base_vseq.sv:303) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_por_reset_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 16495.628669 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_sw_otp_ctrl_escalation_vseq.sv:38) [chip_sw_otp_ctrl_escalation_vseq] Timeout waiting for OTP_CTRL error injection done. has 1 failures:
- Test chip_sw_otp_ctrl_escalation has 1 failures.
  - 0.chip_sw_otp_ctrl_escalation.70514669064157551178548160475955512605882247333884743541766104123887486226150
    Line 778, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_escalation/latest/run.log
```
  UVM_FATAL @ 12852.955024 us: (chip_sw_otp_ctrl_escalation_vseq.sv:38) [uvm_test_top.env.virtual_sequencer.chip_sw_otp_ctrl_escalation_vseq] Timeout waiting for OTP_CTRL error injection done.
  UVM_INFO @ 12852.955024 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(outstanding_load_resp | outstanding_store_resp)' has 1 failures:
- Test chip_sw_rv_core_ibex_lockstep_glitch has 1 failures.
  - 1.chip_sw_rv_core_ibex_lockstep_glitch.50706269851884492598204159090517557062339599247003086016366674699173464794698
    Line 981, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
```
      Offending '(outstanding_load_resp | outstanding_store_resp)'
  UVM_ERROR @ 2576.154380 us: (ibex_core.sv:963) [ASSERT FAILED] NoMemResponseWithoutPendingAccess
  UVM_INFO @ 2576.154380 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:166) [chip_sw_power_virus_vseq] Check failed aes_ctrl_rnd_ctr != *'b* (* [*] vs * [*]) has 1 failures:
- Test chip_sw_power_virus has 1 failures.
  - 2.chip_sw_power_virus.28190354309212469190854316360473976430817800170941134590344228201689509622588
    Line 1085, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 4805.187992 us: (chip_sw_power_virus_vseq.sv:166) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed aes_ctrl_rnd_ctr != 4'b0000 (0 [0x0] vs 0 [0x0])
  UVM_INFO @ 4805.187992 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending 'alert_o' has 1 failures:
- Test chip_sw_all_escalation_resets has 1 failures.
  - 46.chip_sw_all_escalation_resets.91127691665047733828237238415812407185559378991375550322779678696564409243409
    Line 767, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/46.chip_sw_all_escalation_resets/latest/run.log
```
      Offending 'alert_o'
  UVM_ERROR @ 3281.897112 us: (prim_alert_receiver.sv:313) [ASSERT FAILED] Alert_A
  UVM_INFO @ 3281.897112 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected *, got * has 1 failures:
- Test chip_sw_all_escalation_resets has 1 failures.
  - 95.chip_sw_all_escalation_resets.54859757665206712697244539846442473474082843385819991918660492510998625463597
    Line 741, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/95.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 2534.621016 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
  UVM_INFO @ 2534.621016 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```