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LINE 35429
EXPRESSION (addr_hit[566] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T26,T334 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T26 |
LINE 35432
EXPRESSION (addr_hit[567] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T26,T27,T30 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T14,T26,T33 |
LINE 38842
EXPRESSION (reg_busy_sel | shadow_busy)
------1----- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T14,T26,T27 |