| SCORE |
LINE |
COND |
TOGGLE |
FSM |
BRANCH |
ASSERT |
GROUP |
|
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
| 44.48 |
44.48 |
56.72 |
56.72 |
49.84 |
49.84 |
27.38 |
27.38 |
|
|
67.68 |
67.68 |
62.83 |
62.83 |
2.45 |
2.45 |
/workspace/coverage/default/0.chip_plic_all_irqs_20.1656843408 |
| 57.82 |
13.34 |
68.02 |
11.30 |
63.09 |
13.25 |
30.74 |
3.36 |
|
|
79.66 |
11.98 |
90.71 |
27.88 |
14.70 |
12.25 |
/workspace/coverage/default/2.chip_jtag_csr_rw.54161909 |
| 66.79 |
8.97 |
68.17 |
0.15 |
63.37 |
0.29 |
34.78 |
4.04 |
|
|
79.83 |
0.17 |
90.89 |
0.19 |
63.70 |
49.00 |
/workspace/coverage/default/2.chip_sw_alert_test.2914735636 |
| 72.49 |
5.70 |
81.23 |
13.06 |
70.48 |
7.11 |
40.91 |
6.14 |
|
|
83.69 |
3.86 |
90.89 |
0.00 |
67.71 |
4.01 |
/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.2423065653 |
| 76.58 |
4.09 |
81.23 |
0.00 |
70.49 |
0.01 |
65.03 |
24.12 |
|
|
83.70 |
0.01 |
91.08 |
0.19 |
67.93 |
0.22 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.3490784844 |
| 79.38 |
2.80 |
83.53 |
2.30 |
72.89 |
2.40 |
74.50 |
9.46 |
|
|
85.42 |
1.72 |
92.01 |
0.93 |
67.93 |
0.00 |
/workspace/coverage/default/1.rom_raw_unlock.2820489235 |
| 80.97 |
1.59 |
86.17 |
2.64 |
75.23 |
2.34 |
76.33 |
1.83 |
|
|
88.16 |
2.75 |
92.01 |
0.00 |
67.93 |
0.00 |
/workspace/coverage/default/1.chip_plic_all_irqs_0.4026512406 |
| 82.09 |
1.12 |
87.49 |
1.32 |
77.78 |
2.56 |
76.36 |
0.03 |
|
|
90.99 |
2.83 |
92.01 |
0.00 |
67.93 |
0.00 |
/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.2363173371 |
| 82.89 |
0.80 |
87.86 |
0.36 |
77.94 |
0.16 |
76.38 |
0.02 |
|
|
91.16 |
0.16 |
96.10 |
4.09 |
67.93 |
0.00 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.2514808341 |
| 83.67 |
0.78 |
89.08 |
1.23 |
79.13 |
1.18 |
77.99 |
1.61 |
|
|
91.81 |
0.65 |
96.10 |
0.00 |
67.93 |
0.00 |
/workspace/coverage/default/0.chip_jtag_csr_rw.1814575353 |
| 84.43 |
0.75 |
89.91 |
0.83 |
79.85 |
0.72 |
80.25 |
2.26 |
|
|
92.30 |
0.49 |
96.10 |
0.00 |
68.15 |
0.22 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.1290589774 |
| 84.99 |
0.56 |
89.91 |
0.00 |
79.87 |
0.02 |
83.59 |
3.34 |
|
|
92.30 |
0.00 |
96.10 |
0.00 |
68.15 |
0.00 |
/workspace/coverage/default/2.chip_sw_entropy_src_csrng.47257595 |
| 85.35 |
0.36 |
89.91 |
0.00 |
79.87 |
0.00 |
85.75 |
2.16 |
|
|
92.30 |
0.00 |
96.10 |
0.00 |
68.15 |
0.00 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.3708842860 |
| 85.65 |
0.30 |
89.94 |
0.03 |
79.87 |
0.01 |
85.76 |
0.01 |
|
|
92.31 |
0.01 |
96.28 |
0.19 |
69.71 |
1.56 |
/workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.2537917011 |
| 85.94 |
0.29 |
90.40 |
0.46 |
80.41 |
0.54 |
86.25 |
0.49 |
|
|
92.58 |
0.27 |
96.28 |
0.00 |
69.71 |
0.00 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.4278589117 |
| 86.22 |
0.28 |
90.99 |
0.60 |
80.88 |
0.47 |
86.41 |
0.16 |
|
|
93.03 |
0.45 |
96.28 |
0.00 |
69.71 |
0.00 |
/workspace/coverage/default/0.chip_plic_all_irqs_10.2312883883 |
| 86.47 |
0.25 |
91.08 |
0.09 |
80.99 |
0.10 |
87.43 |
1.02 |
|
|
93.10 |
0.07 |
96.28 |
0.00 |
69.93 |
0.22 |
/workspace/coverage/default/25.chip_sw_all_escalation_resets.985105766 |
| 86.69 |
0.22 |
91.29 |
0.21 |
81.28 |
0.29 |
87.47 |
0.03 |
|
|
93.32 |
0.21 |
96.84 |
0.56 |
69.93 |
0.00 |
/workspace/coverage/default/2.chip_sw_sleep_pin_retention.2894533839 |
| 86.87 |
0.18 |
91.57 |
0.28 |
81.41 |
0.14 |
87.65 |
0.18 |
|
|
93.39 |
0.07 |
97.03 |
0.19 |
70.16 |
0.22 |
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.1855807666 |
| 86.98 |
0.11 |
91.57 |
0.00 |
81.41 |
0.00 |
88.32 |
0.67 |
|
|
93.39 |
0.00 |
97.03 |
0.00 |
70.16 |
0.00 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.1160689950 |
| 87.09 |
0.11 |
91.76 |
0.19 |
81.86 |
0.45 |
88.33 |
0.01 |
|
|
93.39 |
0.00 |
97.03 |
0.00 |
70.16 |
0.00 |
/workspace/coverage/default/1.chip_jtag_csr_rw.1723319444 |
| 87.18 |
0.09 |
91.76 |
0.00 |
81.86 |
0.00 |
88.88 |
0.56 |
|
|
93.39 |
0.00 |
97.03 |
0.00 |
70.16 |
0.00 |
/workspace/coverage/default/0.chip_sw_entropy_src_fuse_en_fw_read_test.811389304 |
| 87.27 |
0.09 |
91.77 |
0.01 |
82.11 |
0.25 |
88.88 |
0.00 |
|
|
93.67 |
0.28 |
97.03 |
0.00 |
70.16 |
0.00 |
/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.2113290184 |
| 87.36 |
0.09 |
92.21 |
0.43 |
82.16 |
0.05 |
88.93 |
0.05 |
|
|
93.67 |
0.00 |
97.03 |
0.00 |
70.16 |
0.00 |
/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.1967009976 |
| 87.45 |
0.09 |
92.21 |
0.00 |
82.16 |
0.01 |
89.46 |
0.53 |
|
|
93.67 |
0.00 |
97.03 |
0.00 |
70.16 |
0.00 |
/workspace/coverage/default/91.chip_sw_all_escalation_resets.3009164966 |
| 87.53 |
0.08 |
92.38 |
0.17 |
82.31 |
0.16 |
89.46 |
0.00 |
|
|
93.82 |
0.16 |
97.03 |
0.00 |
70.16 |
0.00 |
/workspace/coverage/default/0.chip_sw_sleep_pin_wake.1882625463 |
| 87.60 |
0.08 |
92.39 |
0.01 |
82.34 |
0.03 |
89.46 |
0.00 |
|
|
93.85 |
0.02 |
97.21 |
0.19 |
70.38 |
0.22 |
/workspace/coverage/default/34.chip_sw_all_escalation_resets.1892548018 |
| 87.68 |
0.07 |
92.39 |
0.01 |
82.35 |
0.01 |
89.47 |
0.02 |
|
|
93.86 |
0.01 |
97.40 |
0.19 |
70.60 |
0.22 |
/workspace/coverage/default/49.chip_sw_all_escalation_resets.2489373807 |
| 87.75 |
0.07 |
92.40 |
0.01 |
82.37 |
0.01 |
89.66 |
0.19 |
|
|
93.86 |
0.01 |
97.40 |
0.00 |
70.82 |
0.22 |
/workspace/coverage/default/67.chip_sw_all_escalation_resets.3662353512 |
| 87.83 |
0.07 |
92.40 |
0.01 |
82.38 |
0.01 |
89.67 |
0.01 |
|
|
93.87 |
0.01 |
97.58 |
0.19 |
71.05 |
0.22 |
/workspace/coverage/default/86.chip_sw_all_escalation_resets.1939192573 |
| 87.89 |
0.06 |
92.42 |
0.01 |
82.55 |
0.17 |
89.67 |
0.00 |
|
|
94.07 |
0.20 |
97.58 |
0.00 |
71.05 |
0.00 |
/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.2114188853 |
| 87.95 |
0.06 |
92.59 |
0.17 |
82.63 |
0.08 |
89.80 |
0.13 |
|
|
94.07 |
0.00 |
97.58 |
0.00 |
71.05 |
0.00 |
/workspace/coverage/default/1.chip_sw_gpio.4289396248 |
| 88.01 |
0.06 |
92.59 |
0.00 |
82.63 |
0.00 |
90.16 |
0.37 |
|
|
94.07 |
0.00 |
97.58 |
0.00 |
71.05 |
0.00 |
/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.2779572181 |
| 88.06 |
0.05 |
92.59 |
0.00 |
82.63 |
0.00 |
90.47 |
0.30 |
|
|
94.07 |
0.00 |
97.58 |
0.00 |
71.05 |
0.00 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.3858785844 |
| 88.11 |
0.05 |
92.59 |
0.00 |
82.63 |
0.00 |
90.54 |
0.07 |
|
|
94.07 |
0.00 |
97.58 |
0.00 |
71.27 |
0.22 |
/workspace/coverage/default/8.chip_sw_all_escalation_resets.2869038157 |
| 88.16 |
0.05 |
92.59 |
0.00 |
82.63 |
0.00 |
90.82 |
0.28 |
|
|
94.07 |
0.00 |
97.58 |
0.00 |
71.27 |
0.00 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.764199947 |
| 88.20 |
0.04 |
92.59 |
0.00 |
82.63 |
0.00 |
90.86 |
0.04 |
|
|
94.07 |
0.00 |
97.58 |
0.00 |
71.49 |
0.22 |
/workspace/coverage/default/36.chip_sw_all_escalation_resets.3606067513 |
| 88.25 |
0.04 |
92.59 |
0.01 |
82.64 |
0.02 |
90.91 |
0.06 |
|
|
94.07 |
0.00 |
97.77 |
0.19 |
71.49 |
0.00 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.1070053252 |
| 88.29 |
0.04 |
92.60 |
0.01 |
82.66 |
0.01 |
90.92 |
0.01 |
|
|
94.08 |
0.01 |
97.77 |
0.00 |
71.71 |
0.22 |
/workspace/coverage/default/5.chip_sw_all_escalation_resets.488497316 |
| 88.33 |
0.04 |
92.60 |
0.00 |
82.66 |
0.00 |
90.94 |
0.02 |
|
|
94.08 |
0.00 |
97.77 |
0.00 |
71.94 |
0.22 |
/workspace/coverage/default/29.chip_sw_all_escalation_resets.1531822721 |
| 88.37 |
0.04 |
92.60 |
0.00 |
82.66 |
0.00 |
90.96 |
0.02 |
|
|
94.08 |
0.00 |
97.77 |
0.00 |
72.16 |
0.22 |
/workspace/coverage/default/13.chip_sw_all_escalation_resets.4229868093 |
| 88.41 |
0.04 |
92.60 |
0.00 |
82.66 |
0.00 |
90.97 |
0.01 |
|
|
94.08 |
0.00 |
97.77 |
0.00 |
72.38 |
0.22 |
/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.1985747257 |
| 88.45 |
0.04 |
92.60 |
0.00 |
82.66 |
0.00 |
90.97 |
0.01 |
|
|
94.08 |
0.00 |
97.77 |
0.00 |
72.61 |
0.22 |
/workspace/coverage/default/57.chip_sw_all_escalation_resets.3431036069 |
| 88.49 |
0.04 |
92.60 |
0.00 |
82.66 |
0.01 |
90.97 |
0.00 |
|
|
94.08 |
0.00 |
97.77 |
0.00 |
72.83 |
0.22 |
/workspace/coverage/default/14.chip_sw_all_escalation_resets.494822137 |
| 88.52 |
0.04 |
92.60 |
0.00 |
82.66 |
0.00 |
90.98 |
0.01 |
|
|
94.08 |
0.00 |
97.77 |
0.00 |
73.05 |
0.22 |
/workspace/coverage/default/59.chip_sw_all_escalation_resets.370222108 |
| 88.56 |
0.04 |
92.60 |
0.00 |
82.66 |
0.00 |
90.98 |
0.01 |
|
|
94.08 |
0.00 |
97.77 |
0.00 |
73.27 |
0.22 |
/workspace/coverage/default/60.chip_sw_all_escalation_resets.2660507103 |
| 88.60 |
0.04 |
92.60 |
0.00 |
82.66 |
0.00 |
90.98 |
0.00 |
|
|
94.08 |
0.00 |
97.77 |
0.00 |
73.50 |
0.22 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.631351280 |
| 88.63 |
0.04 |
92.60 |
0.00 |
82.66 |
0.00 |
90.98 |
0.00 |
|
|
94.08 |
0.00 |
97.77 |
0.00 |
73.72 |
0.22 |
/workspace/coverage/default/0.chip_sw_all_escalation_resets.651627585 |
| 88.67 |
0.04 |
92.60 |
0.00 |
82.66 |
0.00 |
90.98 |
0.00 |
|
|
94.08 |
0.00 |
97.77 |
0.00 |
73.94 |
0.22 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.1138340314 |
| 88.71 |
0.04 |
92.60 |
0.00 |
82.66 |
0.00 |
90.98 |
0.00 |
|
|
94.08 |
0.00 |
97.77 |
0.00 |
74.16 |
0.22 |
/workspace/coverage/default/1.chip_sw_all_escalation_resets.464438470 |
| 88.75 |
0.04 |
92.60 |
0.00 |
82.66 |
0.00 |
90.98 |
0.00 |
|
|
94.08 |
0.00 |
97.77 |
0.00 |
74.39 |
0.22 |
/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.3540455821 |
| 88.78 |
0.04 |
92.60 |
0.00 |
82.66 |
0.00 |
90.98 |
0.00 |
|
|
94.08 |
0.00 |
97.77 |
0.00 |
74.61 |
0.22 |
/workspace/coverage/default/10.chip_sw_all_escalation_resets.1339463706 |
| 88.82 |
0.04 |
92.60 |
0.00 |
82.66 |
0.00 |
90.98 |
0.00 |
|
|
94.08 |
0.00 |
97.77 |
0.00 |
74.83 |
0.22 |
/workspace/coverage/default/11.chip_sw_all_escalation_resets.787762575 |
| 88.86 |
0.04 |
92.60 |
0.00 |
82.66 |
0.00 |
90.98 |
0.00 |
|
|
94.08 |
0.00 |
97.77 |
0.00 |
75.06 |
0.22 |
/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.1248476466 |
| 88.89 |
0.04 |
92.60 |
0.00 |
82.66 |
0.00 |
90.98 |
0.00 |
|
|
94.08 |
0.00 |
97.77 |
0.00 |
75.28 |
0.22 |
/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.959586959 |
| 88.93 |
0.04 |
92.60 |
0.00 |
82.66 |
0.00 |
90.98 |
0.00 |
|
|
94.08 |
0.00 |
97.77 |
0.00 |
75.50 |
0.22 |
/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.1087387921 |
| 88.97 |
0.04 |
92.60 |
0.00 |
82.66 |
0.00 |
90.98 |
0.00 |
|
|
94.08 |
0.00 |
97.77 |
0.00 |
75.72 |
0.22 |
/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.2860561850 |
| 89.01 |
0.04 |
92.60 |
0.00 |
82.66 |
0.00 |
90.98 |
0.00 |
|
|
94.08 |
0.00 |
97.77 |
0.00 |
75.95 |
0.22 |
/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.2600566310 |
| 89.04 |
0.04 |
92.60 |
0.00 |
82.66 |
0.00 |
90.98 |
0.00 |
|
|
94.08 |
0.00 |
97.77 |
0.00 |
76.17 |
0.22 |
/workspace/coverage/default/17.chip_sw_all_escalation_resets.1881859787 |
| 89.08 |
0.04 |
92.60 |
0.00 |
82.66 |
0.00 |
90.98 |
0.00 |
|
|
94.08 |
0.00 |
97.77 |
0.00 |
76.39 |
0.22 |
/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.2131429292 |
| 89.12 |
0.04 |
92.60 |
0.00 |
82.66 |
0.00 |
90.98 |
0.00 |
|
|
94.08 |
0.00 |
97.77 |
0.00 |
76.61 |
0.22 |
/workspace/coverage/default/19.chip_sw_all_escalation_resets.3508000964 |
| 89.15 |
0.04 |
92.60 |
0.00 |
82.66 |
0.00 |
90.98 |
0.00 |
|
|
94.08 |
0.00 |
97.77 |
0.00 |
76.84 |
0.22 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.3166844843 |
| 89.19 |
0.04 |
92.60 |
0.00 |
82.66 |
0.00 |
90.98 |
0.00 |
|
|
94.08 |
0.00 |
97.77 |
0.00 |
77.06 |
0.22 |
/workspace/coverage/default/2.chip_sw_all_escalation_resets.1476496572 |
| 89.23 |
0.04 |
92.60 |
0.00 |
82.66 |
0.00 |
90.98 |
0.00 |
|
|
94.08 |
0.00 |
97.77 |
0.00 |
77.28 |
0.22 |
/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.1137947735 |
| 89.27 |
0.04 |
92.60 |
0.00 |
82.66 |
0.00 |
90.98 |
0.00 |
|
|
94.08 |
0.00 |
97.77 |
0.00 |
77.51 |
0.22 |
/workspace/coverage/default/21.chip_sw_all_escalation_resets.2048393502 |
| 89.30 |
0.04 |
92.60 |
0.00 |
82.66 |
0.00 |
90.98 |
0.00 |
|
|
94.08 |
0.00 |
97.77 |
0.00 |
77.73 |
0.22 |
/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.3197699535 |
| 89.34 |
0.04 |
92.60 |
0.00 |
82.66 |
0.00 |
90.98 |
0.00 |
|
|
94.08 |
0.00 |
97.77 |
0.00 |
77.95 |
0.22 |
/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.2893226690 |
| 89.38 |
0.04 |
92.60 |
0.00 |
82.66 |
0.00 |
90.98 |
0.00 |
|
|
94.08 |
0.00 |
97.77 |
0.00 |
78.17 |
0.22 |
/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.1794985306 |
| 89.41 |
0.04 |
92.60 |
0.00 |
82.66 |
0.00 |
90.98 |
0.00 |
|
|
94.08 |
0.00 |
97.77 |
0.00 |
78.40 |
0.22 |
/workspace/coverage/default/28.chip_sw_all_escalation_resets.54169153 |
| 89.45 |
0.04 |
92.60 |
0.00 |
82.66 |
0.00 |
90.98 |
0.00 |
|
|
94.08 |
0.00 |
97.77 |
0.00 |
78.62 |
0.22 |
/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.1348061361 |
| 89.49 |
0.04 |
92.60 |
0.00 |
82.66 |
0.00 |
90.98 |
0.00 |
|
|
94.08 |
0.00 |
97.77 |
0.00 |
78.84 |
0.22 |
/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.157961599 |
| 89.53 |
0.04 |
92.60 |
0.00 |
82.66 |
0.00 |
90.98 |
0.00 |
|
|
94.08 |
0.00 |
97.77 |
0.00 |
79.06 |
0.22 |
/workspace/coverage/default/30.chip_sw_all_escalation_resets.1154859849 |
| 89.56 |
0.04 |
92.60 |
0.00 |
82.66 |
0.00 |
90.98 |
0.00 |
|
|
94.08 |
0.00 |
97.77 |
0.00 |
79.29 |
0.22 |
/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.1914767572 |
| 89.60 |
0.04 |
92.60 |
0.00 |
82.66 |
0.00 |
90.98 |
0.00 |
|
|
94.08 |
0.00 |
97.77 |
0.00 |
79.51 |
0.22 |
/workspace/coverage/default/32.chip_sw_all_escalation_resets.1111434009 |
| 89.64 |
0.04 |
92.60 |
0.00 |
82.66 |
0.00 |
90.98 |
0.00 |
|
|
94.08 |
0.00 |
97.77 |
0.00 |
79.73 |
0.22 |
/workspace/coverage/default/33.chip_sw_all_escalation_resets.2168454584 |
| 89.67 |
0.04 |
92.60 |
0.00 |
82.66 |
0.00 |
90.98 |
0.00 |
|
|
94.08 |
0.00 |
97.77 |
0.00 |
79.96 |
0.22 |
/workspace/coverage/default/35.chip_sw_all_escalation_resets.2851603563 |
| 89.71 |
0.04 |
92.60 |
0.00 |
82.66 |
0.00 |
90.98 |
0.00 |
|
|
94.08 |
0.00 |
97.77 |
0.00 |
80.18 |
0.22 |
/workspace/coverage/default/37.chip_sw_all_escalation_resets.3105953888 |
| 89.75 |
0.04 |
92.60 |
0.00 |
82.66 |
0.00 |
90.98 |
0.00 |
|
|
94.08 |
0.00 |
97.77 |
0.00 |
80.40 |
0.22 |
/workspace/coverage/default/38.chip_sw_all_escalation_resets.792948552 |
| 89.79 |
0.04 |
92.60 |
0.00 |
82.66 |
0.00 |
90.98 |
0.00 |
|
|
94.08 |
0.00 |
97.77 |
0.00 |
80.62 |
0.22 |
/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.1812014424 |
| 89.82 |
0.04 |
92.60 |
0.00 |
82.66 |
0.00 |
90.98 |
0.00 |
|
|
94.08 |
0.00 |
97.77 |
0.00 |
80.85 |
0.22 |
/workspace/coverage/default/44.chip_sw_all_escalation_resets.1198573827 |
| 89.86 |
0.04 |
92.60 |
0.00 |
82.66 |
0.00 |
90.98 |
0.00 |
|
|
94.08 |
0.00 |
97.77 |
0.00 |
81.07 |
0.22 |
/workspace/coverage/default/48.chip_sw_all_escalation_resets.1164331139 |
| 89.90 |
0.04 |
92.60 |
0.00 |
82.66 |
0.00 |
90.98 |
0.00 |
|
|
94.08 |
0.00 |
97.77 |
0.00 |
81.29 |
0.22 |
/workspace/coverage/default/51.chip_sw_all_escalation_resets.1721159199 |
| 89.93 |
0.04 |
92.60 |
0.00 |
82.66 |
0.00 |
90.98 |
0.00 |
|
|
94.08 |
0.00 |
97.77 |
0.00 |
81.51 |
0.22 |
/workspace/coverage/default/52.chip_sw_all_escalation_resets.2103686615 |
| 89.97 |
0.04 |
92.60 |
0.00 |
82.66 |
0.00 |
90.98 |
0.00 |
|
|
94.08 |
0.00 |
97.77 |
0.00 |
81.74 |
0.22 |
/workspace/coverage/default/53.chip_sw_all_escalation_resets.1442438685 |
| 90.01 |
0.04 |
92.60 |
0.00 |
82.66 |
0.00 |
90.98 |
0.00 |
|
|
94.08 |
0.00 |
97.77 |
0.00 |
81.96 |
0.22 |
/workspace/coverage/default/54.chip_sw_all_escalation_resets.2370328972 |
| 90.04 |
0.04 |
92.60 |
0.00 |
82.66 |
0.00 |
90.98 |
0.00 |
|
|
94.08 |
0.00 |
97.77 |
0.00 |
82.18 |
0.22 |
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.1475591060 |
| 90.08 |
0.04 |
92.60 |
0.00 |
82.66 |
0.00 |
90.98 |
0.00 |
|
|
94.08 |
0.00 |
97.77 |
0.00 |
82.41 |
0.22 |
/workspace/coverage/default/6.chip_sw_all_escalation_resets.2821784919 |
| 90.12 |
0.04 |
92.60 |
0.00 |
82.66 |
0.00 |
90.98 |
0.00 |
|
|
94.08 |
0.00 |
97.77 |
0.00 |
82.63 |
0.22 |
/workspace/coverage/default/61.chip_sw_all_escalation_resets.325879651 |
| 90.16 |
0.04 |
92.60 |
0.00 |
82.66 |
0.00 |
90.98 |
0.00 |
|
|
94.08 |
0.00 |
97.77 |
0.00 |
82.85 |
0.22 |
/workspace/coverage/default/62.chip_sw_all_escalation_resets.3312951175 |
| 90.19 |
0.04 |
92.60 |
0.00 |
82.66 |
0.00 |
90.98 |
0.00 |
|
|
94.08 |
0.00 |
97.77 |
0.00 |
83.07 |
0.22 |
/workspace/coverage/default/70.chip_sw_all_escalation_resets.1293853582 |
| 90.23 |
0.04 |
92.60 |
0.00 |
82.66 |
0.00 |
90.98 |
0.00 |
|
|
94.08 |
0.00 |
97.77 |
0.00 |
83.30 |
0.22 |
/workspace/coverage/default/71.chip_sw_all_escalation_resets.4108211249 |
| 90.27 |
0.04 |
92.60 |
0.00 |
82.66 |
0.00 |
90.98 |
0.00 |
|
|
94.08 |
0.00 |
97.77 |
0.00 |
83.52 |
0.22 |
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.2586293610 |
| 90.30 |
0.04 |
92.60 |
0.00 |
82.66 |
0.00 |
90.98 |
0.00 |
|
|
94.08 |
0.00 |
97.77 |
0.00 |
83.74 |
0.22 |
/workspace/coverage/default/72.chip_sw_all_escalation_resets.791872699 |
| 90.34 |
0.04 |
92.60 |
0.00 |
82.66 |
0.00 |
90.98 |
0.00 |
|
|
94.08 |
0.00 |
97.77 |
0.00 |
83.96 |
0.22 |
/workspace/coverage/default/73.chip_sw_all_escalation_resets.3820009400 |
| 90.38 |
0.04 |
92.60 |
0.00 |
82.66 |
0.00 |
90.98 |
0.00 |
|
|
94.08 |
0.00 |
97.77 |
0.00 |
84.19 |
0.22 |
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.1893028151 |
| 90.42 |
0.04 |
92.60 |
0.00 |
82.66 |
0.00 |
90.98 |
0.00 |
|
|
94.08 |
0.00 |
97.77 |
0.00 |
84.41 |
0.22 |
/workspace/coverage/default/78.chip_sw_all_escalation_resets.1224374170 |
| 90.45 |
0.04 |
92.60 |
0.00 |
82.66 |
0.00 |
90.98 |
0.00 |
|
|
94.08 |
0.00 |
97.77 |
0.00 |
84.63 |
0.22 |
/workspace/coverage/default/87.chip_sw_all_escalation_resets.4213152856 |
| 90.49 |
0.04 |
92.60 |
0.00 |
82.66 |
0.00 |
90.98 |
0.00 |
|
|
94.08 |
0.00 |
97.77 |
0.00 |
84.86 |
0.22 |
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.1968030022 |
| 90.52 |
0.03 |
92.61 |
0.01 |
82.67 |
0.01 |
91.16 |
0.19 |
|
|
94.08 |
0.00 |
97.77 |
0.00 |
84.86 |
0.00 |
/workspace/coverage/default/1.chip_sw_edn_entropy_reqs.2988749098 |
| 90.55 |
0.03 |
92.66 |
0.05 |
82.69 |
0.03 |
91.19 |
0.02 |
|
|
94.14 |
0.07 |
97.77 |
0.00 |
84.86 |
0.00 |
/workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.2114858084 |
| 90.58 |
0.03 |
92.72 |
0.07 |
82.73 |
0.04 |
91.19 |
0.00 |
|
|
94.19 |
0.05 |
97.77 |
0.00 |
84.86 |
0.00 |
/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.1042322016 |
| 90.60 |
0.03 |
92.77 |
0.05 |
82.76 |
0.03 |
91.22 |
0.03 |
|
|
94.23 |
0.04 |
97.77 |
0.00 |
84.86 |
0.00 |
/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.1838656571 |
| 90.63 |
0.02 |
92.77 |
0.00 |
82.91 |
0.15 |
91.22 |
0.00 |
|
|
94.23 |
0.00 |
97.77 |
0.00 |
84.86 |
0.00 |
/workspace/coverage/default/0.chip_plic_all_irqs_0.548496886 |
| 90.65 |
0.02 |
92.82 |
0.05 |
82.98 |
0.07 |
91.23 |
0.01 |
|
|
94.25 |
0.02 |
97.77 |
0.00 |
84.86 |
0.00 |
/workspace/coverage/default/2.chip_sw_sleep_pin_wake.1024531110 |
| 90.67 |
0.02 |
92.90 |
0.07 |
82.98 |
0.00 |
91.29 |
0.06 |
|
|
94.26 |
0.01 |
97.77 |
0.00 |
84.86 |
0.00 |
/workspace/coverage/default/3.chip_tap_straps_rma.3465217006 |
| 90.70 |
0.02 |
92.90 |
0.00 |
82.98 |
0.01 |
91.42 |
0.13 |
|
|
94.26 |
0.00 |
97.77 |
0.00 |
84.86 |
0.00 |
/workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.900208591 |
| 90.72 |
0.02 |
92.90 |
0.00 |
82.98 |
0.00 |
91.54 |
0.12 |
|
|
94.26 |
0.00 |
97.77 |
0.00 |
84.86 |
0.00 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.1776001956 |
| 90.74 |
0.02 |
92.90 |
0.00 |
82.98 |
0.00 |
91.65 |
0.11 |
|
|
94.26 |
0.00 |
97.77 |
0.00 |
84.86 |
0.00 |
/workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1857976231 |
| 90.75 |
0.02 |
92.92 |
0.03 |
82.98 |
0.00 |
91.73 |
0.08 |
|
|
94.26 |
0.00 |
97.77 |
0.00 |
84.86 |
0.00 |
/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.1767381479 |
| 90.77 |
0.02 |
92.93 |
0.01 |
83.00 |
0.02 |
91.79 |
0.05 |
|
|
94.28 |
0.02 |
97.77 |
0.00 |
84.86 |
0.00 |
/workspace/coverage/default/0.chip_sw_usbdev_pincfg.2614073579 |
| 90.79 |
0.02 |
92.93 |
0.00 |
83.09 |
0.09 |
91.79 |
0.00 |
|
|
94.28 |
0.00 |
97.77 |
0.00 |
84.86 |
0.00 |
/workspace/coverage/default/1.chip_plic_all_irqs_20.1794331620 |
| 90.80 |
0.02 |
92.93 |
0.00 |
83.09 |
0.00 |
91.88 |
0.09 |
|
|
94.28 |
0.00 |
97.77 |
0.00 |
84.86 |
0.00 |
/workspace/coverage/default/0.chip_jtag_mem_access.3440348194 |
| 90.81 |
0.01 |
92.97 |
0.04 |
83.13 |
0.04 |
91.88 |
0.00 |
|
|
94.28 |
0.01 |
97.77 |
0.00 |
84.86 |
0.00 |
/workspace/coverage/default/1.chip_sw_sleep_pin_wake.3795847690 |
| 90.83 |
0.01 |
92.97 |
0.00 |
83.20 |
0.08 |
91.88 |
0.00 |
|
|
94.28 |
0.00 |
97.77 |
0.00 |
84.86 |
0.00 |
/workspace/coverage/default/2.chip_plic_all_irqs_0.2373495988 |
| 90.84 |
0.01 |
92.99 |
0.03 |
83.22 |
0.02 |
91.89 |
0.01 |
|
|
94.31 |
0.02 |
97.77 |
0.00 |
84.86 |
0.00 |
/workspace/coverage/default/58.chip_sw_all_escalation_resets.1365177468 |
| 90.85 |
0.01 |
92.99 |
0.00 |
83.22 |
0.00 |
91.95 |
0.07 |
|
|
94.31 |
0.00 |
97.77 |
0.00 |
84.86 |
0.00 |
/workspace/coverage/default/2.chip_sw_edn_boot_mode.1740605258 |
| 90.86 |
0.01 |
92.99 |
0.00 |
83.22 |
0.00 |
92.01 |
0.06 |
|
|
94.31 |
0.00 |
97.77 |
0.00 |
84.86 |
0.00 |
/workspace/coverage/default/2.chip_sw_flash_init.4258488364 |
| 90.87 |
0.01 |
93.02 |
0.03 |
83.24 |
0.01 |
92.01 |
0.00 |
|
|
94.33 |
0.02 |
97.77 |
0.00 |
84.86 |
0.00 |
/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.1197175581 |
| 90.88 |
0.01 |
93.04 |
0.02 |
83.25 |
0.01 |
92.01 |
0.00 |
|
|
94.34 |
0.02 |
97.77 |
0.00 |
84.86 |
0.00 |
/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.1597122942 |
| 90.89 |
0.01 |
93.04 |
0.00 |
83.26 |
0.01 |
92.05 |
0.03 |
|
|
94.34 |
0.00 |
97.77 |
0.00 |
84.86 |
0.00 |
/workspace/coverage/default/0.rom_e2e_shutdown_exception_c.4241523706 |
| 90.89 |
0.01 |
93.04 |
0.00 |
83.26 |
0.00 |
92.09 |
0.04 |
|
|
94.34 |
0.00 |
97.77 |
0.00 |
84.86 |
0.00 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.2479589 |
| 90.90 |
0.01 |
93.07 |
0.03 |
83.26 |
0.01 |
92.09 |
0.01 |
|
|
94.34 |
0.00 |
97.77 |
0.00 |
84.86 |
0.00 |
/workspace/coverage/default/1.chip_sw_spi_device_tpm.1200647538 |
| 90.90 |
0.01 |
93.07 |
0.00 |
83.26 |
0.00 |
92.13 |
0.03 |
|
|
94.34 |
0.00 |
97.77 |
0.00 |
84.86 |
0.00 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3001346990 |
| 90.91 |
0.01 |
93.07 |
0.00 |
83.29 |
0.03 |
92.13 |
0.00 |
|
|
94.34 |
0.00 |
97.77 |
0.00 |
84.86 |
0.00 |
/workspace/coverage/default/1.chip_sival_flash_info_access.3614912743 |
| 90.92 |
0.01 |
93.07 |
0.00 |
83.30 |
0.01 |
92.15 |
0.03 |
|
|
94.34 |
0.00 |
97.77 |
0.00 |
84.86 |
0.00 |
/workspace/coverage/default/2.chip_sw_rstmgr_alert_info.1086468258 |
| 90.92 |
0.01 |
93.08 |
0.01 |
83.30 |
0.01 |
92.17 |
0.01 |
|
|
94.34 |
0.00 |
97.77 |
0.00 |
84.86 |
0.00 |
/workspace/coverage/default/1.chip_sw_power_sleep_load.426120298 |
| 90.92 |
0.01 |
93.09 |
0.01 |
83.32 |
0.01 |
92.17 |
0.01 |
|
|
94.35 |
0.01 |
97.77 |
0.00 |
84.86 |
0.00 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.246567957 |
| 90.93 |
0.01 |
93.09 |
0.00 |
83.34 |
0.03 |
92.17 |
0.00 |
|
|
94.35 |
0.00 |
97.77 |
0.00 |
84.86 |
0.00 |
/workspace/coverage/default/1.chip_plic_all_irqs_10.1397376255 |
| 90.93 |
0.01 |
93.09 |
0.00 |
83.34 |
0.00 |
92.19 |
0.02 |
|
|
94.35 |
0.00 |
97.77 |
0.00 |
84.86 |
0.00 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.3042829232 |
| 90.94 |
0.01 |
93.09 |
0.00 |
83.36 |
0.01 |
92.20 |
0.01 |
|
|
94.35 |
0.00 |
97.77 |
0.00 |
84.86 |
0.00 |
/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.2930180537 |
| 90.94 |
0.01 |
93.09 |
0.00 |
83.37 |
0.01 |
92.21 |
0.01 |
|
|
94.35 |
0.00 |
97.77 |
0.00 |
84.86 |
0.00 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.447597823 |
| 90.94 |
0.01 |
93.09 |
0.01 |
83.38 |
0.01 |
92.21 |
0.01 |
|
|
94.35 |
0.00 |
97.77 |
0.00 |
84.86 |
0.00 |
/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.172421363 |
| 90.95 |
0.01 |
93.09 |
0.00 |
83.38 |
0.00 |
92.23 |
0.02 |
|
|
94.35 |
0.00 |
97.77 |
0.00 |
84.86 |
0.00 |
/workspace/coverage/default/0.chip_sw_kmac_app_rom.1891490941 |
| 90.95 |
0.01 |
93.09 |
0.00 |
83.38 |
0.00 |
92.24 |
0.01 |
|
|
94.36 |
0.01 |
97.77 |
0.00 |
84.86 |
0.00 |
/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.3446023170 |
| 90.95 |
0.01 |
93.09 |
0.00 |
83.38 |
0.00 |
92.26 |
0.02 |
|
|
94.36 |
0.00 |
97.77 |
0.00 |
84.86 |
0.00 |
/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.2167987240 |
| 90.95 |
0.01 |
93.09 |
0.00 |
83.39 |
0.01 |
92.26 |
0.01 |
|
|
94.36 |
0.00 |
97.77 |
0.00 |
84.86 |
0.00 |
/workspace/coverage/default/0.chip_sw_hmac_enc.2762579191 |
| 90.96 |
0.01 |
93.10 |
0.01 |
83.40 |
0.01 |
92.27 |
0.01 |
|
|
94.36 |
0.00 |
97.77 |
0.00 |
84.86 |
0.00 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.2856211597 |
| 90.96 |
0.01 |
93.11 |
0.01 |
83.40 |
0.01 |
92.27 |
0.01 |
|
|
94.36 |
0.00 |
97.77 |
0.00 |
84.86 |
0.00 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.858652242 |
| 90.96 |
0.01 |
93.11 |
0.00 |
83.40 |
0.00 |
92.29 |
0.01 |
|
|
94.36 |
0.00 |
97.77 |
0.00 |
84.86 |
0.00 |
/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.4100579794 |
| 90.97 |
0.01 |
93.11 |
0.00 |
83.40 |
0.00 |
92.30 |
0.01 |
|
|
94.36 |
0.00 |
97.77 |
0.00 |
84.86 |
0.00 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.3291548569 |
| 90.97 |
0.01 |
93.11 |
0.00 |
83.40 |
0.00 |
92.32 |
0.01 |
|
|
94.36 |
0.00 |
97.77 |
0.00 |
84.86 |
0.00 |
/workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.1128173027 |
| 90.97 |
0.01 |
93.11 |
0.00 |
83.41 |
0.01 |
92.32 |
0.00 |
|
|
94.36 |
0.00 |
97.77 |
0.00 |
84.86 |
0.00 |
/workspace/coverage/default/2.chip_plic_all_irqs_10.2088617264 |
| 90.97 |
0.01 |
93.11 |
0.00 |
83.43 |
0.01 |
92.32 |
0.00 |
|
|
94.36 |
0.00 |
97.77 |
0.00 |
84.86 |
0.00 |
/workspace/coverage/default/2.chip_plic_all_irqs_20.3517430689 |
| 90.97 |
0.01 |
93.11 |
0.01 |
83.43 |
0.00 |
92.32 |
0.01 |
|
|
94.36 |
0.00 |
97.77 |
0.00 |
84.86 |
0.00 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.1557022603 |
| 90.98 |
0.01 |
93.12 |
0.01 |
83.43 |
0.00 |
92.33 |
0.01 |
|
|
94.36 |
0.00 |
97.77 |
0.00 |
84.86 |
0.00 |
/workspace/coverage/default/2.chip_sw_pattgen_ios.98590801 |
| 90.98 |
0.01 |
93.12 |
0.01 |
83.43 |
0.00 |
92.33 |
0.01 |
|
|
94.36 |
0.00 |
97.77 |
0.00 |
84.86 |
0.00 |
/workspace/coverage/default/0.chip_tap_straps_rma.2065208980 |
| 90.98 |
0.01 |
93.12 |
0.00 |
83.43 |
0.00 |
92.34 |
0.01 |
|
|
94.36 |
0.00 |
97.77 |
0.00 |
84.86 |
0.00 |
/workspace/coverage/default/0.chip_sw_ast_clk_outputs.1283287388 |
| 90.98 |
0.01 |
93.12 |
0.00 |
83.43 |
0.00 |
92.35 |
0.01 |
|
|
94.36 |
0.00 |
97.77 |
0.00 |
84.86 |
0.00 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.29211124 |
| 90.98 |
0.01 |
93.12 |
0.00 |
83.43 |
0.00 |
92.36 |
0.01 |
|
|
94.36 |
0.00 |
97.77 |
0.00 |
84.86 |
0.00 |
/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.1771894585 |
| 90.98 |
0.01 |
93.12 |
0.00 |
83.43 |
0.00 |
92.37 |
0.01 |
|
|
94.36 |
0.00 |
97.77 |
0.00 |
84.86 |
0.00 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.4013670091 |
| 90.99 |
0.01 |
93.12 |
0.00 |
83.43 |
0.00 |
92.38 |
0.01 |
|
|
94.36 |
0.00 |
97.77 |
0.00 |
84.86 |
0.00 |
/workspace/coverage/default/0.rom_keymgr_functest.758997835 |
| 90.99 |
0.01 |
93.12 |
0.00 |
83.43 |
0.00 |
92.39 |
0.01 |
|
|
94.36 |
0.00 |
97.77 |
0.00 |
84.86 |
0.00 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.315330004 |
| 90.99 |
0.01 |
93.12 |
0.00 |
83.43 |
0.01 |
92.40 |
0.01 |
|
|
94.36 |
0.00 |
97.77 |
0.00 |
84.86 |
0.00 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2166077022 |
| 90.99 |
0.01 |
93.12 |
0.00 |
83.43 |
0.00 |
92.40 |
0.00 |
|
|
94.37 |
0.01 |
97.77 |
0.00 |
84.86 |
0.00 |
/workspace/coverage/default/1.chip_tap_straps_dev.2483339672 |
| 90.99 |
0.01 |
93.12 |
0.00 |
83.43 |
0.00 |
92.41 |
0.01 |
|
|
94.37 |
0.00 |
97.77 |
0.00 |
84.86 |
0.00 |
/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1486817893 |
| 90.99 |
0.01 |
93.12 |
0.00 |
83.43 |
0.00 |
92.41 |
0.01 |
|
|
94.37 |
0.00 |
97.77 |
0.00 |
84.86 |
0.00 |
/workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.3437740614 |
| 90.99 |
0.01 |
93.12 |
0.00 |
83.44 |
0.01 |
92.41 |
0.00 |
|
|
94.37 |
0.00 |
97.77 |
0.00 |
84.86 |
0.00 |
/workspace/coverage/default/0.chip_sw_entropy_src_csrng.1269251966 |
| 91.00 |
0.01 |
93.12 |
0.00 |
83.45 |
0.01 |
92.41 |
0.00 |
|
|
94.37 |
0.00 |
97.77 |
0.00 |
84.86 |
0.00 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1496782009 |
| 91.00 |
0.01 |
93.13 |
0.01 |
83.45 |
0.00 |
92.41 |
0.00 |
|
|
94.37 |
0.00 |
97.77 |
0.00 |
84.86 |
0.00 |
/workspace/coverage/default/0.chip_sw_plic_sw_irq.2050051141 |
| 91.00 |
0.01 |
93.13 |
0.01 |
83.45 |
0.00 |
92.42 |
0.01 |
|
|
94.37 |
0.00 |
97.77 |
0.00 |
84.86 |
0.00 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.4099024188 |
| 91.00 |
0.01 |
93.13 |
0.00 |
83.45 |
0.00 |
92.42 |
0.01 |
|
|
94.37 |
0.00 |
97.77 |
0.00 |
84.86 |
0.00 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation.3372339865 |
| 91.00 |
0.01 |
93.13 |
0.00 |
83.45 |
0.00 |
92.43 |
0.01 |
|
|
94.37 |
0.00 |
97.77 |
0.00 |
84.86 |
0.00 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.3704236410 |
| 91.00 |
0.01 |
93.13 |
0.00 |
83.45 |
0.00 |
92.43 |
0.01 |
|
|
94.37 |
0.00 |
97.77 |
0.00 |
84.86 |
0.00 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1454274074 |
| 91.00 |
0.01 |
93.13 |
0.00 |
83.45 |
0.01 |
92.43 |
0.00 |
|
|
94.37 |
0.00 |
97.77 |
0.00 |
84.86 |
0.00 |
/workspace/coverage/default/0.chip_sival_flash_info_access.723770702 |
| 91.00 |
0.01 |
93.13 |
0.00 |
83.45 |
0.01 |
92.43 |
0.00 |
|
|
94.37 |
0.00 |
97.77 |
0.00 |
84.86 |
0.00 |
/workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.4064319431 |
| 91.00 |
0.01 |
93.13 |
0.00 |
83.46 |
0.01 |
92.43 |
0.00 |
|
|
94.37 |
0.00 |
97.77 |
0.00 |
84.86 |
0.00 |
/workspace/coverage/default/0.chip_sw_gpio.2693564743 |
| 91.00 |
0.01 |
93.13 |
0.00 |
83.46 |
0.01 |
92.43 |
0.00 |
|
|
94.37 |
0.00 |
97.77 |
0.00 |
84.86 |
0.00 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.937789416 |
| 91.00 |
0.01 |
93.13 |
0.00 |
83.46 |
0.01 |
92.43 |
0.00 |
|
|
94.37 |
0.00 |
97.77 |
0.00 |
84.86 |
0.00 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.539483519 |
| 91.00 |
0.01 |
93.13 |
0.00 |
83.46 |
0.00 |
92.43 |
0.01 |
|
|
94.37 |
0.00 |
97.77 |
0.00 |
84.86 |
0.00 |
/workspace/coverage/default/0.chip_sw_edn_auto_mode.1376534769 |
| 91.00 |
0.01 |
93.13 |
0.00 |
83.46 |
0.00 |
92.43 |
0.01 |
|
|
94.37 |
0.00 |
97.77 |
0.00 |
84.86 |
0.00 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.580630619 |
| 91.00 |
0.01 |
93.13 |
0.00 |
83.46 |
0.00 |
92.44 |
0.01 |
|
|
94.37 |
0.00 |
97.77 |
0.00 |
84.86 |
0.00 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.304583205 |
| 91.00 |
0.01 |
93.13 |
0.00 |
83.46 |
0.00 |
92.44 |
0.01 |
|
|
94.37 |
0.00 |
97.77 |
0.00 |
84.86 |
0.00 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.2910624924 |
| 91.01 |
0.01 |
93.13 |
0.00 |
83.46 |
0.00 |
92.44 |
0.01 |
|
|
94.37 |
0.00 |
97.77 |
0.00 |
84.86 |
0.00 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.3878838178 |
| Name |
| /workspace/coverage/default/0.chip_sw_aes_enc.4221605581 |
| /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.2840330641 |
| /workspace/coverage/default/0.chip_sw_aes_entropy.85306404 |
| /workspace/coverage/default/0.chip_sw_aes_idle.1518944108 |
| /workspace/coverage/default/0.chip_sw_aes_masking_off.4181673861 |
| /workspace/coverage/default/0.chip_sw_aes_smoketest.3309837716 |
| /workspace/coverage/default/0.chip_sw_alert_handler_entropy.1411757529 |
| /workspace/coverage/default/0.chip_sw_alert_handler_escalation.123060813 |
| /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.188263009 |
| /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.4065381672 |
| /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.1250002914 |
| /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2845111406 |
| /workspace/coverage/default/0.chip_sw_alert_test.4010028825 |
| /workspace/coverage/default/0.chip_sw_aon_timer_irq.497394495 |
| /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.486074435 |
| /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.421830869 |
| /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.824342819 |
| /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.1517760991 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.261842435 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.4154872697 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3746632250 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1018497983 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.408203887 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2566899180 |
| /workspace/coverage/default/0.chip_sw_clkmgr_jitter.3760673547 |
| /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.1766938955 |
| /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.3394133877 |
| /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.478054560 |
| /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.1250790381 |
| /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.2882080677 |
| /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.946809797 |
| /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.3168825615 |
| /workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.4210594768 |
| /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.763699192 |
| /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.1223043340 |
| /workspace/coverage/default/0.chip_sw_coremark.3477271210 |
| /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.97642614 |
| /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.1832043527 |
| /workspace/coverage/default/0.chip_sw_csrng_kat_test.1409132677 |
| /workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.3730473959 |
| /workspace/coverage/default/0.chip_sw_csrng_smoketest.3237755451 |
| /workspace/coverage/default/0.chip_sw_data_integrity_escalation.4113182364 |
| /workspace/coverage/default/0.chip_sw_edn_boot_mode.597450981 |
| /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.3536742793 |
| /workspace/coverage/default/0.chip_sw_edn_kat.2085998364 |
| /workspace/coverage/default/0.chip_sw_edn_sw_mode.3089211025 |
| /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.3113153926 |
| /workspace/coverage/default/0.chip_sw_entropy_src_kat_test.4008951540 |
| /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.2050171766 |
| /workspace/coverage/default/0.chip_sw_example_concurrency.1686784320 |
| /workspace/coverage/default/0.chip_sw_example_flash.48887853 |
| /workspace/coverage/default/0.chip_sw_example_manufacturer.2700017884 |
| /workspace/coverage/default/0.chip_sw_example_rom.788228267 |
| /workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.3539734860 |
| /workspace/coverage/default/0.chip_sw_flash_crash_alert.2008113193 |
| /workspace/coverage/default/0.chip_sw_flash_ctrl_access.3774006927 |
| /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.3490580411 |
| /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.820690476 |
| /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.2077046828 |
| /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.1301571824 |
| /workspace/coverage/default/0.chip_sw_flash_ctrl_ops.2320870142 |
| /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.4057906390 |
| /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1317130398 |
| /workspace/coverage/default/0.chip_sw_flash_init.2160960645 |
| /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.1073781127 |
| /workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.3124555810 |
| /workspace/coverage/default/0.chip_sw_gpio_smoketest.2932791808 |
| /workspace/coverage/default/0.chip_sw_hmac_enc_idle.1995050170 |
| /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.1686551441 |
| /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.627456215 |
| /workspace/coverage/default/0.chip_sw_hmac_smoketest.532393805 |
| /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.1189643173 |
| /workspace/coverage/default/0.chip_sw_inject_scramble_seed.1047781781 |
| /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.1821339633 |
| /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3484064119 |
| /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.3926080239 |
| /workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.2003706274 |
| /workspace/coverage/default/0.chip_sw_kmac_entropy.502464494 |
| /workspace/coverage/default/0.chip_sw_kmac_idle.95284148 |
| /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.3863397205 |
| /workspace/coverage/default/0.chip_sw_kmac_mode_kmac.709798426 |
| /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.3162395871 |
| /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1622285816 |
| /workspace/coverage/default/0.chip_sw_kmac_smoketest.1711193015 |
| /workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg.3285257040 |
| /workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.3088128181 |
| /workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.2931667546 |
| /workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.1938043292 |
| /workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.3955476481 |
| /workspace/coverage/default/0.chip_sw_lc_ctrl_transition.1678038547 |
| /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.2350936130 |
| /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.741704910 |
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| /workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.1937889568 |
| /workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.3011979706 |
| /workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.1561939331 |
| /workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.3187022259 |
| /workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.4121224457 |
| /workspace/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.2728354712 |
| /workspace/coverage/default/2.chip_sw_rv_plic_smoketest.3933366986 |
| /workspace/coverage/default/2.chip_sw_rv_timer_irq.2669289797 |
| /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.1177479824 |
| /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.2720363746 |
| /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.2397893859 |
| /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.3607307036 |
| /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.1679008657 |
| /workspace/coverage/default/2.chip_sw_spi_device_pass_through.2631721663 |
| /workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.1101098472 |
| /workspace/coverage/default/2.chip_sw_spi_device_tpm.1549273144 |
| /workspace/coverage/default/2.chip_sw_spi_device_tx_rx.420687754 |
| /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.3078063009 |
| /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.1571465420 |
| /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.928728397 |
| /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2777446902 |
| /workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.449070675 |
| /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.2666879824 |
| /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.3590529429 |
| /workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.3743271169 |
| /workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.2196365945 |
| /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.2359278299 |
| /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1729113114 |
| /workspace/coverage/default/2.chip_sw_uart_rand_baudrate.3901437575 |
| /workspace/coverage/default/2.chip_sw_uart_smoketest.4100087026 |
| /workspace/coverage/default/2.chip_sw_uart_smoketest_signed.1605815924 |
| /workspace/coverage/default/2.chip_sw_uart_tx_rx.2721182731 |
| /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.2300729451 |
| /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1078529726 |
| /workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.963048155 |
| /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.1427015961 |
| /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.2418040873 |
| /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.3681081650 |
| /workspace/coverage/default/2.chip_tap_straps_dev.2296776517 |
| /workspace/coverage/default/2.chip_tap_straps_prod.3797563186 |
| /workspace/coverage/default/2.chip_tap_straps_rma.1678273927 |
| /workspace/coverage/default/2.chip_tap_straps_testunlock0.2623989594 |
| /workspace/coverage/default/2.rom_e2e_asm_init_dev.3238833057 |
| /workspace/coverage/default/2.rom_e2e_asm_init_prod.3885048145 |
| /workspace/coverage/default/2.rom_e2e_asm_init_prod_end.2972337002 |
| /workspace/coverage/default/2.rom_e2e_asm_init_rma.2347843124 |
| /workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.3576852443 |
| /workspace/coverage/default/2.rom_e2e_shutdown_exception_c.198705514 |
| /workspace/coverage/default/2.rom_e2e_shutdown_output.1832706714 |
| /workspace/coverage/default/2.rom_e2e_smoke.910019307 |
| /workspace/coverage/default/2.rom_e2e_static_critical.3765455632 |
| /workspace/coverage/default/2.rom_keymgr_functest.2499448616 |
| /workspace/coverage/default/2.rom_raw_unlock.3328400554 |
| /workspace/coverage/default/2.rom_volatile_raw_unlock.1160511295 |
| /workspace/coverage/default/20.chip_sw_all_escalation_resets.129387876 |
| /workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.1953968681 |
| /workspace/coverage/default/22.chip_sw_all_escalation_resets.1984842853 |
| /workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.1920576350 |
| /workspace/coverage/default/23.chip_sw_all_escalation_resets.142652709 |
| /workspace/coverage/default/24.chip_sw_all_escalation_resets.1888268256 |
| /workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.1209419460 |
| /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.1020635889 |
| /workspace/coverage/default/26.chip_sw_all_escalation_resets.1604442708 |
| /workspace/coverage/default/27.chip_sw_all_escalation_resets.334589018 |
| /workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.3680528929 |
| /workspace/coverage/default/3.chip_sw_all_escalation_resets.3291426216 |
| /workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.1462624291 |
| /workspace/coverage/default/3.chip_sw_data_integrity_escalation.1773995697 |
| /workspace/coverage/default/3.chip_sw_lc_ctrl_transition.809565028 |
| /workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.2332846613 |
| /workspace/coverage/default/3.chip_sw_uart_rand_baudrate.2784198782 |
| /workspace/coverage/default/3.chip_sw_uart_tx_rx.4257974392 |
| /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.362180680 |
| /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1749115248 |
| /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.182635477 |
| /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.2698389936 |
| /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.122951587 |
| /workspace/coverage/default/3.chip_tap_straps_dev.782126150 |
| /workspace/coverage/default/3.chip_tap_straps_prod.2790059015 |
| /workspace/coverage/default/3.chip_tap_straps_testunlock0.3397866698 |
| /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.1007055180 |
| /workspace/coverage/default/31.chip_sw_all_escalation_resets.478608997 |
| /workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.4284169188 |
| /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.2455493045 |
| /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.2427438212 |
| /workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.1696384847 |
| /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.1180319077 |
| /workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.3149525158 |
| /workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.2553057687 |
| /workspace/coverage/default/39.chip_sw_all_escalation_resets.1938268625 |
| /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.614600972 |
| /workspace/coverage/default/4.chip_sw_all_escalation_resets.337853010 |
| /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.3529008888 |
| /workspace/coverage/default/4.chip_sw_data_integrity_escalation.2857608621 |
| /workspace/coverage/default/4.chip_sw_lc_ctrl_transition.3452613622 |
| /workspace/coverage/default/4.chip_sw_uart_tx_rx.2363018855 |
| /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.2140063892 |
| /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2233419659 |
| /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.416366390 |
| /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.4139117935 |
| /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.1880440138 |
| /workspace/coverage/default/4.chip_tap_straps_dev.56844191 |
| /workspace/coverage/default/4.chip_tap_straps_prod.1332480950 |
| /workspace/coverage/default/4.chip_tap_straps_rma.1462223463 |
| /workspace/coverage/default/4.chip_tap_straps_testunlock0.75963583 |
| /workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.475471537 |
| /workspace/coverage/default/40.chip_sw_all_escalation_resets.2593756175 |
| /workspace/coverage/default/41.chip_sw_all_escalation_resets.2549355343 |
| /workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.3401929644 |
| /workspace/coverage/default/42.chip_sw_all_escalation_resets.3827387635 |
| /workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.2802327982 |
| /workspace/coverage/default/43.chip_sw_all_escalation_resets.2924364607 |
| /workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.1972350534 |
| /workspace/coverage/default/45.chip_sw_all_escalation_resets.2975862950 |
| /workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.4214921824 |
| /workspace/coverage/default/46.chip_sw_all_escalation_resets.2175439326 |
| /workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.1814785812 |
| /workspace/coverage/default/47.chip_sw_all_escalation_resets.1417537259 |
| /workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.1380285627 |
| /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.423486440 |
| /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.2944290130 |
| /workspace/coverage/default/5.chip_sw_data_integrity_escalation.3861872252 |
| /workspace/coverage/default/5.chip_sw_lc_ctrl_transition.964921006 |
| /workspace/coverage/default/5.chip_sw_uart_rand_baudrate.3747940282 |
| /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.2653611645 |
| /workspace/coverage/default/50.chip_sw_all_escalation_resets.3888983062 |
| /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.981879890 |
| /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.2521053547 |
| /workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.3334041966 |
| /workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.2293627481 |
| /workspace/coverage/default/55.chip_sw_all_escalation_resets.2482932990 |
| /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.3048853013 |
| /workspace/coverage/default/56.chip_sw_all_escalation_resets.1144086175 |
| /workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.2789242605 |
| /workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.732069470 |
| /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.200210082 |
| /workspace/coverage/default/6.chip_sw_lc_ctrl_transition.3426268445 |
| /workspace/coverage/default/6.chip_sw_uart_rand_baudrate.2859834114 |
| /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.3312328692 |
| /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.1552870994 |
| /workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.1714398435 |
| /workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.673039920 |
| /workspace/coverage/default/63.chip_sw_all_escalation_resets.496661584 |
| /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.2596911470 |
| /workspace/coverage/default/64.chip_sw_all_escalation_resets.3139749576 |
| /workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.1901307205 |
| /workspace/coverage/default/65.chip_sw_all_escalation_resets.4252366397 |
| /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.4007619243 |
| /workspace/coverage/default/66.chip_sw_all_escalation_resets.3534940777 |
| /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.3935988756 |
| /workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.3097697169 |
| /workspace/coverage/default/68.chip_sw_all_escalation_resets.270760131 |
| /workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.2542304589 |
| /workspace/coverage/default/69.chip_sw_all_escalation_resets.2111637271 |
| /workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.3122021072 |
| /workspace/coverage/default/7.chip_sw_all_escalation_resets.3100776816 |
| /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.3817250641 |
| /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.530791163 |
| /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.1255674256 |
| /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.2390028226 |
| /workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.1129330316 |
| /workspace/coverage/default/74.chip_sw_all_escalation_resets.2207584639 |
| /workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.2757573421 |
| /workspace/coverage/default/75.chip_sw_all_escalation_resets.664551218 |
| /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.4080260942 |
| /workspace/coverage/default/76.chip_sw_all_escalation_resets.3530006000 |
| /workspace/coverage/default/77.chip_sw_all_escalation_resets.127088620 |
| /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.1424309851 |
| /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.3489371694 |
| /workspace/coverage/default/79.chip_sw_all_escalation_resets.1529968112 |
| /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.1049277930 |
| /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.579674128 |
| /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.1209464480 |
| /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.3312499290 |
| /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.485317313 |
| /workspace/coverage/default/81.chip_sw_all_escalation_resets.2261960994 |
| /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.972253202 |
| /workspace/coverage/default/82.chip_sw_all_escalation_resets.2857417189 |
| /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.712928279 |
| /workspace/coverage/default/83.chip_sw_all_escalation_resets.1129646071 |
| /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.895490452 |
| /workspace/coverage/default/84.chip_sw_all_escalation_resets.3715910624 |
| /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.3538529327 |
| /workspace/coverage/default/85.chip_sw_all_escalation_resets.2828799600 |
| /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.2686003411 |
| /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.1707478062 |
| /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.1578948911 |
| /workspace/coverage/default/88.chip_sw_all_escalation_resets.1417461017 |
| /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.2971563147 |
| /workspace/coverage/default/89.chip_sw_all_escalation_resets.2609406051 |
| /workspace/coverage/default/9.chip_sw_all_escalation_resets.1222488657 |
| /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.2482839875 |
| /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.3128847254 |
| /workspace/coverage/default/90.chip_sw_all_escalation_resets.1981540724 |
| /workspace/coverage/default/92.chip_sw_all_escalation_resets.2376139192 |
| /workspace/coverage/default/93.chip_sw_all_escalation_resets.1354240698 |
| /workspace/coverage/default/94.chip_sw_all_escalation_resets.1589182310 |
| /workspace/coverage/default/95.chip_sw_all_escalation_resets.3087282776 |
| /workspace/coverage/default/96.chip_sw_all_escalation_resets.2496517343 |
| /workspace/coverage/default/97.chip_sw_all_escalation_resets.2183425981 |
| /workspace/coverage/default/98.chip_sw_all_escalation_resets.1553428312 |
| /workspace/coverage/default/99.chip_sw_all_escalation_resets.3582817223 |
| /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.2637572253 |
| /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.3475001133 |
| /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.1847271787 |
| /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.3258097095 |
| /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.189636131 |
| /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.1344735967 |
| /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.2960222522 |
| /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.4207967609 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
| T1 |
/workspace/coverage/default/1.chip_sw_hmac_enc.378811306 |
|
|
Jan 14 03:35:03 PM PST 24 |
Jan 14 03:41:22 PM PST 24 |
3457873940 ps |
| T2 |
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.1855807666 |
|
|
Jan 14 03:58:51 PM PST 24 |
Jan 14 04:05:20 PM PST 24 |
3067069810 ps |
| T3 |
/workspace/coverage/default/0.chip_plic_all_irqs_20.1656843408 |
|
|
Jan 14 03:22:05 PM PST 24 |
Jan 14 03:33:26 PM PST 24 |
4296545608 ps |
| T16 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.3440766501 |
|
|
Jan 14 03:12:26 PM PST 24 |
Jan 14 03:34:59 PM PST 24 |
6839638828 ps |
| T65 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.3525259547 |
|
|
Jan 14 03:32:38 PM PST 24 |
Jan 14 03:46:54 PM PST 24 |
4752753184 ps |
| T17 |
/workspace/coverage/default/25.chip_sw_all_escalation_resets.985105766 |
|
|
Jan 14 03:55:21 PM PST 24 |
Jan 14 04:05:27 PM PST 24 |
4450987428 ps |
| T18 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation.3663837034 |
|
|
Jan 14 03:46:35 PM PST 24 |
Jan 14 03:55:16 PM PST 24 |
4214516810 ps |
| T66 |
/workspace/coverage/default/2.chip_sw_example_manufacturer.196205916 |
|
|
Jan 14 03:41:51 PM PST 24 |
Jan 14 03:45:29 PM PST 24 |
2596493750 ps |
| T49 |
/workspace/coverage/default/2.chip_tap_straps_testunlock0.2623989594 |
|
|
Jan 14 03:48:34 PM PST 24 |
Jan 14 03:53:40 PM PST 24 |
3828884583 ps |
| T23 |
/workspace/coverage/default/1.rom_e2e_static_critical.3574390859 |
|
|
Jan 14 03:43:44 PM PST 24 |
Jan 14 04:21:31 PM PST 24 |
10697370096 ps |
| T44 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.3490784844 |
|
|
Jan 14 03:46:13 PM PST 24 |
Jan 14 03:54:04 PM PST 24 |
3738314702 ps |
| T47 |
/workspace/coverage/default/67.chip_sw_all_escalation_resets.3662353512 |
|
|
Jan 14 03:58:34 PM PST 24 |
Jan 14 04:07:22 PM PST 24 |
3863860168 ps |
| T28 |
/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.1838656571 |
|
|
Jan 14 03:23:53 PM PST 24 |
Jan 14 03:30:43 PM PST 24 |
3482693582 ps |
| T4 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.1290589774 |
|
|
Jan 14 03:31:51 PM PST 24 |
Jan 14 04:06:48 PM PST 24 |
8517945180 ps |
| T48 |
/workspace/coverage/default/36.chip_sw_all_escalation_resets.3606067513 |
|
|
Jan 14 03:59:25 PM PST 24 |
Jan 14 04:10:16 PM PST 24 |
4726232426 ps |
| T54 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3001346990 |
|
|
Jan 14 03:36:34 PM PST 24 |
Jan 14 03:47:03 PM PST 24 |
4381088196 ps |
| T149 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.3582736089 |
|
|
Jan 14 03:37:02 PM PST 24 |
Jan 14 03:43:45 PM PST 24 |
4298309360 ps |
| T101 |
/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.2779572181 |
|
|
Jan 14 03:16:46 PM PST 24 |
Jan 14 03:21:10 PM PST 24 |
2810322439 ps |
| T110 |
/workspace/coverage/default/2.chip_sw_entropy_src_csrng.47257595 |
|
|
Jan 14 03:46:37 PM PST 24 |
Jan 14 04:05:35 PM PST 24 |
5458346656 ps |
| T147 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.2003706274 |
|
|
Jan 14 03:21:04 PM PST 24 |
Jan 14 03:29:13 PM PST 24 |
4963801508 ps |
| T52 |
/workspace/coverage/default/2.chip_tap_straps_rma.1678273927 |
|
|
Jan 14 03:48:14 PM PST 24 |
Jan 14 04:06:55 PM PST 24 |
8669480897 ps |
| T53 |
/workspace/coverage/default/3.chip_tap_straps_rma.3465217006 |
|
|
Jan 14 03:52:02 PM PST 24 |
Jan 14 03:57:17 PM PST 24 |
3228504634 ps |
| T5 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.1424871262 |
|
|
Jan 14 03:33:38 PM PST 24 |
Jan 14 03:42:19 PM PST 24 |
6954871324 ps |
| T55 |
/workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1857976231 |
|
|
Jan 14 03:49:51 PM PST 24 |
Jan 14 03:57:58 PM PST 24 |
3842196168 ps |
| T274 |
/workspace/coverage/default/2.chip_sw_clkmgr_smoketest.2505723111 |
|
|
Jan 14 03:50:14 PM PST 24 |
Jan 14 03:54:44 PM PST 24 |
2944356002 ps |
| T15 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.3631315835 |
|
|
Jan 14 03:33:56 PM PST 24 |
Jan 14 03:40:32 PM PST 24 |
3509729129 ps |
| T6 |
/workspace/coverage/default/1.rom_raw_unlock.2820489235 |
|
|
Jan 14 03:40:54 PM PST 24 |
Jan 14 04:12:35 PM PST 24 |
14695030340 ps |
| T90 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.3368977516 |
|
|
Jan 14 03:45:23 PM PST 24 |
Jan 14 04:14:03 PM PST 24 |
8748039208 ps |
| T317 |
/workspace/coverage/default/60.chip_sw_all_escalation_resets.2660507103 |
|
|
Jan 14 03:58:25 PM PST 24 |
Jan 14 04:06:35 PM PST 24 |
4440091400 ps |
| T211 |
/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.1985747257 |
|
|
Jan 14 03:54:54 PM PST 24 |
Jan 14 04:02:13 PM PST 24 |
3198303480 ps |
| T266 |
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.2293627481 |
|
|
Jan 14 03:59:13 PM PST 24 |
Jan 14 04:05:10 PM PST 24 |
3332648250 ps |
| T213 |
/workspace/coverage/default/2.chip_sw_pattgen_ios.98590801 |
|
|
Jan 14 03:41:42 PM PST 24 |
Jan 14 03:45:51 PM PST 24 |
2736652240 ps |
| T122 |
/workspace/coverage/default/19.chip_sw_uart_rand_baudrate.2869151658 |
|
|
Jan 14 03:55:42 PM PST 24 |
Jan 14 04:56:31 PM PST 24 |
22772704072 ps |
| T99 |
/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.3607307036 |
|
|
Jan 14 03:46:50 PM PST 24 |
Jan 14 03:55:34 PM PST 24 |
6236959494 ps |
| T311 |
/workspace/coverage/default/8.chip_sw_all_escalation_resets.2869038157 |
|
|
Jan 14 03:52:50 PM PST 24 |
Jan 14 04:04:10 PM PST 24 |
5895107840 ps |
| T215 |
/workspace/coverage/default/0.chip_sw_otbn_mem_scramble.362353951 |
|
|
Jan 14 03:17:04 PM PST 24 |
Jan 14 03:24:21 PM PST 24 |
3543091736 ps |
| T180 |
/workspace/coverage/default/57.chip_sw_all_escalation_resets.3431036069 |
|
|
Jan 14 03:57:08 PM PST 24 |
Jan 14 04:07:19 PM PST 24 |
4578608148 ps |
| T94 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.1802561181 |
|
|
Jan 14 03:11:52 PM PST 24 |
Jan 14 03:26:24 PM PST 24 |
5561127032 ps |
| T24 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.2644037573 |
|
|
Jan 14 03:34:58 PM PST 24 |
Jan 14 04:12:25 PM PST 24 |
9122948366 ps |
| T111 |
/workspace/coverage/default/0.chip_sw_edn_kat.2085998364 |
|
|
Jan 14 03:18:30 PM PST 24 |
Jan 14 03:28:25 PM PST 24 |
3461019000 ps |
| T371 |
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.972253202 |
|
|
Jan 14 04:00:02 PM PST 24 |
Jan 14 04:06:20 PM PST 24 |
3344456110 ps |
| T179 |
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.2586293610 |
|
|
Jan 14 03:59:10 PM PST 24 |
Jan 14 04:06:27 PM PST 24 |
3996030964 ps |
| T45 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.2931667546 |
|
|
Jan 14 03:12:35 PM PST 24 |
Jan 14 03:14:44 PM PST 24 |
3397359262 ps |
| T123 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.4139117935 |
|
|
Jan 14 03:53:00 PM PST 24 |
Jan 14 04:10:30 PM PST 24 |
5952178510 ps |
| T270 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx.4257974392 |
|
|
Jan 14 03:52:08 PM PST 24 |
Jan 14 04:05:46 PM PST 24 |
5403623802 ps |
| T136 |
/workspace/coverage/default/13.chip_sw_all_escalation_resets.4229868093 |
|
|
Jan 14 03:56:34 PM PST 24 |
Jan 14 04:10:40 PM PST 24 |
6593503610 ps |
| T112 |
/workspace/coverage/default/0.chip_sw_entropy_src_fuse_en_fw_read_test.811389304 |
|
|
Jan 14 03:17:36 PM PST 24 |
Jan 14 03:25:18 PM PST 24 |
4773042192 ps |
| T151 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.1250790381 |
|
|
Jan 14 03:22:54 PM PST 24 |
Jan 14 03:33:27 PM PST 24 |
4564158424 ps |
| T100 |
/workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.357948076 |
|
|
Jan 14 03:36:18 PM PST 24 |
Jan 14 04:18:58 PM PST 24 |
23449945048 ps |
| T97 |
/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.1771894585 |
|
|
Jan 14 03:17:24 PM PST 24 |
Jan 14 03:25:58 PM PST 24 |
7907527458 ps |
| T25 |
/workspace/coverage/default/1.rom_e2e_asm_init_prod.3338858318 |
|
|
Jan 14 03:43:41 PM PST 24 |
Jan 14 04:15:15 PM PST 24 |
8533781110 ps |
| T102 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.4005056714 |
|
|
Jan 14 03:44:02 PM PST 24 |
Jan 14 04:41:05 PM PST 24 |
18809700421 ps |
| T170 |
/workspace/coverage/default/76.chip_sw_all_escalation_resets.3530006000 |
|
|
Jan 14 04:00:08 PM PST 24 |
Jan 14 04:09:36 PM PST 24 |
5020391838 ps |
| T145 |
/workspace/coverage/default/0.chip_sw_hmac_smoketest.532393805 |
|
|
Jan 14 03:31:09 PM PST 24 |
Jan 14 03:38:42 PM PST 24 |
2967458660 ps |
| T124 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1506840249 |
|
|
Jan 14 03:47:46 PM PST 24 |
Jan 14 04:00:49 PM PST 24 |
4684181920 ps |
| T132 |
/workspace/coverage/default/2.chip_sw_kmac_app_rom.136282981 |
|
|
Jan 14 03:47:26 PM PST 24 |
Jan 14 03:50:12 PM PST 24 |
2793494740 ps |
| T95 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.963048155 |
|
|
Jan 14 03:41:14 PM PST 24 |
Jan 14 07:00:39 PM PST 24 |
73048367586 ps |
| T176 |
/workspace/coverage/default/1.chip_sw_entropy_src_fuse_en_fw_read_test.2070033307 |
|
|
Jan 14 03:35:29 PM PST 24 |
Jan 14 03:45:15 PM PST 24 |
5550837628 ps |
| T178 |
/workspace/coverage/default/0.chip_sw_otbn_smoketest.3994262800 |
|
|
Jan 14 03:30:26 PM PST 24 |
Jan 14 04:10:26 PM PST 24 |
8577885400 ps |
| T281 |
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.200210082 |
|
|
Jan 14 03:53:18 PM PST 24 |
Jan 14 03:59:43 PM PST 24 |
3599846216 ps |
| T46 |
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.964921006 |
|
|
Jan 14 03:53:00 PM PST 24 |
Jan 14 04:00:09 PM PST 24 |
5558991298 ps |
| T103 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2166077022 |
|
|
Jan 14 03:49:30 PM PST 24 |
Jan 14 04:53:51 PM PST 24 |
24621548034 ps |
| T230 |
/workspace/coverage/default/1.chip_sw_plic_sw_irq.555578174 |
|
|
Jan 14 03:37:03 PM PST 24 |
Jan 14 03:42:14 PM PST 24 |
3421999322 ps |
| T190 |
/workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.867408887 |
|
|
Jan 14 03:48:34 PM PST 24 |
Jan 14 04:12:35 PM PST 24 |
20321594495 ps |
| T293 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.694888108 |
|
|
Jan 14 03:45:53 PM PST 24 |
Jan 14 03:58:18 PM PST 24 |
9720197158 ps |
| T21 |
/workspace/coverage/default/1.rom_e2e_shutdown_exception_c.2867866865 |
|
|
Jan 14 03:42:33 PM PST 24 |
Jan 14 04:12:37 PM PST 24 |
8558538170 ps |
| T148 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.2636807302 |
|
|
Jan 14 03:36:16 PM PST 24 |
Jan 14 03:45:45 PM PST 24 |
4126555914 ps |
| T35 |
/workspace/coverage/default/2.chip_sw_alert_test.2914735636 |
|
|
Jan 14 03:44:54 PM PST 24 |
Jan 14 03:52:41 PM PST 24 |
3604409456 ps |
| T350 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.478054560 |
|
|
Jan 14 03:22:26 PM PST 24 |
Jan 14 03:28:42 PM PST 24 |
3482932640 ps |
| T137 |
/workspace/coverage/default/59.chip_sw_all_escalation_resets.370222108 |
|
|
Jan 14 03:57:39 PM PST 24 |
Jan 14 04:07:18 PM PST 24 |
4847428592 ps |
| T197 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops.309408009 |
|
|
Jan 14 03:42:44 PM PST 24 |
Jan 14 03:57:06 PM PST 24 |
4851601464 ps |
| T86 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_peri.665599329 |
|
|
Jan 14 03:36:34 PM PST 24 |
Jan 14 04:02:42 PM PST 24 |
10594111744 ps |
| T351 |
/workspace/coverage/default/1.chip_sw_example_manufacturer.3744290799 |
|
|
Jan 14 03:30:52 PM PST 24 |
Jan 14 03:36:34 PM PST 24 |
2933037212 ps |
| T235 |
/workspace/coverage/default/1.chip_sw_aon_timer_smoketest.369475260 |
|
|
Jan 14 03:40:01 PM PST 24 |
Jan 14 03:47:04 PM PST 24 |
3394240316 ps |
| T214 |
/workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.2760166013 |
|
|
Jan 14 03:41:54 PM PST 24 |
Jan 14 03:52:07 PM PST 24 |
3569851064 ps |
| T206 |
/workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.4149228030 |
|
|
Jan 14 03:34:03 PM PST 24 |
Jan 14 04:00:50 PM PST 24 |
6555044706 ps |
| T146 |
/workspace/coverage/default/1.chip_sw_hmac_smoketest.4132787518 |
|
|
Jan 14 03:41:00 PM PST 24 |
Jan 14 03:47:29 PM PST 24 |
2698008152 ps |
| T505 |
/workspace/coverage/default/16.chip_sw_uart_rand_baudrate.156132360 |
|
|
Jan 14 03:54:23 PM PST 24 |
Jan 14 04:28:26 PM PST 24 |
13169437924 ps |
| T177 |
/workspace/coverage/default/2.chip_sw_entropy_src_fuse_en_fw_read_test.3727340777 |
|
|
Jan 14 03:45:49 PM PST 24 |
Jan 14 03:57:54 PM PST 24 |
4855870460 ps |
| T61 |
/workspace/coverage/default/0.chip_sw_alert_handler_entropy.1411757529 |
|
|
Jan 14 03:18:06 PM PST 24 |
Jan 14 03:22:31 PM PST 24 |
3337627508 ps |
| T506 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.986406663 |
|
|
Jan 14 03:40:41 PM PST 24 |
Jan 14 03:45:22 PM PST 24 |
3111532120 ps |
| T507 |
/workspace/coverage/default/1.chip_sw_rstmgr_sw_req.2143830612 |
|
|
Jan 14 03:33:19 PM PST 24 |
Jan 14 03:42:37 PM PST 24 |
4905373488 ps |
| T236 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.80164537 |
|
|
Jan 14 03:34:31 PM PST 24 |
Jan 14 03:50:02 PM PST 24 |
5262345592 ps |
| T150 |
/workspace/coverage/default/1.chip_sw_aes_enc.1128745070 |
|
|
Jan 14 03:34:22 PM PST 24 |
Jan 14 03:37:41 PM PST 24 |
2716873306 ps |
| T89 |
/workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.1763433752 |
|
|
Jan 14 03:33:26 PM PST 24 |
Jan 14 03:40:26 PM PST 24 |
3867074200 ps |
| T183 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.1776001956 |
|
|
Jan 14 03:32:43 PM PST 24 |
Jan 14 03:35:25 PM PST 24 |
3572986241 ps |
| T138 |
/workspace/coverage/default/3.chip_sw_all_escalation_resets.3291426216 |
|
|
Jan 14 03:52:02 PM PST 24 |
Jan 14 04:05:16 PM PST 24 |
4553626630 ps |
| T22 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.795639830 |
|
|
Jan 14 03:32:31 PM PST 24 |
Jan 14 04:23:13 PM PST 24 |
11595355345 ps |
| T318 |
/workspace/coverage/default/18.chip_sw_all_escalation_resets.4181970503 |
|
|
Jan 14 03:54:25 PM PST 24 |
Jan 14 04:05:49 PM PST 24 |
5940467546 ps |
| T328 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.631351280 |
|
|
Jan 14 03:17:36 PM PST 24 |
Jan 14 03:24:33 PM PST 24 |
4143107910 ps |
| T508 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.1179570326 |
|
|
Jan 14 03:33:59 PM PST 24 |
Jan 14 04:01:58 PM PST 24 |
7233873946 ps |
| T156 |
/workspace/coverage/default/1.chip_sw_edn_boot_mode.2822205600 |
|
|
Jan 14 03:35:11 PM PST 24 |
Jan 14 03:45:11 PM PST 24 |
3287986012 ps |
| T509 |
/workspace/coverage/default/0.chip_sw_csrng_smoketest.3237755451 |
|
|
Jan 14 03:29:27 PM PST 24 |
Jan 14 03:32:52 PM PST 24 |
2382854672 ps |
| T465 |
/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.732069470 |
|
|
Jan 14 03:58:25 PM PST 24 |
Jan 14 04:03:53 PM PST 24 |
3408909824 ps |
| T237 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2538079709 |
|
|
Jan 14 03:46:21 PM PST 24 |
Jan 14 04:08:38 PM PST 24 |
13388506922 ps |
| T13 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.3681081650 |
|
|
Jan 14 03:40:45 PM PST 24 |
Jan 14 03:55:40 PM PST 24 |
5420012666 ps |
| T153 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.1081421952 |
|
|
Jan 14 03:48:45 PM PST 24 |
Jan 14 03:58:02 PM PST 24 |
4478729956 ps |
| T510 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.1926295377 |
|
|
Jan 14 03:35:02 PM PST 24 |
Jan 14 04:04:57 PM PST 24 |
6775552766 ps |
| T511 |
/workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.3113153926 |
|
|
Jan 14 03:18:25 PM PST 24 |
Jan 14 03:22:25 PM PST 24 |
3016257528 ps |
| T154 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.856618247 |
|
|
Jan 14 03:37:18 PM PST 24 |
Jan 14 03:43:23 PM PST 24 |
4472033528 ps |
| T139 |
/workspace/coverage/default/2.chip_sw_rstmgr_alert_info.1086468258 |
|
|
Jan 14 03:42:53 PM PST 24 |
Jan 14 04:04:36 PM PST 24 |
8659071610 ps |
| T125 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1419493493 |
|
|
Jan 14 03:37:22 PM PST 24 |
Jan 14 03:48:44 PM PST 24 |
4851679070 ps |
| T512 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac.2830528538 |
|
|
Jan 14 03:46:10 PM PST 24 |
Jan 14 03:51:16 PM PST 24 |
3068108526 ps |
| T184 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.3858785844 |
|
|
Jan 14 03:43:09 PM PST 24 |
Jan 14 04:18:35 PM PST 24 |
20984803270 ps |
| T172 |
/workspace/coverage/default/1.chip_plic_all_irqs_0.4026512406 |
|
|
Jan 14 03:37:01 PM PST 24 |
Jan 14 03:58:09 PM PST 24 |
6614867876 ps |
| T433 |
/workspace/coverage/default/5.chip_sw_all_escalation_resets.488497316 |
|
|
Jan 14 03:52:54 PM PST 24 |
Jan 14 04:02:46 PM PST 24 |
5362930768 ps |
| T513 |
/workspace/coverage/default/1.chip_sw_uart_smoketest_signed.2468021098 |
|
|
Jan 14 03:44:34 PM PST 24 |
Jan 14 04:19:48 PM PST 24 |
8709904176 ps |
| T514 |
/workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.1517760991 |
|
|
Jan 14 03:16:43 PM PST 24 |
Jan 14 03:27:34 PM PST 24 |
5597255716 ps |
| T515 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.611756673 |
|
|
Jan 14 03:15:05 PM PST 24 |
Jan 14 03:31:37 PM PST 24 |
7661698198 ps |
| T516 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2485402852 |
|
|
Jan 14 03:36:32 PM PST 24 |
Jan 14 03:46:33 PM PST 24 |
4554889604 ps |
| T113 |
/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.2167987240 |
|
|
Jan 14 03:26:11 PM PST 24 |
Jan 14 04:25:07 PM PST 24 |
18726556314 ps |
| T264 |
/workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.2684057682 |
|
|
Jan 14 03:43:33 PM PST 24 |
Jan 14 03:52:09 PM PST 24 |
6742589040 ps |
| T87 |
/workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.4181848378 |
|
|
Jan 14 03:34:28 PM PST 24 |
Jan 14 03:37:44 PM PST 24 |
2864136946 ps |
| T517 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.290717079 |
|
|
Jan 14 03:12:14 PM PST 24 |
Jan 14 03:21:37 PM PST 24 |
4218844952 ps |
| T431 |
/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.2802327982 |
|
|
Jan 14 03:56:44 PM PST 24 |
Jan 14 04:04:59 PM PST 24 |
4002029408 ps |
| T425 |
/workspace/coverage/default/17.chip_sw_all_escalation_resets.1881859787 |
|
|
Jan 14 03:54:37 PM PST 24 |
Jan 14 04:05:06 PM PST 24 |
4777530926 ps |
| T220 |
/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.614600972 |
|
|
Jan 14 03:53:49 PM PST 24 |
Jan 14 03:59:47 PM PST 24 |
3771661760 ps |
| T518 |
/workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.2413130645 |
|
|
Jan 14 03:34:02 PM PST 24 |
Jan 14 03:37:05 PM PST 24 |
2234707100 ps |
| T173 |
/workspace/coverage/default/2.chip_sw_hmac_enc.87319053 |
|
|
Jan 14 03:46:59 PM PST 24 |
Jan 14 03:51:04 PM PST 24 |
3125974584 ps |
| T267 |
/workspace/coverage/default/2.chip_sw_aon_timer_irq.517356583 |
|
|
Jan 14 03:43:31 PM PST 24 |
Jan 14 03:49:06 PM PST 24 |
4092512696 ps |
| T519 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.1398489014 |
|
|
Jan 14 03:46:12 PM PST 24 |
Jan 14 03:51:59 PM PST 24 |
3280972628 ps |
| T414 |
/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.1814785812 |
|
|
Jan 14 03:58:10 PM PST 24 |
Jan 14 04:04:22 PM PST 24 |
3320106128 ps |
| T194 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.764199947 |
|
|
Jan 14 03:11:45 PM PST 24 |
Jan 14 03:19:08 PM PST 24 |
5210198041 ps |
| T14 |
/workspace/coverage/default/2.chip_sw_sleep_pin_retention.2894533839 |
|
|
Jan 14 03:41:14 PM PST 24 |
Jan 14 03:46:04 PM PST 24 |
4351802320 ps |
| T77 |
/workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.3231144790 |
|
|
Jan 14 03:43:20 PM PST 24 |
Jan 14 03:52:34 PM PST 24 |
9665539012 ps |
| T78 |
/workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.2513094546 |
|
|
Jan 14 03:30:19 PM PST 24 |
Jan 14 03:38:43 PM PST 24 |
4950350800 ps |
| T79 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.2981508677 |
|
|
Jan 14 03:38:22 PM PST 24 |
Jan 14 04:14:11 PM PST 24 |
8193297792 ps |
| T80 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.1593089689 |
|
|
Jan 14 03:48:14 PM PST 24 |
Jan 14 03:57:08 PM PST 24 |
7028637093 ps |
| T81 |
/workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.1250002914 |
|
|
Jan 14 03:17:13 PM PST 24 |
Jan 14 03:24:31 PM PST 24 |
4402339980 ps |
| T82 |
/workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.899156435 |
|
|
Jan 14 03:32:11 PM PST 24 |
Jan 14 03:39:56 PM PST 24 |
4244825405 ps |
| T83 |
/workspace/coverage/default/2.chip_sw_edn_boot_mode.1740605258 |
|
|
Jan 14 03:45:36 PM PST 24 |
Jan 14 03:54:47 PM PST 24 |
3314858572 ps |
| T84 |
/workspace/coverage/default/0.chip_sw_entropy_src_smoketest.2050171766 |
|
|
Jan 14 03:29:58 PM PST 24 |
Jan 14 03:40:04 PM PST 24 |
4264483616 ps |
| T85 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.2257830313 |
|
|
Jan 14 03:31:12 PM PST 24 |
Jan 14 03:52:39 PM PST 24 |
9125451664 ps |
| T199 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.4198383459 |
|
|
Jan 14 03:46:27 PM PST 24 |
Jan 14 03:55:36 PM PST 24 |
4529785348 ps |
| T520 |
/workspace/coverage/default/2.rom_e2e_asm_init_rma.2347843124 |
|
|
Jan 14 03:53:37 PM PST 24 |
Jan 14 04:17:00 PM PST 24 |
8628101809 ps |
| T521 |
/workspace/coverage/default/0.chip_sw_example_concurrency.1686784320 |
|
|
Jan 14 03:11:40 PM PST 24 |
Jan 14 03:16:02 PM PST 24 |
2753422700 ps |
| T419 |
/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.1160640945 |
|
|
Jan 14 03:54:30 PM PST 24 |
Jan 14 04:01:41 PM PST 24 |
3474091634 ps |
| T474 |
/workspace/coverage/default/65.chip_sw_all_escalation_resets.4252366397 |
|
|
Jan 14 03:58:30 PM PST 24 |
Jan 14 04:06:58 PM PST 24 |
4861604504 ps |
| T212 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.813579037 |
|
|
Jan 14 03:41:39 PM PST 24 |
Jan 14 03:57:39 PM PST 24 |
5918875580 ps |
| T316 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.3887886617 |
|
|
Jan 14 03:16:59 PM PST 24 |
Jan 14 04:19:57 PM PST 24 |
18905492682 ps |
| T104 |
/workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.900208591 |
|
|
Jan 14 03:39:59 PM PST 24 |
Jan 14 03:53:13 PM PST 24 |
10992799428 ps |
| T401 |
/workspace/coverage/default/15.chip_sw_all_escalation_resets.1413509007 |
|
|
Jan 14 03:56:37 PM PST 24 |
Jan 14 04:09:28 PM PST 24 |
4681257480 ps |
| T96 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.246567957 |
|
|
Jan 14 03:11:23 PM PST 24 |
Jan 14 06:36:51 PM PST 24 |
72567172535 ps |
| T280 |
/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.1914767572 |
|
|
Jan 14 03:55:12 PM PST 24 |
Jan 14 04:01:20 PM PST 24 |
3884587760 ps |
| T522 |
/workspace/coverage/default/1.chip_sw_otbn_randomness.1966755147 |
|
|
Jan 14 03:33:57 PM PST 24 |
Jan 14 03:43:02 PM PST 24 |
6424086856 ps |
| T523 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2312712877 |
|
|
Jan 14 03:33:05 PM PST 24 |
Jan 14 03:55:17 PM PST 24 |
13070670860 ps |
| T333 |
/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.695372737 |
|
|
Jan 14 03:36:04 PM PST 24 |
Jan 14 03:48:49 PM PST 24 |
6460011156 ps |
| T185 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.29211124 |
|
|
Jan 14 03:22:53 PM PST 24 |
Jan 14 03:41:03 PM PST 24 |
9772227431 ps |
| T10 |
/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.189636131 |
|
|
Jan 14 03:04:50 PM PST 24 |
Jan 14 03:10:29 PM PST 24 |
5763585198 ps |
| T11 |
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.1344735967 |
|
|
Jan 14 03:04:50 PM PST 24 |
Jan 14 03:09:13 PM PST 24 |
4942958954 ps |
| T12 |
/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.2423065653 |
|
|
Jan 14 03:04:49 PM PST 24 |
Jan 14 03:10:01 PM PST 24 |
5222507303 ps |
| T19 |
/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.2960222522 |
|
|
Jan 14 03:04:51 PM PST 24 |
Jan 14 03:10:44 PM PST 24 |
5236643706 ps |
| T20 |
/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.1847271787 |
|
|
Jan 14 03:04:49 PM PST 24 |
Jan 14 03:09:12 PM PST 24 |
4903619872 ps |
| T91 |
/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.2637572253 |
|
|
Jan 14 03:04:41 PM PST 24 |
Jan 14 03:08:54 PM PST 24 |
4426269080 ps |
| T337 |
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.3258097095 |
|
|
Jan 14 03:04:49 PM PST 24 |
Jan 14 03:08:28 PM PST 24 |
4246006048 ps |
| T126 |
/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.3475001133 |
|
|
Jan 14 03:04:49 PM PST 24 |
Jan 14 03:08:34 PM PST 24 |
5514115290 ps |
| T326 |
/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.2930180537 |
|
|
Jan 14 03:04:49 PM PST 24 |
Jan 14 03:09:01 PM PST 24 |
3803949443 ps |
| T524 |
/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.4207967609 |
|
|
Jan 14 03:04:51 PM PST 24 |
Jan 14 03:09:35 PM PST 24 |
4789341591 ps |
| T271 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.539483519 |
|
|
Jan 14 03:11:42 PM PST 24 |
Jan 14 03:24:44 PM PST 24 |
6213602191 ps |
| T525 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.2418040873 |
|
|
Jan 14 03:42:26 PM PST 24 |
Jan 14 03:59:06 PM PST 24 |
5614396168 ps |
| T152 |
/workspace/coverage/default/2.chip_sw_aes_smoketest.3431262394 |
|
|
Jan 14 03:51:15 PM PST 24 |
Jan 14 03:57:19 PM PST 24 |
2794116800 ps |
| T105 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.1070053252 |
|
|
Jan 14 03:21:38 PM PST 24 |
Jan 14 03:30:42 PM PST 24 |
4257508935 ps |
| T247 |
/workspace/coverage/default/0.chip_sw_uart_rand_baudrate.3738349787 |
|
|
Jan 14 03:11:55 PM PST 24 |
Jan 14 04:21:54 PM PST 24 |
23305037756 ps |
| T248 |
/workspace/coverage/default/2.chip_sw_aes_idle.1321522624 |
|
|
Jan 14 03:45:07 PM PST 24 |
Jan 14 03:49:29 PM PST 24 |
1988892870 ps |
| T186 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.3708842860 |
|
|
Jan 14 03:14:47 PM PST 24 |
Jan 14 04:49:15 PM PST 24 |
49444136936 ps |
| T249 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_access.560277196 |
|
|
Jan 14 03:32:36 PM PST 24 |
Jan 14 03:51:59 PM PST 24 |
5546621596 ps |
| T526 |
/workspace/coverage/default/2.chip_sw_otbn_randomness.1572852637 |
|
|
Jan 14 03:44:59 PM PST 24 |
Jan 14 03:53:20 PM PST 24 |
5747595208 ps |
| T188 |
/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.1073781127 |
|
|
Jan 14 03:26:20 PM PST 24 |
Jan 14 04:06:05 PM PST 24 |
25511161619 ps |
| T297 |
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.673039920 |
|
|
Jan 14 03:58:21 PM PST 24 |
Jan 14 04:06:00 PM PST 24 |
3683187120 ps |
| T527 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.4056409175 |
|
|
Jan 14 03:33:59 PM PST 24 |
Jan 14 03:52:31 PM PST 24 |
5856133992 ps |
| T198 |
/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.3197699535 |
|
|
Jan 14 03:54:27 PM PST 24 |
Jan 14 04:01:44 PM PST 24 |
4013956936 ps |
| T528 |
/workspace/coverage/default/1.chip_sw_csrng_kat_test.2321799630 |
|
|
Jan 14 03:34:06 PM PST 24 |
Jan 14 03:37:57 PM PST 24 |
2464731272 ps |
| T269 |
/workspace/coverage/default/77.chip_sw_all_escalation_resets.127088620 |
|
|
Jan 14 04:00:22 PM PST 24 |
Jan 14 04:08:41 PM PST 24 |
4399479844 ps |
| T342 |
/workspace/coverage/default/34.chip_sw_all_escalation_resets.1892548018 |
|
|
Jan 14 03:55:01 PM PST 24 |
Jan 14 04:03:23 PM PST 24 |
5306856800 ps |
| T332 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.1309422625 |
|
|
Jan 14 03:37:44 PM PST 24 |
Jan 14 04:16:23 PM PST 24 |
8850330988 ps |
| T26 |
/workspace/coverage/default/2.chip_jtag_csr_rw.54161909 |
|
|
Jan 14 03:41:38 PM PST 24 |
Jan 14 04:17:05 PM PST 24 |
19681799096 ps |
| T347 |
/workspace/coverage/default/1.chip_sw_edn_entropy_reqs.2988749098 |
|
|
Jan 14 03:35:32 PM PST 24 |
Jan 14 03:51:02 PM PST 24 |
4037402086 ps |
| T309 |
/workspace/coverage/default/68.chip_sw_all_escalation_resets.270760131 |
|
|
Jan 14 03:58:23 PM PST 24 |
Jan 14 04:07:48 PM PST 24 |
4740655320 ps |
| T372 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.1240219 |
|
|
Jan 14 03:45:50 PM PST 24 |
Jan 14 04:51:23 PM PST 24 |
17582175048 ps |
| T529 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.2198270389 |
|
|
Jan 14 03:11:23 PM PST 24 |
Jan 14 03:26:31 PM PST 24 |
5663786648 ps |
| T362 |
/workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.2196867796 |
|
|
Jan 14 03:37:25 PM PST 24 |
Jan 14 03:44:36 PM PST 24 |
3458123056 ps |
| T210 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.3088128181 |
|
|
Jan 14 03:12:23 PM PST 24 |
Jan 14 03:14:31 PM PST 24 |
3334865362 ps |
| T344 |
/workspace/coverage/default/47.chip_sw_all_escalation_resets.1417537259 |
|
|
Jan 14 03:56:53 PM PST 24 |
Jan 14 04:07:59 PM PST 24 |
4691535770 ps |
| T348 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.2698389936 |
|
|
Jan 14 03:52:35 PM PST 24 |
Jan 14 04:08:15 PM PST 24 |
5513643660 ps |
| T268 |
/workspace/coverage/default/0.chip_sw_aon_timer_irq.497394495 |
|
|
Jan 14 03:16:18 PM PST 24 |
Jan 14 03:21:29 PM PST 24 |
3683358680 ps |
| T349 |
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.3817250641 |
|
|
Jan 14 03:52:15 PM PST 24 |
Jan 14 04:12:39 PM PST 24 |
14406647166 ps |
| T314 |
/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.627456215 |
|
|
Jan 14 03:25:52 PM PST 24 |
Jan 14 03:31:03 PM PST 24 |
3602829672 ps |
| T282 |
/workspace/coverage/default/11.chip_sw_uart_rand_baudrate.2382063344 |
|
|
Jan 14 03:55:43 PM PST 24 |
Jan 14 04:33:08 PM PST 24 |
13925644142 ps |
| T530 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.1159135720 |
|
|
Jan 14 03:31:21 PM PST 24 |
Jan 14 03:56:41 PM PST 24 |
7636889436 ps |
| T531 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter.3760673547 |
|
|
Jan 14 03:22:50 PM PST 24 |
Jan 14 03:26:38 PM PST 24 |
2346814123 ps |
| T37 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.447597823 |
|
|
Jan 14 03:42:45 PM PST 24 |
Jan 14 03:47:09 PM PST 24 |
3434446727 ps |
| T532 |
/workspace/coverage/default/13.chip_sw_lc_ctrl_transition.3304271002 |
|
|
Jan 14 03:54:19 PM PST 24 |
Jan 14 04:04:11 PM PST 24 |
7017737586 ps |
| T233 |
/workspace/coverage/default/1.chip_sw_rv_timer_smoketest.2641048391 |
|
|
Jan 14 03:40:57 PM PST 24 |
Jan 14 03:45:32 PM PST 24 |
3007167344 ps |
| T127 |
/workspace/coverage/default/0.chip_jtag_mem_access.3440348194 |
|
|
Jan 14 03:17:00 PM PST 24 |
Jan 14 03:40:49 PM PST 24 |
13093760136 ps |
| T143 |
/workspace/coverage/default/0.chip_plic_all_irqs_10.2312883883 |
|
|
Jan 14 03:22:18 PM PST 24 |
Jan 14 03:33:50 PM PST 24 |
4583887462 ps |
| T533 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2480053884 |
|
|
Jan 14 03:48:08 PM PST 24 |
Jan 14 03:57:37 PM PST 24 |
3358629166 ps |
| T283 |
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.3747940282 |
|
|
Jan 14 03:53:55 PM PST 24 |
Jan 14 04:07:04 PM PST 24 |
4727197516 ps |
| T144 |
/workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.1812088498 |
|
|
Jan 14 03:43:14 PM PST 24 |
Jan 14 03:47:22 PM PST 24 |
2946807418 ps |
| T161 |
/workspace/coverage/default/2.chip_sw_spi_device_pass_through.2631721663 |
|
|
Jan 14 03:41:38 PM PST 24 |
Jan 14 03:51:08 PM PST 24 |
5310555383 ps |
| T273 |
/workspace/coverage/default/1.chip_sw_power_idle_load.3702405989 |
|
|
Jan 14 03:39:00 PM PST 24 |
Jan 14 03:51:47 PM PST 24 |
4375936870 ps |
| T388 |
/workspace/coverage/default/43.chip_sw_all_escalation_resets.2924364607 |
|
|
Jan 14 04:00:51 PM PST 24 |
Jan 14 04:11:16 PM PST 24 |
4178478016 ps |
| T534 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.1692471167 |
|
|
Jan 14 03:21:52 PM PST 24 |
Jan 14 03:37:46 PM PST 24 |
6795592546 ps |
| T92 |
/workspace/coverage/default/2.chip_plic_all_irqs_20.3517430689 |
|
|
Jan 14 03:48:11 PM PST 24 |
Jan 14 04:00:57 PM PST 24 |
4943666840 ps |
| T174 |
/workspace/coverage/default/2.chip_plic_all_irqs_0.2373495988 |
|
|
Jan 14 03:46:24 PM PST 24 |
Jan 14 04:05:31 PM PST 24 |
6829730068 ps |
| T284 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.2766757181 |
|
|
Jan 14 03:32:26 PM PST 24 |
Jan 14 03:49:55 PM PST 24 |
5449532774 ps |
| T107 |
/workspace/coverage/default/0.chip_sw_power_sleep_load.2497698208 |
|
|
Jan 14 03:26:41 PM PST 24 |
Jan 14 03:35:48 PM PST 24 |
10201090376 ps |
| T225 |
/workspace/coverage/default/0.rom_e2e_shutdown_exception_c.4241523706 |
|
|
Jan 14 03:30:04 PM PST 24 |
Jan 14 04:06:55 PM PST 24 |
8929184258 ps |
| T67 |
/workspace/coverage/default/86.chip_sw_all_escalation_resets.1939192573 |
|
|
Jan 14 04:00:43 PM PST 24 |
Jan 14 04:08:32 PM PST 24 |
4914735210 ps |
| T69 |
/workspace/coverage/default/1.rom_e2e_asm_init_rma.4106765561 |
|
|
Jan 14 03:43:31 PM PST 24 |
Jan 14 04:17:26 PM PST 24 |
9008076741 ps |
| T70 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1729113114 |
|
|
Jan 14 03:44:04 PM PST 24 |
Jan 14 03:50:29 PM PST 24 |
5035113336 ps |
| T71 |
/workspace/coverage/default/11.chip_sw_lc_ctrl_transition.2272091376 |
|
|
Jan 14 03:55:52 PM PST 24 |
Jan 14 04:12:22 PM PST 24 |
9928867267 ps |
| T72 |
/workspace/coverage/default/0.chip_sw_clkmgr_smoketest.1223043340 |
|
|
Jan 14 03:30:28 PM PST 24 |
Jan 14 03:33:10 PM PST 24 |
2887750624 ps |
| T73 |
/workspace/coverage/default/2.chip_sw_power_sleep_load.2224770079 |
|
|
Jan 14 03:49:24 PM PST 24 |
Jan 14 03:57:50 PM PST 24 |
10021553840 ps |
| T74 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1684456249 |
|
|
Jan 14 03:32:22 PM PST 24 |
Jan 14 03:44:57 PM PST 24 |
3602309984 ps |
| T75 |
/workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.3825764683 |
|
|
Jan 14 03:11:51 PM PST 24 |
Jan 14 03:34:57 PM PST 24 |
7929470270 ps |
| T29 |
/workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.589026412 |
|
|
Jan 14 03:37:35 PM PST 24 |
Jan 14 03:43:11 PM PST 24 |
3803330250 ps |
| T76 |
/workspace/coverage/default/1.chip_sw_otbn_mem_scramble.2685882895 |
|
|
Jan 14 03:34:57 PM PST 24 |
Jan 14 03:45:28 PM PST 24 |
3965841254 ps |
| T397 |
/workspace/coverage/default/74.chip_sw_all_escalation_resets.2207584639 |
|
|
Jan 14 04:00:26 PM PST 24 |
Jan 14 04:11:04 PM PST 24 |
5128267780 ps |
| T278 |
/workspace/coverage/default/0.chip_sw_pattgen_ios.199342734 |
|
|
Jan 14 03:11:20 PM PST 24 |
Jan 14 03:15:12 PM PST 24 |
2223969060 ps |
| T423 |
/workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.3668837903 |
|
|
Jan 14 03:47:31 PM PST 24 |
Jan 14 03:53:30 PM PST 24 |
3654507460 ps |
| T27 |
/workspace/coverage/default/1.chip_sw_sleep_pin_wake.3795847690 |
|
|
Jan 14 03:31:46 PM PST 24 |
Jan 14 03:36:15 PM PST 24 |
2717350692 ps |
| T378 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1454274074 |
|
|
Jan 14 03:15:00 PM PST 24 |
Jan 14 03:22:41 PM PST 24 |
6465962488 ps |
| T106 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.124687705 |
|
|
Jan 14 03:38:29 PM PST 24 |
Jan 14 03:44:52 PM PST 24 |
4775870270 ps |
| T369 |
/workspace/coverage/default/2.chip_sw_edn_sw_mode.4110502386 |
|
|
Jan 14 03:46:06 PM PST 24 |
Jan 14 04:05:33 PM PST 24 |
6051193904 ps |
| T201 |
/workspace/coverage/default/20.chip_sw_all_escalation_resets.129387876 |
|
|
Jan 14 03:54:27 PM PST 24 |
Jan 14 04:04:37 PM PST 24 |
5146351080 ps |
| T363 |
/workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.4011175488 |
|
|
Jan 14 03:46:29 PM PST 24 |
Jan 14 04:00:40 PM PST 24 |
4620803628 ps |
| T294 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.2387242739 |
|
|
Jan 14 03:35:04 PM PST 24 |
Jan 14 03:45:49 PM PST 24 |
4006572382 ps |
| T222 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.4072234906 |
|
|
Jan 14 03:32:20 PM PST 24 |
Jan 14 04:23:24 PM PST 24 |
12240081800 ps |
| T535 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.30003840 |
|
|
Jan 14 03:32:32 PM PST 24 |
Jan 14 04:03:38 PM PST 24 |
9099914982 ps |
| T536 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.192154822 |
|
|
Jan 14 03:36:54 PM PST 24 |
Jan 14 03:46:06 PM PST 24 |
4872267594 ps |
| T537 |
/workspace/coverage/default/2.chip_sw_rv_plic_smoketest.3933366986 |
|
|
Jan 14 03:51:15 PM PST 24 |
Jan 14 03:56:36 PM PST 24 |
3083179760 ps |
| T238 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.1937889568 |
|
|
Jan 14 03:49:06 PM PST 24 |
Jan 14 03:54:47 PM PST 24 |
3597206038 ps |
| T255 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.3291548569 |
|
|
Jan 14 03:14:51 PM PST 24 |
Jan 14 03:25:16 PM PST 24 |
6251756156 ps |
| T256 |
/workspace/coverage/default/22.chip_sw_all_escalation_resets.1984842853 |
|
|
Jan 14 03:54:19 PM PST 24 |
Jan 14 04:06:05 PM PST 24 |
5338154104 ps |
| T257 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.3228479726 |
|
|
Jan 14 03:16:21 PM PST 24 |
Jan 14 03:31:05 PM PST 24 |
5594256884 ps |
| T258 |
/workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.486074435 |
|
|
Jan 14 03:15:17 PM PST 24 |
Jan 14 03:22:59 PM PST 24 |
7638288336 ps |
| T259 |
/workspace/coverage/default/49.chip_sw_all_escalation_resets.2489373807 |
|
|
Jan 14 03:56:56 PM PST 24 |
Jan 14 04:07:40 PM PST 24 |
5168083880 ps |
| T260 |
/workspace/coverage/default/2.chip_sw_gpio_smoketest.1790999585 |
|
|
Jan 14 03:50:34 PM PST 24 |
Jan 14 03:54:04 PM PST 24 |
2684781651 ps |
| T538 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1078529726 |
|
|
Jan 14 03:42:30 PM PST 24 |
Jan 14 04:10:04 PM PST 24 |
13530330132 ps |
| T462 |
/workspace/coverage/default/30.chip_sw_all_escalation_resets.1154859849 |
|
|
Jan 14 03:55:30 PM PST 24 |
Jan 14 04:06:14 PM PST 24 |
5199583700 ps |
| T377 |
/workspace/coverage/default/87.chip_sw_all_escalation_resets.4213152856 |
|
|
Jan 14 03:59:48 PM PST 24 |
Jan 14 04:08:29 PM PST 24 |
4891808116 ps |
| T539 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1914982626 |
|
|
Jan 14 03:49:22 PM PST 24 |
Jan 14 03:54:57 PM PST 24 |
3108449593 ps |
| T475 |
/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.3048853013 |
|
|
Jan 14 03:58:28 PM PST 24 |
Jan 14 04:04:21 PM PST 24 |
3795458436 ps |
| T540 |
/workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.1657533612 |
|
|
Jan 14 03:43:44 PM PST 24 |
Jan 14 03:51:31 PM PST 24 |
5167315518 ps |
| T541 |
/workspace/coverage/default/27.chip_sw_all_escalation_resets.334589018 |
|
|
Jan 14 03:56:05 PM PST 24 |
Jan 14 04:05:44 PM PST 24 |
4755927568 ps |
| T466 |
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.3935988756 |
|
|
Jan 14 04:02:29 PM PST 24 |
Jan 14 04:10:35 PM PST 24 |
3420371980 ps |
| T542 |
/workspace/coverage/default/0.chip_sw_all_escalation_resets.651627585 |
|
|
Jan 14 03:11:55 PM PST 24 |
Jan 14 03:21:34 PM PST 24 |
6102435026 ps |
| T157 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.1418635200 |
|
|
Jan 14 03:21:02 PM PST 24 |
Jan 14 03:32:58 PM PST 24 |
4941037388 ps |
| T116 |
/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.1042322016 |
|
|
Jan 14 03:22:10 PM PST 24 |
Jan 14 03:40:59 PM PST 24 |
7047492536 ps |
| T543 |
/workspace/coverage/default/0.chip_sw_rstmgr_smoketest.698716704 |
|
|
Jan 14 03:31:50 PM PST 24 |
Jan 14 03:35:14 PM PST 24 |
2500179384 ps |