Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.rom_ctrl__regs_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	156125	1			T31	86		T32	107		T53	88
values[2]	4598	1			T32	1		T221	57		T102	1
values[3]	2290	1			T221	48		T387	19		T502	7
values[4]	1752	1			T221	38		T387	26		T502	12
values[5]	1429	1			T221	14		T387	21		T502	21
values[6]	1214	1			T221	5		T387	32		T502	21
values[7]	1059	1			T221	7		T387	23		T502	11
values[8]	831	1			T221	12		T387	10		T502	16
values[9]	801	1			T221	17		T387	11		T502	24
values[10]	701	1			T221	15		T387	10		T502	37
values[11]	703	1			T221	17		T387	20		T502	27
values[12]	678	1			T221	23		T387	18		T502	22
values[13]	626	1			T221	34		T387	8		T502	17
values[14]	551	1			T221	42		T387	8		T502	20
values[15]	444	1			T221	44		T387	13		T502	4
values[16]	411	1			T221	44		T387	10		T502	4
values[17]	388	1			T221	31		T387	22		T502	3
values[18]	370	1			T221	33		T387	12		T650	2
values[19]	346	1			T221	21		T387	23		T650	3
values[20]	320	1			T221	6		T387	29		T650	1
values[21]	309	1			T387	41		T650	2		T501	5
values[22]	329	1			T387	42		T650	1		T501	9
values[23]	361	1			T387	34		T650	3		T501	9
values[24]	312	1			T387	22		T650	1		T501	10
values[25]	285	1			T387	7		T650	5		T501	1
values[26]	224	1			T387	7		T650	2		T775	41
values[27]	203	1			T387	6		T650	1		T775	33
values[28]	154	1			T387	1		T650	1		T775	14
values[29]	183	1			T650	2		T775	4		T753	1
values[30]	130	1			T650	4		T753	1		T746	1
values[31]	135	1			T650	1		T753	1		T746	1
values[32]	134	1			T650	1		T753	1		T746	1
values[33]	120	1			T650	2		T753	1		T746	1
values[34]	140	1			T650	2		T753	1		T746	1
values[35]	108	1			T650	6		T753	1		T746	1
values[36]	71	1			T650	3		T753	1		T746	1
values[37]	83	1			T650	4		T753	1		T746	1
values[38]	67	1			T650	1		T753	1		T746	1
values[39]	57	1			T650	4		T753	1		T746	1
values[40]	51	1			T650	2		T753	1		T746	1
values[41]	50	1			T650	2		T753	1		T746	1
values[42]	51	1			T650	1		T753	1		T746	1
values[43]	80	1			T650	4		T753	1		T746	1
values[44]	105	1			T650	3		T753	1		T746	1
values[45]	151	1			T650	1		T753	1		T746	1
values[46]	81	1			T650	2		T753	1		T746	1
values[47]	66	1			T650	2		T753	1		T746	1
values[48]	60	1			T650	7		T753	1		T746	1
values[49]	65	1			T650	3		T753	1		T746	1
values[50]	74	1			T650	2		T753	1		T746	1
values[51]	68	1			T650	3		T753	1		T746	1
values[52]	69	1			T650	3		T753	1		T746	1
values[53]	63	1			T650	3		T753	1		T746	1
values[54]	73	1			T650	3		T753	1		T746	1
values[55]	50	1			T650	3		T753	1		T746	1
values[56]	49	1			T650	2		T753	1		T746	1
values[57]	47	1			T650	3		T753	1		T746	1
values[58]	44	1			T650	2		T753	1		T746	1
values[59]	43	1			T650	1		T753	1		T746	1
values[60]	44	1			T650	1		T753	1		T746	1
values[61]	38	1			T650	2		T753	1		T746	1
values[62]	38	1			T650	3		T753	1		T746	1
values[63]	45	1			T650	2		T753	1		T746	1
values[64]	41	1			T650	1		T753	1		T746	1
values[65]	44	1			T650	1		T753	1		T746	1
values[66]	45	1			T650	2		T753	1		T746	1
values[67]	54	1			T650	6		T753	1		T746	1
values[68]	43	1			T650	3		T753	1		T746	1
values[69]	40	1			T650	1		T753	1		T746	1
values[70]	40	1			T650	2		T753	1		T746	1
values[71]	38	1			T650	1		T753	1		T746	1
values[72]	43	1			T650	4		T753	1		T746	1
values[73]	42	1			T650	2		T753	1		T746	1
values[74]	50	1			T650	3		T753	1		T746	1
values[75]	48	1			T650	2		T753	1		T746	1
values[76]	46	1			T650	2		T753	1		T746	1
values[77]	37	1			T650	1		T753	1		T746	1
values[78]	46	1			T650	5		T753	1		T746	1
values[79]	44	1			T650	4		T753	1		T746	1
values[80]	53	1			T650	6		T753	1		T746	1
values[81]	57	1			T650	8		T753	1		T746	1
values[82]	64	1			T650	3		T753	1		T746	1
values[83]	62	1			T650	1		T753	1		T746	1
values[84]	45	1			T650	1		T753	1		T746	1
values[85]	50	1			T650	1		T753	1		T746	1
values[86]	65	1			T650	8		T753	1		T746	1
values[87]	60	1			T650	4		T753	1		T746	1
values[88]	54	1			T650	9		T753	1		T746	1
values[89]	45	1			T650	3		T753	1		T746	1
values[90]	50	1			T650	2		T753	1		T746	1
values[91]	44	1			T650	4		T753	1		T746	1
values[92]	52	1			T650	2		T753	1		T746	1
values[93]	52	1			T650	2		T753	1		T746	1
values[94]	51	1			T650	5		T753	1		T746	1
values[95]	53	1			T650	7		T753	1		T746	1
values[96]	57	1			T650	10		T753	1		T746	1
values[97]	50	1			T650	1		T753	1		T746	1
values[98]	64	1			T650	4		T753	1		T746	1
values[99]	55	1			T650	2		T753	1		T746	1
values[100]	59	1			T650	3		T753	1		T746	1
values[101]	58	1			T650	6		T753	1		T746	1
values[102]	59	1			T650	3		T753	1		T746	1
values[103]	57	1			T650	1		T753	1		T746	1
values[104]	76	1			T650	3		T753	1		T746	1
values[105]	73	1			T650	6		T753	1		T746	1
values[106]	47	1			T650	1		T753	1		T746	1
values[107]	67	1			T650	2		T753	1		T746	1
values[108]	75	1			T650	4		T753	1		T746	1
values[109]	57	1			T650	1		T753	1		T746	1
values[110]	64	1			T650	2		T753	1		T746	1
values[111]	61	1			T650	1		T753	2		T746	1
values[112]	85	1			T650	1		T753	1		T746	2
values[113]	68	1			T650	4		T753	2		T746	1
values[114]	69	1			T650	4		T753	4		T746	2
values[115]	63	1			T650	5		T753	1		T746	1
values[116]	72	1			T650	4		T753	1		T746	2
values[117]	71	1			T650	5		T753	2		T746	2
values[118]	73	1			T650	5		T753	3		T746	3
values[119]	65	1			T650	4		T753	1		T746	2
values[120]	76	1			T650	4		T753	1		T746	2
values[121]	71	1			T650	7		T753	1		T746	2
values[122]	84	1			T650	7		T753	1		T746	1
values[123]	104	1			T650	4		T753	3		T746	1
values[124]	155	1			T650	14		T753	3		T746	3
values[125]	242	1			T650	48		T753	3		T746	3
values[126]	475	1			T650	52		T753	14		T746	10
values[127]	2299	1			T650	31		T753	121		T746	127
values[128]	4246	1			T650	2		T753	251		T746	220