Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.78	95.37	94.46	98.06		95.24	97.93	99.61

Total tests in report: 2866

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
42.25	42.25	63.46	63.46	57.26	57.26	43.89	43.89			65.77	65.77	21.00	21.00	2.13	2.13	/workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.1619404061
57.66	15.41	75.09	11.62	75.72	18.46	51.40	7.51			83.82	18.05	57.81	36.80	2.13	0.00	/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.73001729
63.15	5.49	76.33	1.25	77.39	1.68	51.50	0.10			85.68	1.86	85.69	27.88	2.32	0.19	/workspace/coverage/default/2.chip_jtag_csr_rw.664826368
68.22	5.07	82.07	5.74	78.41	1.02	58.35	6.85			85.76	0.07	85.69	0.00	19.03	16.71	/workspace/coverage/cover_reg_top/40.xbar_stress_all_with_reset_error.1550630883
72.82	4.60	83.58	1.51	78.79	0.37	78.99	20.64			86.01	0.26	90.52	4.83	19.03	0.00	/workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.2702879788
76.84	4.02	83.58	0.00	78.79	0.00	78.99	0.00			86.01	0.00	90.52	0.00	43.14	24.12	/workspace/coverage/cover_reg_top/58.xbar_access_same_device_slow_rsp.820680987
79.26	2.42	83.58	0.00	78.85	0.07	78.99	0.00			86.01	0.00	90.52	0.00	57.58	14.44	/workspace/coverage/cover_reg_top/44.xbar_access_same_device_slow_rsp.4287793034
81.16	1.91	89.51	5.93	81.24	2.39	79.34	0.35			88.78	2.77	90.52	0.00	57.58	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_0.3727272001
83.04	1.87	89.51	0.00	81.24	0.00	79.34	0.00			88.78	0.00	90.52	0.00	68.81	11.23	/workspace/coverage/cover_reg_top/38.xbar_access_same_device_slow_rsp.1991753711
84.57	1.53	89.51	0.00	81.24	0.00	79.34	0.00			88.78	0.00	90.52	0.00	78.02	9.21	/workspace/coverage/cover_reg_top/26.xbar_access_same_device_slow_rsp.3858487802
86.04	1.47	89.63	0.12	81.32	0.08	87.02	7.67			88.98	0.20	91.26	0.74	78.02	0.00	/workspace/coverage/default/1.rom_raw_unlock.2742508326
86.90	0.86	90.30	0.67	83.56	2.24	87.04	0.03			91.23	2.25	91.26	0.00	78.02	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1274868665
87.70	0.79	90.30	0.00	84.14	0.58	87.04	0.00			91.27	0.03	91.26	0.00	82.16	4.14	/workspace/coverage/cover_reg_top/73.xbar_stress_all.2887458070
88.46	0.76	90.57	0.27	84.23	0.09	87.06	0.02			91.37	0.11	95.35	4.09	82.16	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.753552964
89.13	0.67	90.74	0.17	84.31	0.08	90.13	3.07			91.50	0.13	95.91	0.56	82.16	0.00	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.4025251795
89.74	0.62	90.74	0.00	84.39	0.09	90.13	0.00			91.50	0.00	95.91	0.00	85.78	3.62	/workspace/coverage/cover_reg_top/39.xbar_access_same_device_slow_rsp.64044254
90.33	0.59	91.82	1.08	85.44	1.05	90.30	0.17			92.74	1.24	95.91	0.00	85.78	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_20.2522973693
90.85	0.51	91.82	0.00	85.44	0.00	90.30	0.00			92.74	0.00	95.91	0.00	88.86	3.08	/workspace/coverage/cover_reg_top/8.xbar_access_same_device_slow_rsp.1490364717
91.34	0.50	91.83	0.01	87.44	2.00	90.83	0.53			92.74	0.00	95.91	0.00	89.31	0.45	/workspace/coverage/cover_reg_top/25.chip_tl_errors.131602413
91.79	0.44	91.83	0.00	87.44	0.00	90.83	0.00			92.74	0.00	95.91	0.00	91.96	2.65	/workspace/coverage/cover_reg_top/2.xbar_access_same_device.3486673421
92.22	0.43	92.56	0.73	88.13	0.68	91.01	0.18			93.55	0.81	96.10	0.19	91.96	0.00	/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.3735955008
92.61	0.39	93.08	0.52	89.64	1.51	91.13	0.12			93.61	0.06	96.10	0.00	92.10	0.14	/workspace/coverage/cover_reg_top/6.chip_same_csr_outstanding.572693301
92.94	0.33	93.17	0.09	89.69	0.05	92.19	1.06			93.66	0.05	96.10	0.00	92.80	0.71	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.851498705
93.20	0.27	93.72	0.54	90.18	0.50	92.29	0.10			94.13	0.47	96.10	0.00	92.80	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_10.3099080409
93.46	0.26	93.72	0.00	90.18	0.00	93.86	1.57			94.13	0.00	96.10	0.00	92.80	0.00	/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.864747777
93.71	0.24	93.72	0.00	90.27	0.09	93.86	0.00			94.16	0.03	96.10	0.00	94.13	1.33	/workspace/coverage/cover_reg_top/92.xbar_random.2280689251
93.93	0.22	93.91	0.19	90.60	0.33	93.87	0.01			94.41	0.25	96.65	0.56	94.13	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_retention.3064242440
94.14	0.21	93.91	0.00	90.70	0.10	93.87	0.00			94.41	0.00	96.65	0.00	95.32	1.19	/workspace/coverage/cover_reg_top/22.xbar_stress_all.752790241
94.33	0.18	93.91	0.00	91.79	1.10	93.87	0.00			94.41	0.00	96.65	0.00	95.33	0.01	/workspace/coverage/cover_reg_top/21.chip_tl_errors.1549171199
94.51	0.18	93.91	0.00	91.80	0.01	93.87	0.00			94.41	0.00	96.65	0.00	96.43	1.09	/workspace/coverage/cover_reg_top/41.xbar_stress_all_with_reset_error.2735706439
94.65	0.14	93.91	0.00	91.81	0.01	93.87	0.00			94.41	0.00	96.65	0.00	97.26	0.83	/workspace/coverage/cover_reg_top/4.xbar_random_large_delays.259185782
94.78	0.13	94.13	0.22	91.85	0.04	94.10	0.24			94.42	0.01	96.84	0.19	97.35	0.09	/workspace/coverage/default/94.chip_sw_all_escalation_resets.2818148806
94.91	0.13	94.36	0.23	92.12	0.26	94.38	0.27			94.42	0.00	96.84	0.00	97.35	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2011391697
95.02	0.11	94.36	0.00	92.12	0.00	95.06	0.68			94.42	0.00	96.84	0.00	97.35	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.2895278100
95.14	0.11	94.41	0.05	92.43	0.31	95.06	0.01			94.73	0.31	96.84	0.00	97.35	0.00	/workspace/coverage/default/1.chip_jtag_csr_rw.337480184
95.23	0.09	94.41	0.00	92.43	0.00	95.61	0.55			94.73	0.00	96.84	0.00	97.35	0.00	/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.1188942948
95.31	0.08	94.41	0.00	92.45	0.03	96.05	0.44			94.73	0.00	96.84	0.00	97.35	0.00	/workspace/coverage/default/0.chip_sw_entropy_src_csrng.516588721
95.38	0.07	94.41	0.00	92.45	0.00	96.48	0.43			94.73	0.00	96.84	0.00	97.35	0.00	/workspace/coverage/default/63.chip_sw_all_escalation_resets.3736499777
95.45	0.07	94.41	0.00	92.48	0.03	96.48	0.00			94.73	0.00	96.84	0.00	97.74	0.39	/workspace/coverage/cover_reg_top/89.xbar_access_same_device_slow_rsp.2985405125
95.51	0.07	94.42	0.02	92.52	0.03	96.49	0.01			94.73	0.00	96.84	0.00	98.08	0.34	/workspace/coverage/default/0.chip_sw_alert_test.873897206
95.57	0.05	94.42	0.00	92.84	0.33	96.49	0.00			94.73	0.00	96.84	0.00	98.08	0.00	/workspace/coverage/cover_reg_top/0.chip_tl_errors.4037344330
95.62	0.05	94.42	0.00	92.84	0.00	96.80	0.31			94.73	0.00	96.84	0.00	98.08	0.00	/workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.2128474888
95.67	0.05	94.42	0.00	92.99	0.14	96.80	0.00			94.89	0.16	96.84	0.00	98.08	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.2960025390
95.72	0.05	94.42	0.00	93.00	0.01	96.80	0.00			94.89	0.00	96.84	0.00	98.35	0.27	/workspace/coverage/cover_reg_top/54.xbar_stress_all.814907288
95.77	0.05	94.45	0.03	93.03	0.03	96.83	0.02			94.91	0.02	97.03	0.19	98.35	0.00	/workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.543013390
95.81	0.04	94.62	0.17	93.10	0.07	96.83	0.01			94.91	0.00	97.03	0.00	98.35	0.00	/workspace/coverage/default/0.chip_sw_gpio.3651978857
95.85	0.04	94.64	0.01	93.11	0.01	96.83	0.00			94.94	0.02	97.21	0.19	98.37	0.01	/workspace/coverage/default/20.chip_sw_all_escalation_resets.3184162106
95.89	0.04	94.65	0.01	93.13	0.01	96.84	0.01			94.94	0.01	97.40	0.19	98.38	0.01	/workspace/coverage/default/28.chip_sw_all_escalation_resets.3673731279
95.93	0.04	94.65	0.01	93.14	0.01	96.85	0.01			94.95	0.01	97.58	0.19	98.39	0.01	/workspace/coverage/default/22.chip_sw_all_escalation_resets.1129411549
95.97	0.04	94.65	0.01	93.15	0.01	96.88	0.03			94.95	0.00	97.77	0.19	98.39	0.00	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3096698554
96.00	0.03	94.66	0.01	93.35	0.20	96.88	0.01			94.95	0.00	97.77	0.00	98.39	0.00	/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.8350631
96.03	0.03	94.66	0.00	93.35	0.00	97.08	0.20			94.95	0.00	97.77	0.00	98.39	0.00	/workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.4204834430
96.07	0.03	94.67	0.01	93.36	0.01	97.26	0.18			94.95	0.00	97.77	0.00	98.39	0.00	/workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.2251456117
96.10	0.03	94.67	0.00	93.36	0.00	97.27	0.01			94.95	0.00	97.96	0.19	98.39	0.00	/workspace/coverage/default/2.chip_sw_data_integrity_escalation.402484788
96.12	0.03	94.67	0.00	93.43	0.07	97.27	0.00			95.03	0.08	97.96	0.00	98.39	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.731675160
96.15	0.03	94.71	0.05	93.46	0.03	97.28	0.01			95.10	0.07	97.96	0.00	98.39	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.3502014223
96.17	0.02	94.78	0.07	93.51	0.05	97.29	0.01			95.12	0.02	97.96	0.00	98.39	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.2571303606
96.20	0.02	94.83	0.04	93.55	0.04	97.32	0.03			95.14	0.02	97.96	0.00	98.39	0.00	/workspace/coverage/default/0.chip_jtag_csr_rw.1219205934
96.22	0.02	94.83	0.00	93.55	0.00	97.32	0.00			95.14	0.00	97.96	0.00	98.53	0.14	/workspace/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.48743374
96.24	0.02	94.90	0.08	93.55	0.00	97.37	0.05			95.15	0.01	97.96	0.00	98.53	0.00	/workspace/coverage/default/0.chip_tap_straps_rma.2142599608
96.26	0.02	94.90	0.00	93.68	0.13	97.37	0.00			95.15	0.00	97.96	0.00	98.53	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_0.602131144
96.28	0.02	94.96	0.06	93.72	0.05	97.37	0.00			95.17	0.02	97.96	0.00	98.53	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_wake.1384204408
96.30	0.02	94.96	0.00	93.84	0.12	97.37	0.00			95.17	0.00	97.96	0.00	98.53	0.00	/workspace/coverage/cover_reg_top/16.chip_tl_errors.2392212654
96.32	0.02	94.96	0.00	93.88	0.04	97.42	0.05			95.18	0.02	97.96	0.00	98.53	0.00	/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.3322578296
96.34	0.02	94.96	0.00	93.89	0.01	97.52	0.11			95.18	0.00	97.96	0.00	98.53	0.00	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2724791220
96.35	0.01	94.98	0.03	93.89	0.01	97.57	0.05			95.18	0.00	97.96	0.00	98.53	0.00	/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.40819099
96.36	0.01	94.98	0.00	93.89	0.00	97.64	0.07			95.18	0.00	97.96	0.00	98.53	0.00	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.2213390843
96.38	0.01	94.98	0.00	93.89	0.00	97.64	0.00			95.18	0.00	97.96	0.00	98.60	0.07	/workspace/coverage/cover_reg_top/25.xbar_stress_all_with_rand_reset.1154114110
96.39	0.01	94.98	0.00	93.90	0.01	97.68	0.04			95.18	0.00	97.96	0.00	98.61	0.01	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.211370472
96.40	0.01	94.98	0.00	93.96	0.05	97.68	0.00			95.18	0.00	97.96	0.00	98.61	0.00	/workspace/coverage/cover_reg_top/4.chip_tl_errors.3232554150
96.40	0.01	94.98	0.00	94.01	0.05	97.68	0.00			95.18	0.00	97.96	0.00	98.61	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_20.1348504393
96.41	0.01	94.98	0.00	94.01	0.00	97.73	0.05			95.18	0.00	97.96	0.00	98.61	0.00	/workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.3304020447
96.42	0.01	94.99	0.01	94.02	0.01	97.77	0.03			95.19	0.01	97.96	0.00	98.61	0.00	/workspace/coverage/default/0.chip_sw_usbdev_pincfg.1430734197
96.43	0.01	94.99	0.00	94.02	0.01	97.77	0.00			95.19	0.00	97.96	0.00	98.66	0.05	/workspace/coverage/cover_reg_top/88.xbar_stress_all_with_error.1015450890
96.44	0.01	95.01	0.02	94.03	0.01	97.77	0.00			95.21	0.02	97.96	0.00	98.66	0.00	/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.1415198447
96.45	0.01	95.01	0.00	94.07	0.04	97.77	0.01			95.21	0.00	97.96	0.00	98.66	0.00	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops.2969949873
96.45	0.01	95.01	0.00	94.11	0.04	97.77	0.00			95.21	0.00	97.96	0.00	98.66	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_10.1107513898
96.46	0.01	95.01	0.00	94.11	0.00	97.81	0.04			95.21	0.00	97.96	0.00	98.66	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.3550074736
96.47	0.01	95.02	0.01	94.12	0.01	97.82	0.01			95.22	0.02	97.96	0.00	98.66	0.00	/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.3886195446
96.47	0.01	95.02	0.00	94.16	0.04	97.82	0.00			95.22	0.00	97.96	0.00	98.66	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_20.993925314
96.48	0.01	95.02	0.00	94.20	0.04	97.82	0.00			95.22	0.00	97.96	0.00	98.66	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_0.2550790458
96.49	0.01	95.02	0.00	94.20	0.00	97.82	0.00			95.22	0.00	97.96	0.00	98.69	0.04	/workspace/coverage/cover_reg_top/4.xbar_stress_all_with_reset_error.2051231678
96.49	0.01	95.02	0.00	94.20	0.00	97.82	0.00			95.22	0.00	97.96	0.00	98.73	0.04	/workspace/coverage/cover_reg_top/79.xbar_stress_all_with_reset_error.1478734206
96.50	0.01	95.04	0.02	94.20	0.00	97.83	0.01			95.22	0.00	97.96	0.00	98.73	0.00	/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.3940141443
96.50	0.01	95.04	0.00	94.21	0.01	97.85	0.02			95.22	0.00	97.96	0.00	98.73	0.00	/workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.192113175
96.51	0.01	95.04	0.00	94.21	0.00	97.88	0.03			95.22	0.00	97.96	0.00	98.73	0.00	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.237299641
96.51	0.01	95.04	0.00	94.21	0.00	97.91	0.03			95.22	0.00	97.96	0.00	98.73	0.00	/workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.3369429771
96.52	0.01	95.04	0.01	94.21	0.01	97.93	0.02			95.22	0.00	97.96	0.00	98.73	0.00	/workspace/coverage/default/0.rom_e2e_shutdown_output.3672933235
96.52	0.01	95.04	0.00	94.22	0.01	97.93	0.00			95.22	0.00	97.96	0.00	98.75	0.02	/workspace/coverage/cover_reg_top/67.xbar_stress_all_with_rand_reset.3892197981
96.53	0.01	95.04	0.00	94.22	0.01	97.93	0.00			95.22	0.00	97.96	0.00	98.78	0.02	/workspace/coverage/cover_reg_top/96.xbar_stress_all_with_reset_error.238098117
96.53	0.01	95.04	0.00	94.24	0.03	97.93	0.00			95.22	0.00	97.96	0.00	98.78	0.00	/workspace/coverage/cover_reg_top/1.chip_tl_errors.2336386674
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96.72	0.01	95.10	0.00	94.39	0.00	98.02	0.00			95.23	0.01	97.96	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.791080168
96.72	0.01	95.10	0.00	94.39	0.00	98.02	0.00			95.24	0.01	97.96	0.00	99.61	0.00	/workspace/coverage/default/0.chip_tap_straps_dev.968502774
96.72	0.01	95.10	0.00	94.39	0.01	98.02	0.00			95.24	0.00	97.96	0.00	99.61	0.00	/workspace/coverage/cover_reg_top/10.chip_tl_errors.3837373037
96.72	0.01	95.10	0.00	94.40	0.01	98.02	0.00			95.24	0.00	97.96	0.00	99.61	0.00	/workspace/coverage/cover_reg_top/26.xbar_stress_all_with_reset_error.1011554471
96.72	0.01	95.10	0.00	94.41	0.01	98.02	0.00			95.24	0.00	97.96	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_spi_device_tx_rx.3277370313
96.72	0.01	95.11	0.01	94.41	0.00	98.02	0.00			95.24	0.00	97.96	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.2055778230
96.72	0.01	95.11	0.01	94.41	0.00	98.02	0.00			95.24	0.00	97.96	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.2570236143
96.72	0.01	95.11	0.00	94.41	0.00	98.02	0.01			95.24	0.00	97.96	0.00	99.61	0.00	/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.1079485667
96.73	0.01	95.11	0.00	94.41	0.00	98.02	0.01			95.24	0.00	97.96	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_edn_boot_mode.416033313
96.73	0.01	95.11	0.00	94.41	0.00	98.03	0.01			95.24	0.00	97.96	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.715364422
96.73	0.01	95.11	0.00	94.41	0.00	98.03	0.01			95.24	0.00	97.96	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.1645820675
96.73	0.01	95.11	0.00	94.41	0.00	98.04	0.01			95.24	0.00	97.96	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.33032167
96.73	0.01	95.11	0.00	94.41	0.00	98.04	0.01			95.24	0.00	97.96	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2788779556
96.73	0.01	95.11	0.00	94.41	0.00	98.05	0.01			95.24	0.00	97.96	0.00	99.61	0.00	/workspace/coverage/default/1.chip_sw_flash_init.1134363290
96.73	0.01	95.11	0.00	94.41	0.00	98.05	0.01			95.24	0.00	97.96	0.00	99.61	0.00	/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.1359986362
96.73	0.01	95.11	0.00	94.41	0.01	98.05	0.00			95.24	0.00	97.96	0.00	99.61	0.00	/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.1563529700
96.73	0.01	95.11	0.00	94.41	0.01	98.05	0.00			95.24	0.00	97.96	0.00	99.61	0.00	/workspace/coverage/cover_reg_top/18.xbar_stress_all_with_rand_reset.852593028
96.73	0.01	95.11	0.00	94.42	0.01	98.05	0.00			95.24	0.00	97.96	0.00	99.61	0.00	/workspace/coverage/cover_reg_top/24.xbar_stress_all_with_reset_error.2477280424
96.73	0.01	95.11	0.00	94.42	0.01	98.05	0.00			95.24	0.00	97.96	0.00	99.61	0.00	/workspace/coverage/cover_reg_top/3.chip_tl_errors.189330455
96.73	0.01	95.11	0.00	94.43	0.01	98.05	0.00			95.24	0.00	97.96	0.00	99.61	0.00	/workspace/coverage/cover_reg_top/38.xbar_stress_all_with_error.141712460
96.73	0.01	95.11	0.00	94.43	0.01	98.05	0.00			95.24	0.00	97.96	0.00	99.61	0.00	/workspace/coverage/cover_reg_top/47.xbar_stress_all_with_reset_error.113177598
96.73	0.01	95.11	0.00	94.43	0.01	98.05	0.00			95.24	0.00	97.96	0.00	99.61	0.00	/workspace/coverage/cover_reg_top/54.xbar_stress_all_with_reset_error.1535547220
96.74	0.01	95.11	0.00	94.44	0.01	98.05	0.00			95.24	0.00	97.96	0.00	99.61	0.00	/workspace/coverage/cover_reg_top/59.xbar_stress_all_with_reset_error.1309895430
96.74	0.01	95.11	0.00	94.44	0.01	98.05	0.00			95.24	0.00	97.96	0.00	99.61	0.00	/workspace/coverage/cover_reg_top/99.xbar_stress_all_with_error.428376668
96.74	0.01	95.11	0.00	94.44	0.01	98.05	0.00			95.24	0.00	97.96	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_aon_timer_irq.2512361683
96.74	0.01	95.11	0.00	94.45	0.01	98.05	0.00			95.24	0.00	97.96	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.825981763
96.74	0.01	95.11	0.00	94.45	0.01	98.05	0.00			95.24	0.00	97.96	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.1722307118
96.74	0.01	95.11	0.00	94.45	0.01	98.05	0.00			95.24	0.00	97.96	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.3523370632
96.74	0.01	95.11	0.00	94.46	0.01	98.05	0.00			95.24	0.00	97.96	0.00	99.61	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_10.652135844
96.74	0.01	95.12	0.01	94.46	0.00	98.05	0.00			95.24	0.00	97.96	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_power_idle_load.2740979932
96.74	0.01	95.12	0.00	94.46	0.00	98.06	0.01			95.24	0.00	97.96	0.00	99.61	0.00	/workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.1651352902
96.74	0.01	95.12	0.00	94.46	0.00	98.06	0.01			95.24	0.00	97.96	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.3321754571
96.74	0.01	95.12	0.00	94.46	0.00	98.06	0.01			95.24	0.00	97.96	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.2202862272
96.74	0.01	95.12	0.00	94.46	0.00	98.06	0.01			95.24	0.00	97.96	0.00	99.61	0.00	/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.3628745362
96.74	0.01	95.12	0.00	94.46	0.00	98.06	0.01			95.24	0.00	97.96	0.00	99.61	0.00	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.1264636332

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.2175984178
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.1675897631
/workspace/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.1470599588
/workspace/coverage/cover_reg_top/0.chip_csr_rw.1335746711
/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.1369981120
/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.3318144942
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.2875829452
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.2333933504
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.1236283557
/workspace/coverage/cover_reg_top/0.xbar_error_random.3014018128
/workspace/coverage/cover_reg_top/0.xbar_random.827087267
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.4002388787
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.3544452596
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.2072177342
/workspace/coverage/cover_reg_top/0.xbar_same_source.3800800757
/workspace/coverage/cover_reg_top/0.xbar_smoke.2154016376
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.3965731043
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.4104048927
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.2635506148
/workspace/coverage/cover_reg_top/0.xbar_stress_all.509576869
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.3335444488
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.1635201469
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.223232388
/workspace/coverage/cover_reg_top/1.chip_csr_aliasing.415109199
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.3337942274
/workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.1592714590
/workspace/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.1184263848
/workspace/coverage/cover_reg_top/1.chip_csr_rw.3710403590
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.354428886
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.2963948438
/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.1374553430
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.2340670936
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.1389052169
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.1489857906
/workspace/coverage/cover_reg_top/1.xbar_error_random.2507488191
/workspace/coverage/cover_reg_top/1.xbar_random.2468265468
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.4167391136
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.4286741369
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.3454277099
/workspace/coverage/cover_reg_top/1.xbar_same_source.2009610712
/workspace/coverage/cover_reg_top/1.xbar_smoke.1663994951
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.4174618278
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.2467134554
/workspace/coverage/cover_reg_top/1.xbar_stress_all.994827600
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.3391199290
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.1655078102
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.690733611
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.1778510330
/workspace/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.2071690847
/workspace/coverage/cover_reg_top/10.chip_csr_rw.3188405269
/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.1680186271
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.1093255239
/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.3293493182
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.273190411
/workspace/coverage/cover_reg_top/10.xbar_error_random.2867893504
/workspace/coverage/cover_reg_top/10.xbar_random.2029255005
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.2830139738
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.3951108280
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.826270602
/workspace/coverage/cover_reg_top/10.xbar_same_source.1789654197
/workspace/coverage/cover_reg_top/10.xbar_smoke.2551465208
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.4008512589
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.2129208819
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.730786787
/workspace/coverage/cover_reg_top/10.xbar_stress_all.1875004768
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.2395403292
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.210167180
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.3721907442
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.4194302958
/workspace/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.2620125540
/workspace/coverage/cover_reg_top/11.chip_csr_rw.2760184910
/workspace/coverage/cover_reg_top/11.chip_tl_errors.3130818887
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.2539071744
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.1706183405
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.2873903387
/workspace/coverage/cover_reg_top/11.xbar_error_random.1634066293
/workspace/coverage/cover_reg_top/11.xbar_random.3404664303
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.3974458938
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.3693819058
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.2214264995
/workspace/coverage/cover_reg_top/11.xbar_same_source.3648680130
/workspace/coverage/cover_reg_top/11.xbar_smoke.1653711189
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.3133770776
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.4054334163
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.1039693246
/workspace/coverage/cover_reg_top/11.xbar_stress_all.2583285060
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.2392041463
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.285213823
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.3158176246
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.51355382
/workspace/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.368553640
/workspace/coverage/cover_reg_top/12.chip_csr_rw.1579608931
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.1597902841
/workspace/coverage/cover_reg_top/12.chip_tl_errors.2405207779
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.2189951611
/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.1959605223
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.2184167009
/workspace/coverage/cover_reg_top/12.xbar_error_random.1670171984
/workspace/coverage/cover_reg_top/12.xbar_random.2306109654
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.537774415
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.2256520449
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.2957806639
/workspace/coverage/cover_reg_top/12.xbar_same_source.2377210106
/workspace/coverage/cover_reg_top/12.xbar_smoke.3013968924
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.1242221589
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.2389716130
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.783434032
/workspace/coverage/cover_reg_top/12.xbar_stress_all.3154676077
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.1152806547
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.1070607619
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.398043394
/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.122477041
/workspace/coverage/cover_reg_top/13.chip_csr_mem_rw_with_rand_reset.331628305
/workspace/coverage/cover_reg_top/13.chip_csr_rw.1774001581
/workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.1023002078
/workspace/coverage/cover_reg_top/13.chip_tl_errors.3465071116
/workspace/coverage/cover_reg_top/13.xbar_access_same_device.2535637046
/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.1843195949
/workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.2622529056
/workspace/coverage/cover_reg_top/13.xbar_error_random.790901112
/workspace/coverage/cover_reg_top/13.xbar_random.2807884176
/workspace/coverage/cover_reg_top/13.xbar_random_large_delays.941319834
/workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.3387189021
/workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.2339751765
/workspace/coverage/cover_reg_top/13.xbar_same_source.1611850198
/workspace/coverage/cover_reg_top/13.xbar_smoke.253924291
/workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.3637249514
/workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.4170273373
/workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.1719711789
/workspace/coverage/cover_reg_top/13.xbar_stress_all.572493233
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.2907545045
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.1298215605
/workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.2955776873
/workspace/coverage/cover_reg_top/14.chip_csr_mem_rw_with_rand_reset.1574595680
/workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.3667972777
/workspace/coverage/cover_reg_top/14.chip_tl_errors.1203682825
/workspace/coverage/cover_reg_top/14.xbar_access_same_device.1495291567
/workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.1851112002
/workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.1186199278
/workspace/coverage/cover_reg_top/14.xbar_error_random.3743270809
/workspace/coverage/cover_reg_top/14.xbar_random.4206446878
/workspace/coverage/cover_reg_top/14.xbar_random_large_delays.301608780
/workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.1693385090
/workspace/coverage/cover_reg_top/14.xbar_random_zero_delays.1556848619
/workspace/coverage/cover_reg_top/14.xbar_same_source.3247850636
/workspace/coverage/cover_reg_top/14.xbar_smoke.3922395029
/workspace/coverage/cover_reg_top/14.xbar_smoke_large_delays.1467072755
/workspace/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.2746891828
/workspace/coverage/cover_reg_top/14.xbar_smoke_zero_delays.3179985130
/workspace/coverage/cover_reg_top/14.xbar_stress_all.616233500
/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_error.3333215686
/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.845394169
/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.4223693137
/workspace/coverage/cover_reg_top/14.xbar_unmapped_addr.1567048105
/workspace/coverage/cover_reg_top/15.chip_csr_mem_rw_with_rand_reset.3541470570
/workspace/coverage/cover_reg_top/15.chip_csr_rw.3501483586
/workspace/coverage/cover_reg_top/15.chip_same_csr_outstanding.3514890506
/workspace/coverage/cover_reg_top/15.chip_tl_errors.1313054800
/workspace/coverage/cover_reg_top/15.xbar_access_same_device.55356532
/workspace/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.736204321
/workspace/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.2626968026
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/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.34522368
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.4151437153
/workspace/coverage/default/3.chip_tap_straps_dev.3480313256
/workspace/coverage/default/3.chip_tap_straps_prod.1513597526
/workspace/coverage/default/3.chip_tap_straps_rma.2172037516
/workspace/coverage/default/3.chip_tap_straps_testunlock0.262488870
/workspace/coverage/default/30.chip_sw_all_escalation_resets.3022888089
/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.3948422288
/workspace/coverage/default/32.chip_sw_all_escalation_resets.1623908767
/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.2482014571
/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.1421789573
/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.1689995336
/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.458097214
/workspace/coverage/default/37.chip_sw_all_escalation_resets.644550399
/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.3090070636
/workspace/coverage/default/38.chip_sw_all_escalation_resets.1603224857
/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.1505131662
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.3693862089
/workspace/coverage/default/4.chip_sw_data_integrity_escalation.3483565432
/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.3006542862
/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.1122589348
/workspace/coverage/default/4.chip_sw_uart_tx_rx.1674185457
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.4136909103
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.776696050
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.4276624437
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.3502140140
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.2036219918
/workspace/coverage/default/4.chip_tap_straps_dev.1557431260
/workspace/coverage/default/4.chip_tap_straps_prod.2665568890
/workspace/coverage/default/4.chip_tap_straps_rma.854469999
/workspace/coverage/default/4.chip_tap_straps_testunlock0.2802805631
/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.1347645300
/workspace/coverage/default/41.chip_sw_all_escalation_resets.4024802836
/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.3744831744
/workspace/coverage/default/44.chip_sw_all_escalation_resets.159761328
/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.2793384353
/workspace/coverage/default/45.chip_sw_all_escalation_resets.3943874369
/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.817941856
/workspace/coverage/default/47.chip_sw_all_escalation_resets.196208017
/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.3429031189
/workspace/coverage/default/48.chip_sw_all_escalation_resets.3359495220
/workspace/coverage/default/49.chip_sw_all_escalation_resets.2768330648
/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.3742752849
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.3279139840
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.3725846239
/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.178111593
/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.1037180105
/workspace/coverage/default/51.chip_sw_all_escalation_resets.1011074105
/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.1196025306
/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.3835382973
/workspace/coverage/default/53.chip_sw_all_escalation_resets.1640382218
/workspace/coverage/default/54.chip_sw_all_escalation_resets.1655749699
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.1628326345
/workspace/coverage/default/55.chip_sw_all_escalation_resets.3755417791
/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.1417687782
/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.3461631873
/workspace/coverage/default/57.chip_sw_all_escalation_resets.619117135
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.2428387454
/workspace/coverage/default/58.chip_sw_all_escalation_resets.3157476525
/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.4113459293
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.3683500595
/workspace/coverage/default/6.chip_sw_all_escalation_resets.2643742232
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.1222906885
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.3379410672
/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.2445306776
/workspace/coverage/default/60.chip_sw_all_escalation_resets.2434136459
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.550887892
/workspace/coverage/default/61.chip_sw_all_escalation_resets.1704464207
/workspace/coverage/default/62.chip_sw_all_escalation_resets.3825824674
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.3770048281
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.1368109697
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.2601573564
/workspace/coverage/default/65.chip_sw_all_escalation_resets.1215444425
/workspace/coverage/default/66.chip_sw_all_escalation_resets.3665191656
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.712169585
/workspace/coverage/default/67.chip_sw_all_escalation_resets.2577397976
/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.624613964
/workspace/coverage/default/68.chip_sw_all_escalation_resets.3599025469
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.1025201259
/workspace/coverage/default/69.chip_sw_all_escalation_resets.792261439
/workspace/coverage/default/7.chip_sw_all_escalation_resets.3170492797
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.1992040827
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.604657469
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.843960602
/workspace/coverage/default/70.chip_sw_all_escalation_resets.3734766318
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.1814509093
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.3500214064
/workspace/coverage/default/72.chip_sw_all_escalation_resets.2653481810
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.939998735
/workspace/coverage/default/73.chip_sw_all_escalation_resets.778933221
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.4081528793
/workspace/coverage/default/74.chip_sw_all_escalation_resets.42338545
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.2155592374
/workspace/coverage/default/75.chip_sw_all_escalation_resets.1759917065
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.2570582715
/workspace/coverage/default/76.chip_sw_all_escalation_resets.1871677346
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.2738063129
/workspace/coverage/default/77.chip_sw_all_escalation_resets.241728093
/workspace/coverage/default/78.chip_sw_all_escalation_resets.1032727511
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.2168369390
/workspace/coverage/default/79.chip_sw_all_escalation_resets.1024789718
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.885375767
/workspace/coverage/default/8.chip_sw_all_escalation_resets.3968190392
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.3951823314
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.3440666963
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.1709652788
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.3811065190
/workspace/coverage/default/81.chip_sw_all_escalation_resets.3557008740
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.3461514043
/workspace/coverage/default/82.chip_sw_all_escalation_resets.3184588667
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.1627914011
/workspace/coverage/default/83.chip_sw_all_escalation_resets.4223596972
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.57324199
/workspace/coverage/default/84.chip_sw_all_escalation_resets.2658238744
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.1976971679
/workspace/coverage/default/85.chip_sw_all_escalation_resets.3469458678
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.903407927
/workspace/coverage/default/87.chip_sw_all_escalation_resets.3831455636
/workspace/coverage/default/88.chip_sw_all_escalation_resets.1594949307
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.2508533165
/workspace/coverage/default/89.chip_sw_all_escalation_resets.1322288410
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.544926534
/workspace/coverage/default/9.chip_sw_all_escalation_resets.1737833541
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.2281564705
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.1177547783
/workspace/coverage/default/90.chip_sw_all_escalation_resets.1567490799
/workspace/coverage/default/91.chip_sw_all_escalation_resets.2861076988
/workspace/coverage/default/92.chip_sw_all_escalation_resets.621420705
/workspace/coverage/default/95.chip_sw_all_escalation_resets.2568167506
/workspace/coverage/default/96.chip_sw_all_escalation_resets.1014199855
/workspace/coverage/default/97.chip_sw_all_escalation_resets.116390445
/workspace/coverage/default/98.chip_sw_all_escalation_resets.2023090926
/workspace/coverage/default/99.chip_sw_all_escalation_resets.638266142
/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.1398259029
/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.1830091438
/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.1800781015
/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.1356422212
/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.3239602668
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.1336392527
/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.1830168473
/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.2502822861

---

Total test records in report: 2866

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tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html | tests35.html | tests36.html | tests37.html | tests38.html | tests39.html | tests40.html | tests41.html | tests42.html | tests43.html | tests44.html | tests45.html | tests46.html | tests47.html | tests48.html | tests49.html | tests50.html | tests51.html | tests52.html | tests53.html | tests54.html | tests55.html | tests56.html | tests57.html | tests58.html | tests59.html | tests60.html

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T31	/workspace/coverage/cover_reg_top/83.xbar_random_zero_delays.4055114381			Jan 17 04:29:19 PM PST 24	Jan 17 04:30:00 PM PST 24	444778674 ps
T32	/workspace/coverage/cover_reg_top/4.xbar_random_large_delays.259185782			Jan 17 04:18:39 PM PST 24	Jan 17 04:37:01 PM PST 24	106130275853 ps
T28	/workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.1619404061			Jan 17 04:18:47 PM PST 24	Jan 17 04:22:42 PM PST 24	3876975697 ps
T53	/workspace/coverage/cover_reg_top/56.xbar_random_zero_delays.3977161270			Jan 17 04:25:31 PM PST 24	Jan 17 04:26:17 PM PST 24	465870520 ps
T54	/workspace/coverage/cover_reg_top/63.xbar_random_large_delays.3552313490			Jan 17 04:26:36 PM PST 24	Jan 17 04:28:33 PM PST 24	10883747555 ps
T221	/workspace/coverage/cover_reg_top/32.xbar_access_same_device.3407249724			Jan 17 04:21:55 PM PST 24	Jan 17 04:23:36 PM PST 24	2430873332 ps
T222	/workspace/coverage/cover_reg_top/92.xbar_random.2280689251			Jan 17 04:30:37 PM PST 24	Jan 17 04:31:02 PM PST 24	270153110 ps
T223	/workspace/coverage/cover_reg_top/92.xbar_error_and_unmapped_addr.1250672361			Jan 17 04:30:48 PM PST 24	Jan 17 04:31:04 PM PST 24	310545037 ps
T102	/workspace/coverage/cover_reg_top/40.xbar_stress_all_with_reset_error.1550630883			Jan 17 04:23:13 PM PST 24	Jan 17 04:28:20 PM PST 24	6286475063 ps
T224	/workspace/coverage/cover_reg_top/34.xbar_unmapped_addr.3183292335			Jan 17 04:22:19 PM PST 24	Jan 17 04:23:06 PM PST 24	328135252 ps
T29	/workspace/coverage/cover_reg_top/25.chip_tl_errors.131602413			Jan 17 04:20:39 PM PST 24	Jan 17 04:24:44 PM PST 24	4168914873 ps
T386	/workspace/coverage/cover_reg_top/46.xbar_smoke_slow_rsp.2615533875			Jan 17 04:24:07 PM PST 24	Jan 17 04:25:36 PM PST 24	5347376725 ps
T385	/workspace/coverage/cover_reg_top/72.xbar_smoke_zero_delays.1708599700			Jan 17 04:27:43 PM PST 24	Jan 17 04:27:49 PM PST 24	41814493 ps
T339	/workspace/coverage/cover_reg_top/74.xbar_same_source.2091832982			Jan 17 04:28:20 PM PST 24	Jan 17 04:28:34 PM PST 24	150621341 ps
T367	/workspace/coverage/cover_reg_top/88.xbar_error_and_unmapped_addr.2925181139			Jan 17 04:30:09 PM PST 24	Jan 17 04:30:54 PM PST 24	1070833843 ps
T374	/workspace/coverage/cover_reg_top/77.xbar_unmapped_addr.1385229048			Jan 17 04:28:35 PM PST 24	Jan 17 04:28:52 PM PST 24	67802807 ps
T384	/workspace/coverage/cover_reg_top/32.xbar_random_slow_rsp.28014425			Jan 17 04:21:49 PM PST 24	Jan 17 04:29:59 PM PST 24	28042132490 ps
T378	/workspace/coverage/cover_reg_top/15.xbar_unmapped_addr.4268575566			Jan 17 04:19:15 PM PST 24	Jan 17 04:19:25 PM PST 24	41910356 ps
T383	/workspace/coverage/cover_reg_top/80.xbar_random.3142119255			Jan 17 04:28:50 PM PST 24	Jan 17 04:29:00 PM PST 24	164482402 ps
T377	/workspace/coverage/cover_reg_top/94.xbar_unmapped_addr.2860433406			Jan 17 04:31:09 PM PST 24	Jan 17 04:31:17 PM PST 24	21728715 ps
T379	/workspace/coverage/cover_reg_top/4.xbar_smoke_zero_delays.43843673			Jan 17 04:18:33 PM PST 24	Jan 17 04:18:40 PM PST 24	46786224 ps
T381	/workspace/coverage/cover_reg_top/44.xbar_error_random.960965425			Jan 17 04:23:52 PM PST 24	Jan 17 04:24:25 PM PST 24	379231633 ps
T382	/workspace/coverage/cover_reg_top/39.xbar_error_and_unmapped_addr.1176277171			Jan 17 04:22:54 PM PST 24	Jan 17 04:23:55 PM PST 24	1281561310 ps
T390	/workspace/coverage/cover_reg_top/7.xbar_smoke_zero_delays.1420541843			Jan 17 04:18:35 PM PST 24	Jan 17 04:18:44 PM PST 24	50284014 ps
T340	/workspace/coverage/cover_reg_top/78.xbar_stress_all.3562407359			Jan 17 04:28:51 PM PST 24	Jan 17 04:30:57 PM PST 24	1603948420 ps
T368	/workspace/coverage/cover_reg_top/96.xbar_random_zero_delays.3331665292			Jan 17 04:31:27 PM PST 24	Jan 17 04:32:27 PM PST 24	591247499 ps
T605	/workspace/coverage/cover_reg_top/80.xbar_access_same_device_slow_rsp.2364631210			Jan 17 04:29:02 PM PST 24	Jan 17 04:30:36 PM PST 24	5323923149 ps
T352	/workspace/coverage/cover_reg_top/54.xbar_stress_all.814907288			Jan 17 04:25:19 PM PST 24	Jan 17 04:29:04 PM PST 24	7236704184 ps
T388	/workspace/coverage/cover_reg_top/39.xbar_access_same_device_slow_rsp.64044254			Jan 17 04:22:52 PM PST 24	Jan 17 04:48:42 PM PST 24	81915338900 ps
T391	/workspace/coverage/cover_reg_top/36.xbar_error_and_unmapped_addr.1435188877			Jan 17 04:22:29 PM PST 24	Jan 17 04:22:40 PM PST 24	70692271 ps
T375	/workspace/coverage/cover_reg_top/55.xbar_random.3621144126			Jan 17 04:25:22 PM PST 24	Jan 17 04:25:47 PM PST 24	551467672 ps
T524	/workspace/coverage/cover_reg_top/73.xbar_smoke.2816336182			Jan 17 04:27:52 PM PST 24	Jan 17 04:28:00 PM PST 24	43043103 ps
T387	/workspace/coverage/cover_reg_top/26.xbar_stress_all_with_reset_error.1011554471			Jan 17 04:21:13 PM PST 24	Jan 17 04:24:39 PM PST 24	3127228206 ps
T488	/workspace/coverage/cover_reg_top/75.xbar_smoke.1714602103			Jan 17 04:28:20 PM PST 24	Jan 17 04:28:30 PM PST 24	210518046 ps
T397	/workspace/coverage/cover_reg_top/74.xbar_smoke.307794575			Jan 17 04:28:04 PM PST 24	Jan 17 04:28:15 PM PST 24	230928993 ps
T398	/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.2830139738			Jan 17 04:18:58 PM PST 24	Jan 17 04:21:00 PM PST 24	11395286302 ps
T389	/workspace/coverage/cover_reg_top/1.xbar_error_random.2507488191			Jan 17 04:18:27 PM PST 24	Jan 17 04:19:10 PM PST 24	564249582 ps
T376	/workspace/coverage/cover_reg_top/34.xbar_same_source.146118319			Jan 17 04:22:07 PM PST 24	Jan 17 04:22:24 PM PST 24	134754603 ps
T395	/workspace/coverage/cover_reg_top/35.xbar_error_and_unmapped_addr.3246217984			Jan 17 04:22:27 PM PST 24	Jan 17 04:22:49 PM PST 24	197819311 ps
T392	/workspace/coverage/cover_reg_top/32.xbar_stress_all_with_error.140366594			Jan 17 04:21:47 PM PST 24	Jan 17 04:23:07 PM PST 24	2040295941 ps
T353	/workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.2955776873			Jan 17 04:19:19 PM PST 24	Jan 17 04:19:37 PM PST 24	153985061 ps
T371	/workspace/coverage/cover_reg_top/90.xbar_random_zero_delays.3440147911			Jan 17 04:30:31 PM PST 24	Jan 17 04:31:22 PM PST 24	534226751 ps
T396	/workspace/coverage/cover_reg_top/60.xbar_error_random.1354142010			Jan 17 04:26:12 PM PST 24	Jan 17 04:27:28 PM PST 24	2373495865 ps
T30	/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.1079485667			Jan 17 04:18:15 PM PST 24	Jan 17 04:21:18 PM PST 24	4173252832 ps
T369	/workspace/coverage/cover_reg_top/73.xbar_stress_all.2887458070			Jan 17 04:28:07 PM PST 24	Jan 17 04:34:01 PM PST 24	9189027023 ps
T337	/workspace/coverage/cover_reg_top/29.xbar_random.2712499463			Jan 17 04:21:11 PM PST 24	Jan 17 04:21:57 PM PST 24	451816674 ps
T338	/workspace/coverage/cover_reg_top/4.xbar_access_same_device.2314801344			Jan 17 04:18:47 PM PST 24	Jan 17 04:19:26 PM PST 24	772038299 ps
T523	/workspace/coverage/cover_reg_top/78.xbar_smoke_large_delays.1852081582			Jan 17 04:28:49 PM PST 24	Jan 17 04:30:40 PM PST 24	10120165706 ps
T399	/workspace/coverage/cover_reg_top/65.xbar_error_and_unmapped_addr.1584305726			Jan 17 04:26:51 PM PST 24	Jan 17 04:27:34 PM PST 24	1008535671 ps
T394	/workspace/coverage/cover_reg_top/86.xbar_stress_all_with_error.3799712369			Jan 17 04:29:55 PM PST 24	Jan 17 04:31:10 PM PST 24	1897996313 ps
T400	/workspace/coverage/cover_reg_top/82.xbar_random_zero_delays.2210540642			Jan 17 04:29:13 PM PST 24	Jan 17 04:29:38 PM PST 24	266838597 ps
T393	/workspace/coverage/cover_reg_top/82.xbar_stress_all_with_reset_error.4288716264			Jan 17 04:29:22 PM PST 24	Jan 17 04:32:47 PM PST 24	3450387062 ps
T372	/workspace/coverage/cover_reg_top/28.xbar_same_source.2613240811			Jan 17 04:21:11 PM PST 24	Jan 17 04:22:24 PM PST 24	2250762270 ps
T759	/workspace/coverage/cover_reg_top/45.xbar_access_same_device_slow_rsp.3357664292			Jan 17 04:24:03 PM PST 24	Jan 17 04:25:49 PM PST 24	5948411450 ps
T122	/workspace/coverage/cover_reg_top/3.chip_csr_mem_rw_with_rand_reset.1700954853			Jan 17 04:18:49 PM PST 24	Jan 17 04:24:41 PM PST 24	7488942063 ps
T373	/workspace/coverage/cover_reg_top/63.xbar_unmapped_addr.804308738			Jan 17 04:26:57 PM PST 24	Jan 17 04:27:42 PM PST 24	957207350 ps
T1	/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.1830168473			Jan 17 04:18:25 PM PST 24	Jan 17 04:23:20 PM PST 24	5584296141 ps
T2	/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.2502822861			Jan 17 04:18:22 PM PST 24	Jan 17 04:22:10 PM PST 24	4484795656 ps
T3	/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.73001729			Jan 17 04:18:25 PM PST 24	Jan 17 04:22:31 PM PST 24	4537376666 ps
T59	/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.1356422212			Jan 17 04:18:20 PM PST 24	Jan 17 04:22:03 PM PST 24	4934801815 ps
T60	/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.3322578296			Jan 17 04:18:18 PM PST 24	Jan 17 04:21:58 PM PST 24	4216494892 ps
T61	/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.3239602668			Jan 17 04:18:18 PM PST 24	Jan 17 04:23:15 PM PST 24	5800140844 ps
T62	/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.1830091438			Jan 17 04:18:22 PM PST 24	Jan 17 04:23:19 PM PST 24	4997070850 ps
T63	/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.1398259029			Jan 17 04:18:08 PM PST 24	Jan 17 04:23:29 PM PST 24	5921371699 ps
T64	/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.1800781015			Jan 17 04:18:15 PM PST 24	Jan 17 04:23:17 PM PST 24	5269064248 ps
T65	/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.1336392527			Jan 17 04:18:23 PM PST 24	Jan 17 04:22:42 PM PST 24	5052758784 ps
T17	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.4025251795			Jan 17 04:52:21 PM PST 24	Jan 17 05:45:49 PM PST 24	23840567539 ps
T18	/workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.2895278100			Jan 17 04:39:11 PM PST 24	Jan 17 04:51:48 PM PST 24	6051038181 ps
T19	/workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.2702879788			Jan 17 04:50:03 PM PST 24	Jan 17 05:02:02 PM PST 24	4181905420 ps
T20	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.211370472			Jan 17 04:46:40 PM PST 24	Jan 17 05:03:10 PM PST 24	12757525915 ps
T86	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.54895524			Jan 17 04:40:43 PM PST 24	Jan 17 05:06:30 PM PST 24	8215285000 ps
T7	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.2571303606			Jan 17 04:39:46 PM PST 24	Jan 17 04:47:05 PM PST 24	4274820668 ps
T35	/workspace/coverage/default/1.rom_raw_unlock.2742508326			Jan 17 04:53:37 PM PST 24	Jan 17 05:26:41 PM PST 24	16450367132 ps
T45	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3464149107			Jan 17 04:59:21 PM PST 24	Jan 17 05:09:32 PM PST 24	5069131890 ps
T77	/workspace/coverage/default/2.chip_sw_clkmgr_off_peri.422922585			Jan 17 04:58:11 PM PST 24	Jan 17 05:17:25 PM PST 24	9715774640 ps
T78	/workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.3997869973			Jan 17 04:54:38 PM PST 24	Jan 17 05:02:40 PM PST 24	3499083892 ps
T79	/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.4210813217			Jan 17 04:40:18 PM PST 24	Jan 17 04:45:29 PM PST 24	3124451739 ps
T21	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops.2969949873			Jan 17 04:45:24 PM PST 24	Jan 17 04:59:18 PM PST 24	4681255354 ps
T80	/workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.3953671440			Jan 17 04:46:08 PM PST 24	Jan 17 04:50:17 PM PST 24	3049804800 ps
T36	/workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.2128474888			Jan 17 04:45:25 PM PST 24	Jan 17 04:51:10 PM PST 24	3915892421 ps
T81	/workspace/coverage/default/2.chip_sw_hmac_enc.4007763832			Jan 17 04:57:58 PM PST 24	Jan 17 05:03:48 PM PST 24	3342721896 ps
T43	/workspace/coverage/default/1.chip_tap_straps_testunlock0.1390955708			Jan 17 04:50:24 PM PST 24	Jan 17 04:54:19 PM PST 24	3369652484 ps
T812	/workspace/coverage/default/0.chip_sw_example_rom.2626642197			Jan 17 04:37:25 PM PST 24	Jan 17 04:39:26 PM PST 24	2624961056 ps
T174	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.316386492			Jan 17 04:46:30 PM PST 24	Jan 17 04:56:41 PM PST 24	4685040682 ps
T38	/workspace/coverage/default/37.chip_sw_all_escalation_resets.644550399			Jan 17 05:05:54 PM PST 24	Jan 17 05:16:13 PM PST 24	5381127720 ps
T145	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.2742052271			Jan 17 04:48:01 PM PST 24	Jan 17 05:12:36 PM PST 24	7451005642 ps
T150	/workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.3369429771			Jan 17 04:51:26 PM PST 24	Jan 17 05:17:16 PM PST 24	23169936957 ps
T161	/workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.1591249374			Jan 17 04:39:24 PM PST 24	Jan 17 08:00:05 PM PST 24	72477259886 ps
T95	/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.2974528733			Jan 17 04:44:10 PM PST 24	Jan 17 05:24:31 PM PST 24	14243938628 ps
T813	/workspace/coverage/default/0.chip_sw_example_manufacturer.3288193793			Jan 17 04:38:38 PM PST 24	Jan 17 04:43:14 PM PST 24	3094967502 ps
T91	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3096698554			Jan 17 04:59:53 PM PST 24	Jan 17 05:09:35 PM PST 24	5313069698 ps
T131	/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.3090070636			Jan 17 05:06:22 PM PST 24	Jan 17 05:11:23 PM PST 24	3015022236 ps
T289	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.3186860200			Jan 17 04:47:25 PM PST 24	Jan 17 05:20:09 PM PST 24	8859846260 ps
T92	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.3590753823			Jan 17 04:58:48 PM PST 24	Jan 17 05:06:55 PM PST 24	4141735031 ps
T39	/workspace/coverage/default/94.chip_sw_all_escalation_resets.2818148806			Jan 17 05:10:12 PM PST 24	Jan 17 05:17:49 PM PST 24	5027953460 ps
T70	/workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.1149982775			Jan 17 04:54:18 PM PST 24	Jan 17 05:15:14 PM PST 24	8009393384 ps
T55	/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.2793384353			Jan 17 05:07:28 PM PST 24	Jan 17 05:13:24 PM PST 24	3717992008 ps
T71	/workspace/coverage/default/2.chip_sw_flash_ctrl_access.3186736921			Jan 17 04:54:11 PM PST 24	Jan 17 05:10:53 PM PST 24	5091826244 ps
T72	/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.3898513937			Jan 17 05:06:54 PM PST 24	Jan 17 05:12:40 PM PST 24	3657896360 ps
T73	/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.1923260086			Jan 17 04:45:18 PM PST 24	Jan 17 05:01:34 PM PST 24	5188414652 ps
T74	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.3970518366			Jan 17 04:57:28 PM PST 24	Jan 17 05:06:04 PM PST 24	4312720875 ps
T75	/workspace/coverage/default/28.chip_sw_all_escalation_resets.3673731279			Jan 17 05:05:00 PM PST 24	Jan 17 05:13:21 PM PST 24	5314798120 ps
T76	/workspace/coverage/default/2.chip_sw_kmac_mode_cshake.2628806083			Jan 17 04:56:51 PM PST 24	Jan 17 05:00:46 PM PST 24	2635663808 ps
T44	/workspace/coverage/default/1.chip_sw_alert_handler_escalation.1335583295			Jan 17 04:47:19 PM PST 24	Jan 17 04:55:54 PM PST 24	5293430100 ps
T294	/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.458097214			Jan 17 05:06:38 PM PST 24	Jan 17 05:12:47 PM PST 24	4080355870 ps
T117	/workspace/coverage/default/89.chip_sw_all_escalation_resets.1322288410			Jan 17 05:09:33 PM PST 24	Jan 17 05:17:42 PM PST 24	4624919824 ps
T201	/workspace/coverage/default/42.chip_sw_all_escalation_resets.1293351541			Jan 17 05:06:41 PM PST 24	Jan 17 05:20:53 PM PST 24	5434153560 ps
T37	/workspace/coverage/default/1.chip_sw_lc_ctrl_program_error.838039229			Jan 17 04:50:50 PM PST 24	Jan 17 04:58:33 PM PST 24	3803257536 ps
T814	/workspace/coverage/default/0.chip_sw_kmac_smoketest.588270873			Jan 17 04:43:19 PM PST 24	Jan 17 04:47:53 PM PST 24	2177371260 ps
T595	/workspace/coverage/default/62.chip_sw_all_escalation_resets.3825824674			Jan 17 05:07:48 PM PST 24	Jan 17 05:19:54 PM PST 24	5574143250 ps
T325	/workspace/coverage/default/2.chip_sw_uart_smoketest_signed.3530469919			Jan 17 05:03:54 PM PST 24	Jan 17 05:35:20 PM PST 24	8697282950 ps
T169	/workspace/coverage/default/11.chip_sw_uart_rand_baudrate.641858659			Jan 17 05:02:53 PM PST 24	Jan 17 06:01:13 PM PST 24	23483562768 ps
T56	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.851498705			Jan 17 04:56:49 PM PST 24	Jan 17 05:13:17 PM PST 24	10110399736 ps
T168	/workspace/coverage/default/17.chip_sw_uart_rand_baudrate.1156989769			Jan 17 05:03:28 PM PST 24	Jan 17 05:16:06 PM PST 24	5933540802 ps
T46	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.563135801			Jan 17 04:41:58 PM PST 24	Jan 17 04:51:55 PM PST 24	5905600086 ps
T632	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.584385820			Jan 17 04:47:17 PM PST 24	Jan 17 04:59:01 PM PST 24	7468674696 ps
T204	/workspace/coverage/default/72.chip_sw_all_escalation_resets.2653481810			Jan 17 05:08:41 PM PST 24	Jan 17 05:18:18 PM PST 24	5434213224 ps
T815	/workspace/coverage/default/1.chip_sw_kmac_idle.1705740495			Jan 17 04:49:23 PM PST 24	Jan 17 04:53:06 PM PST 24	2816240900 ps
T326	/workspace/coverage/default/2.rom_e2e_asm_init_prod_end.925190933			Jan 17 05:05:34 PM PST 24	Jan 17 05:32:09 PM PST 24	8460667085 ps
T644	/workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.4231389369			Jan 17 04:40:35 PM PST 24	Jan 17 04:49:11 PM PST 24	5224558800 ps
T33	/workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.3502014223			Jan 17 04:44:22 PM PST 24	Jan 17 04:52:29 PM PST 24	5070615662 ps
T816	/workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.3571795611			Jan 17 04:50:28 PM PST 24	Jan 17 05:01:35 PM PST 24	5110135750 ps
T96	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.653371906			Jan 17 04:50:17 PM PST 24	Jan 17 04:59:40 PM PST 24	3791113000 ps
T183	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.3647990217			Jan 17 04:40:56 PM PST 24	Jan 17 04:56:08 PM PST 24	5054942740 ps
T817	/workspace/coverage/default/2.chip_sw_aes_enc.471258900			Jan 17 04:57:10 PM PST 24	Jan 17 05:01:46 PM PST 24	2639483186 ps
T207	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.2679375934			Jan 17 04:46:47 PM PST 24	Jan 17 04:51:33 PM PST 24	2804973860 ps
T97	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3284441455			Jan 17 04:58:49 PM PST 24	Jan 17 05:10:16 PM PST 24	3936054478 ps
T256	/workspace/coverage/default/1.chip_sw_aon_timer_smoketest.1263508009			Jan 17 04:52:55 PM PST 24	Jan 17 04:59:29 PM PST 24	2983779280 ps
T305	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.3124825562			Jan 17 04:49:08 PM PST 24	Jan 17 05:34:16 PM PST 24	12187320280 ps
T100	/workspace/coverage/default/0.chip_sw_otbn_smoketest.3597978242			Jan 17 04:44:26 PM PST 24	Jan 17 05:14:47 PM PST 24	7358108040 ps
T253	/workspace/coverage/default/1.chip_sw_plic_sw_irq.1079642444			Jan 17 04:50:31 PM PST 24	Jan 17 04:54:48 PM PST 24	2948404240 ps
T138	/workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1277128167			Jan 17 04:58:18 PM PST 24	Jan 17 08:04:07 PM PST 24	255851950632 ps
T327	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.4207921589			Jan 17 04:46:10 PM PST 24	Jan 17 05:18:10 PM PST 24	8329422974 ps
T634	/workspace/coverage/default/0.chip_sw_power_idle_load.2740979932			Jan 17 04:41:10 PM PST 24	Jan 17 04:53:08 PM PST 24	4479067400 ps
T93	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.2213390843			Jan 17 04:51:03 PM PST 24	Jan 17 05:06:55 PM PST 24	13136780477 ps
T225	/workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.1694374411			Jan 17 04:51:49 PM PST 24	Jan 17 04:56:15 PM PST 24	2760195965 ps
T162	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.2036219918			Jan 17 05:02:42 PM PST 24	Jan 17 05:16:20 PM PST 24	5512856814 ps
T227	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1480786533			Jan 17 04:39:50 PM PST 24	Jan 17 04:49:20 PM PST 24	4993666760 ps
T228	/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.341399639			Jan 17 05:05:04 PM PST 24	Jan 17 05:12:11 PM PST 24	3844325952 ps
T110	/workspace/coverage/default/0.chip_jtag_csr_rw.1219205934			Jan 17 04:33:40 PM PST 24	Jan 17 05:08:52 PM PST 24	20214902020 ps
T211	/workspace/coverage/default/32.chip_sw_all_escalation_resets.1623908767			Jan 17 05:06:46 PM PST 24	Jan 17 05:17:20 PM PST 24	6226852770 ps
T132	/workspace/coverage/default/84.chip_sw_all_escalation_resets.2658238744			Jan 17 05:09:59 PM PST 24	Jan 17 05:19:37 PM PST 24	5892233396 ps
T101	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.2171125470			Jan 17 04:40:18 PM PST 24	Jan 17 05:34:32 PM PST 24	17194605970 ps
T233	/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.2738063129			Jan 17 05:10:04 PM PST 24	Jan 17 05:16:17 PM PST 24	3238596474 ps
T234	/workspace/coverage/default/2.chip_sw_clkmgr_jitter.2220006808			Jan 17 04:57:44 PM PST 24	Jan 17 05:03:09 PM PST 24	3203427756 ps
T303	/workspace/coverage/default/0.rom_e2e_shutdown_exception_c.122475110			Jan 17 04:46:23 PM PST 24	Jan 17 05:20:52 PM PST 24	9479817558 ps
T205	/workspace/coverage/default/27.chip_sw_all_escalation_resets.1963408530			Jan 17 05:04:37 PM PST 24	Jan 17 05:14:59 PM PST 24	5319656824 ps
T89	/workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.2251456117			Jan 17 04:48:56 PM PST 24	Jan 17 05:03:21 PM PST 24	5082364742 ps
T599	/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.939998735			Jan 17 05:11:18 PM PST 24	Jan 17 05:16:54 PM PST 24	3746114828 ps
T818	/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.1749949353			Jan 17 05:00:50 PM PST 24	Jan 17 05:09:53 PM PST 24	6964978032 ps
T819	/workspace/coverage/default/2.chip_sw_example_manufacturer.2290869340			Jan 17 04:54:46 PM PST 24	Jan 17 04:59:04 PM PST 24	2473569452 ps
T251	/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.3744831744			Jan 17 05:08:07 PM PST 24	Jan 17 05:15:27 PM PST 24	4109624580 ps
T295	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.4174835741			Jan 17 04:48:14 PM PST 24	Jan 17 05:17:43 PM PST 24	8291251681 ps
T296	/workspace/coverage/default/1.chip_sw_kmac_app_rom.3792418472			Jan 17 04:49:43 PM PST 24	Jan 17 04:53:36 PM PST 24	2487772040 ps
T146	/workspace/coverage/default/0.rom_e2e_shutdown_output.3672933235			Jan 17 04:45:56 PM PST 24	Jan 17 05:31:28 PM PST 24	21884411182 ps
T297	/workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.4084007780			Jan 17 04:40:54 PM PST 24	Jan 17 04:48:32 PM PST 24	3039013112 ps
T254	/workspace/coverage/default/2.chip_sw_rv_timer_smoketest.277179511			Jan 17 05:00:52 PM PST 24	Jan 17 05:05:18 PM PST 24	2796168532 ps
T602	/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.3951929055			Jan 17 05:08:37 PM PST 24	Jan 17 05:14:25 PM PST 24	3007087860 ps
T179	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.2702502112			Jan 17 04:39:02 PM PST 24	Jan 17 04:56:06 PM PST 24	6318472714 ps
T820	/workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.3637407709			Jan 17 04:43:22 PM PST 24	Jan 17 04:46:25 PM PST 24	2274523784 ps
T821	/workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.2304577254			Jan 17 04:57:08 PM PST 24	Jan 17 05:01:45 PM PST 24	3170915584 ps
T822	/workspace/coverage/default/1.chip_sw_clkmgr_jitter.775339173			Jan 17 04:51:09 PM PST 24	Jan 17 04:55:54 PM PST 24	2896866734 ps
T362	/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.2671522297			Jan 17 04:40:13 PM PST 24	Jan 17 04:47:21 PM PST 24	5045177086 ps
T98	/workspace/coverage/default/0.chip_sw_entropy_src_csrng.516588721			Jan 17 04:39:43 PM PST 24	Jan 17 04:59:45 PM PST 24	6437051972 ps
T94	/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.864747777			Jan 17 05:02:47 PM PST 24	Jan 17 05:10:59 PM PST 24	5834593206 ps
T728	/workspace/coverage/default/7.chip_sw_all_escalation_resets.3170492797			Jan 17 05:03:38 PM PST 24	Jan 17 05:14:17 PM PST 24	4523409900 ps
T248	/workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.543013390			Jan 17 04:47:27 PM PST 24	Jan 17 04:56:19 PM PST 24	5997960474 ps
T160	/workspace/coverage/default/1.chip_plic_all_irqs_0.3727272001			Jan 17 04:50:22 PM PST 24	Jan 17 05:11:35 PM PST 24	5883495816 ps
T268	/workspace/coverage/default/0.chip_sw_hmac_smoketest.2436861537			Jan 17 04:44:11 PM PST 24	Jan 17 04:49:51 PM PST 24	3124732840 ps
T269	/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.3948422288			Jan 17 05:05:40 PM PST 24	Jan 17 05:12:56 PM PST 24	3714112250 ps
T270	/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.3645812988			Jan 17 04:59:02 PM PST 24	Jan 17 05:03:12 PM PST 24	3467086897 ps
T271	/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.22015534			Jan 17 04:55:08 PM PST 24	Jan 17 05:06:25 PM PST 24	5492113693 ps
T206	/workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.3697373332			Jan 17 04:56:59 PM PST 24	Jan 17 05:06:49 PM PST 24	5509221608 ps
T214	/workspace/coverage/default/53.chip_sw_all_escalation_resets.1640382218			Jan 17 05:07:38 PM PST 24	Jan 17 05:16:20 PM PST 24	5263172380 ps
T272	/workspace/coverage/default/1.chip_sw_all_escalation_resets.3123601219			Jan 17 04:45:19 PM PST 24	Jan 17 04:58:04 PM PST 24	5136972056 ps
T82	/workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.368502654			Jan 17 04:47:41 PM PST 24	Jan 17 04:55:22 PM PST 24	18048111040 ps
T363	/workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.2961299920			Jan 17 04:48:23 PM PST 24	Jan 17 04:56:19 PM PST 24	5227296264 ps
T597	/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.1325716209			Jan 17 05:04:05 PM PST 24	Jan 17 05:11:28 PM PST 24	3320688190 ps
T192	/workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.3489949254			Jan 17 04:39:32 PM PST 24	Jan 17 04:45:04 PM PST 24	3245566844 ps
T823	/workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.2561387671			Jan 17 04:56:29 PM PST 24	Jan 17 05:06:20 PM PST 24	6386101040 ps
T66	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.2997924107			Jan 17 04:48:49 PM PST 24	Jan 17 04:56:53 PM PST 24	3847894360 ps
T704	/workspace/coverage/default/79.chip_sw_all_escalation_resets.1024789718			Jan 17 05:11:58 PM PST 24	Jan 17 05:20:18 PM PST 24	4754920026 ps
T114	/workspace/coverage/default/2.chip_sw_gpio_smoketest.3235316109			Jan 17 05:00:32 PM PST 24	Jan 17 05:06:14 PM PST 24	2718927976 ps
T824	/workspace/coverage/default/0.rom_e2e_asm_init_prod_end.1379664991			Jan 17 04:47:25 PM PST 24	Jan 17 05:19:32 PM PST 24	9082415473 ps
T135	/workspace/coverage/default/2.chip_plic_all_irqs_20.1348504393			Jan 17 04:59:21 PM PST 24	Jan 17 05:13:25 PM PST 24	5280434138 ps
T255	/workspace/coverage/default/0.chip_sw_rv_timer_smoketest.1014114367			Jan 17 04:43:52 PM PST 24	Jan 17 04:47:31 PM PST 24	2175611162 ps
T208	/workspace/coverage/default/0.chip_sw_otbn_randomness.1354551282			Jan 17 04:39:15 PM PST 24	Jan 17 04:49:29 PM PST 24	5930297102 ps
T361	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.2787341950			Jan 17 04:57:47 PM PST 24	Jan 17 05:44:14 PM PST 24	16917673416 ps
T825	/workspace/coverage/default/2.chip_sw_rstmgr_smoketest.277717019			Jan 17 05:03:30 PM PST 24	Jan 17 05:06:58 PM PST 24	2570026114 ps
T596	/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.2482014571			Jan 17 05:06:14 PM PST 24	Jan 17 05:12:09 PM PST 24	3274031744 ps
T115	/workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.1111416808			Jan 17 04:39:03 PM PST 24	Jan 17 04:59:21 PM PST 24	10355067593 ps
T669	/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.3500214064			Jan 17 05:08:54 PM PST 24	Jan 17 05:15:16 PM PST 24	4194229522 ps
T587	/workspace/coverage/default/29.chip_sw_all_escalation_resets.3857312026			Jan 17 05:05:12 PM PST 24	Jan 17 05:15:32 PM PST 24	6157935656 ps
T600	/workspace/coverage/default/5.chip_sw_all_escalation_resets.434836726			Jan 17 05:02:25 PM PST 24	Jan 17 05:12:43 PM PST 24	4725097256 ps
T187	/workspace/coverage/default/13.chip_sw_uart_rand_baudrate.3571677141			Jan 17 05:04:30 PM PST 24	Jan 17 05:19:46 PM PST 24	5126575640 ps
T598	/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.624613964			Jan 17 05:09:31 PM PST 24	Jan 17 05:15:25 PM PST 24	3146952840 ps
T116	/workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.845995217			Jan 17 04:39:29 PM PST 24	Jan 17 04:41:43 PM PST 24	3145650400 ps
T826	/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.3519626467			Jan 17 04:55:14 PM PST 24	Jan 17 05:10:39 PM PST 24	5617205104 ps
T646	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.3978645543			Jan 17 04:46:27 PM PST 24	Jan 17 05:17:04 PM PST 24	24194380204 ps
T358	/workspace/coverage/default/0.chip_sw_flash_init.1575817097			Jan 17 04:40:05 PM PST 24	Jan 17 05:13:48 PM PST 24	20097575000 ps
T827	/workspace/coverage/default/2.chip_sw_example_flash.3649268615			Jan 17 04:54:43 PM PST 24	Jan 17 04:58:08 PM PST 24	2749895198 ps
T139	/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.1976971679			Jan 17 05:10:54 PM PST 24	Jan 17 05:17:59 PM PST 24	3863290294 ps
T635	/workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.825895566			Jan 17 04:44:47 PM PST 24	Jan 17 05:09:44 PM PST 24	8906773220 ps
T366	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.3915569989			Jan 17 04:57:03 PM PST 24	Jan 17 05:06:06 PM PST 24	4041738584 ps
T247	/workspace/coverage/default/2.chip_sw_otbn_mem_scramble.3824759914			Jan 17 04:56:31 PM PST 24	Jan 17 05:07:25 PM PST 24	3731639744 ps
T828	/workspace/coverage/default/14.chip_sw_lc_ctrl_transition.2658062492			Jan 17 05:04:12 PM PST 24	Jan 17 05:17:47 PM PST 24	11367396016 ps
T829	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.828130579			Jan 17 04:57:35 PM PST 24	Jan 17 05:07:32 PM PST 24	4437935980 ps
T585	/workspace/coverage/default/1.chip_sw_aes_masking_off.3899706132			Jan 17 04:47:40 PM PST 24	Jan 17 04:53:36 PM PST 24	2627924343 ps
T830	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3688254509			Jan 17 04:58:19 PM PST 24	Jan 17 05:10:53 PM PST 24	4175068656 ps
T831	/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1478417246			Jan 17 04:58:46 PM PST 24	Jan 17 05:16:06 PM PST 24	8196194482 ps
T832	/workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.3884543004			Jan 17 04:51:26 PM PST 24	Jan 17 04:59:21 PM PST 24	4504667920 ps
T356	/workspace/coverage/default/2.chip_sw_flash_init.4228135034			Jan 17 04:56:04 PM PST 24	Jan 17 05:24:06 PM PST 24	16848020107 ps
T642	/workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.3605097765			Jan 17 04:41:00 PM PST 24	Jan 17 05:26:12 PM PST 24	21225143344 ps
T215	/workspace/coverage/default/14.chip_sw_all_escalation_resets.131644691			Jan 17 05:04:21 PM PST 24	Jan 17 05:16:49 PM PST 24	6132842168 ps
T357	/workspace/coverage/default/1.chip_sw_flash_init.1134363290			Jan 17 04:43:59 PM PST 24	Jan 17 05:14:46 PM PST 24	18549429272 ps
T833	/workspace/coverage/default/2.chip_sw_example_concurrency.3057046819			Jan 17 04:54:07 PM PST 24	Jan 17 04:59:44 PM PST 24	3193795510 ps
T673	/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.1215970048			Jan 17 05:07:52 PM PST 24	Jan 17 05:14:17 PM PST 24	3501279560 ps
T354	/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.3728942864			Jan 17 04:41:29 PM PST 24	Jan 17 05:12:20 PM PST 24	20324326185 ps
T601	/workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.1929539570			Jan 17 04:44:10 PM PST 24	Jan 17 04:51:33 PM PST 24	3259733052 ps
T40	/workspace/coverage/default/0.chip_tap_straps_rma.2142599608			Jan 17 04:41:11 PM PST 24	Jan 17 04:59:59 PM PST 24	8556841311 ps
T834	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2352171602			Jan 17 04:50:13 PM PST 24	Jan 17 05:00:06 PM PST 24	4014449224 ps
T136	/workspace/coverage/default/0.chip_plic_all_irqs_20.2522973693			Jan 17 04:41:04 PM PST 24	Jan 17 04:53:41 PM PST 24	4589783568 ps
T835	/workspace/coverage/default/1.rom_e2e_smoke.2549952537			Jan 17 04:54:39 PM PST 24	Jan 17 05:25:57 PM PST 24	8191630820 ps
T133	/workspace/coverage/default/9.chip_sw_all_escalation_resets.1737833541			Jan 17 05:04:29 PM PST 24	Jan 17 05:13:51 PM PST 24	5961168208 ps
T836	/workspace/coverage/default/1.chip_sw_rstmgr_sw_req.3466119155			Jan 17 04:46:57 PM PST 24	Jan 17 04:55:03 PM PST 24	3740731624 ps
T152	/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.1188942948			Jan 17 04:39:05 PM PST 24	Jan 17 05:58:19 PM PST 24	45157398462 ps
T837	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.571394734			Jan 17 04:55:13 PM PST 24	Jan 17 05:12:58 PM PST 24	6775846348 ps
T22	/workspace/coverage/default/2.chip_sw_alert_test.1616411127			Jan 17 04:56:29 PM PST 24	Jan 17 05:02:19 PM PST 24	3473493970 ps
T304	/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.2281564705			Jan 17 05:05:01 PM PST 24	Jan 17 05:14:30 PM PST 24	4896012945 ps
T90	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.1437866657			Jan 17 04:56:27 PM PST 24	Jan 17 05:50:22 PM PST 24	18416260576 ps
T838	/workspace/coverage/default/0.rom_e2e_asm_init_prod.4168637704			Jan 17 04:47:42 PM PST 24	Jan 17 05:18:47 PM PST 24	8850284529 ps
T99	/workspace/coverage/default/2.chip_sw_entropy_src_csrng.3923524092			Jan 17 04:57:51 PM PST 24	Jan 17 05:22:25 PM PST 24	6796575606 ps
T359	/workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.262795707			Jan 17 04:45:22 PM PST 24	Jan 17 04:54:04 PM PST 24	4355085916 ps
T144	/workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.2565424246			Jan 17 04:55:04 PM PST 24	Jan 17 05:10:00 PM PST 24	9778032043 ps
T311	/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.2202862272			Jan 17 04:42:43 PM PST 24	Jan 17 04:48:48 PM PST 24	3245832620 ps
T198	/workspace/coverage/default/0.chip_sw_pattgen_ios.4270091479			Jan 17 04:39:31 PM PST 24	Jan 17 04:42:59 PM PST 24	2707814690 ps
T839	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.1541529893			Jan 17 04:42:05 PM PST 24	Jan 17 04:46:26 PM PST 24	2551492832 ps
T212	/workspace/coverage/default/31.chip_sw_all_escalation_resets.4286068113			Jan 17 05:05:27 PM PST 24	Jan 17 05:14:32 PM PST 24	4942221012 ps
T263	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.3321754571			Jan 17 04:42:01 PM PST 24	Jan 17 04:59:10 PM PST 24	5207371536 ps
T647	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.2819655181			Jan 17 04:56:19 PM PST 24	Jan 17 05:21:40 PM PST 24	21009431162 ps
T194	/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.253565551			Jan 17 04:57:12 PM PST 24	Jan 17 05:04:10 PM PST 24	3186841696 ps
T264	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.2958772026			Jan 17 04:40:55 PM PST 24	Jan 17 04:59:05 PM PST 24	4788195561 ps
T840	/workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.595246927			Jan 17 04:47:31 PM PST 24	Jan 17 04:57:02 PM PST 24	5604570536 ps
T841	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1362580147			Jan 17 04:58:59 PM PST 24	Jan 17 05:04:54 PM PST 24	3016063775 ps
T586	/workspace/coverage/default/2.chip_sw_aes_masking_off.3343210891			Jan 17 04:56:55 PM PST 24	Jan 17 05:02:49 PM PST 24	3539564725 ps
T118	/workspace/coverage/default/0.chip_sw_spi_device_pass_through.1591844776			Jan 17 04:39:28 PM PST 24	Jan 17 04:52:04 PM PST 24	6757723732 ps
T306	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.1006635130			Jan 17 04:47:41 PM PST 24	Jan 17 05:33:44 PM PST 24	9871043828 ps
T364	/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.1645820675			Jan 17 04:41:04 PM PST 24	Jan 17 05:48:25 PM PST 24	16576683188 ps
T842	/workspace/coverage/default/2.chip_sw_aes_smoketest.1283997505			Jan 17 05:01:54 PM PST 24	Jan 17 05:06:09 PM PST 24	2518716280 ps
T213	/workspace/coverage/default/60.chip_sw_all_escalation_resets.2434136459			Jan 17 05:09:22 PM PST 24	Jan 17 05:19:31 PM PST 24	4836808992 ps