Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_ret_aon__ram_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	142610	1			T31	95		T32	85		T53	95
values[2]	10069	1			T31	3		T32	3		T53	1
values[3]	3832	1			T221	181		T340	33		T502	3
values[4]	2280	1			T221	100		T340	6		T502	2
values[5]	1382	1			T221	46		T340	4		T502	2
values[6]	1011	1			T221	9		T340	4		T502	3
values[7]	706	1			T340	4		T502	2		T501	4
values[8]	597	1			T502	2		T501	4		T751	1
values[9]	474	1			T502	3		T501	4		T751	1
values[10]	510	1			T502	5		T501	4		T751	1
values[11]	449	1			T502	8		T501	6		T751	1
values[12]	339	1			T502	3		T501	3		T751	1
values[13]	391	1			T502	2		T501	5		T751	1
values[14]	397	1			T502	1		T501	5		T751	1
values[15]	369	1			T502	2		T501	8		T751	1
values[16]	328	1			T502	3		T501	7		T751	1
values[17]	323	1			T502	1		T501	6		T751	1
values[18]	385	1			T502	5		T501	6		T751	1
values[19]	369	1			T502	8		T501	10		T751	1
values[20]	314	1			T502	5		T501	5		T751	1
values[21]	325	1			T502	9		T501	3		T751	1
values[22]	335	1			T502	6		T501	3		T751	1
values[23]	318	1			T502	4		T501	11		T751	1
values[24]	342	1			T502	5		T501	13		T751	1
values[25]	305	1			T502	9		T501	5		T751	1
values[26]	292	1			T502	8		T501	5		T751	1
values[27]	310	1			T502	2		T501	6		T751	1
values[28]	283	1			T502	1		T501	5		T751	1
values[29]	283	1			T502	6		T501	8		T751	1
values[30]	346	1			T502	5		T501	7		T751	1
values[31]	308	1			T502	3		T501	3		T751	1
values[32]	313	1			T502	2		T501	1		T751	1
values[33]	329	1			T502	2		T501	2		T751	1
values[34]	290	1			T502	1		T501	1		T751	1
values[35]	357	1			T502	3		T501	4		T751	1
values[36]	302	1			T502	5		T501	1		T751	1
values[37]	285	1			T502	8		T501	4		T751	1
values[38]	303	1			T502	3		T501	5		T751	1
values[39]	340	1			T502	6		T501	1		T751	1
values[40]	255	1			T502	3		T501	1		T751	1
values[41]	303	1			T502	3		T501	3		T751	1
values[42]	292	1			T502	3		T501	3		T751	1
values[43]	259	1			T502	1		T501	1		T751	1
values[44]	292	1			T502	2		T501	6		T751	1
values[45]	255	1			T502	3		T501	3		T751	1
values[46]	266	1			T502	2		T501	2		T751	1
values[47]	266	1			T502	1		T501	4		T751	1
values[48]	265	1			T502	4		T501	8		T751	1
values[49]	291	1			T502	2		T501	9		T751	1
values[50]	266	1			T502	4		T501	12		T751	1
values[51]	267	1			T502	3		T501	2		T751	1
values[52]	264	1			T502	2		T501	6		T751	1
values[53]	218	1			T502	1		T501	1		T751	1
values[54]	296	1			T502	3		T501	2		T751	1
values[55]	298	1			T502	4		T501	1		T751	1
values[56]	262	1			T502	1		T501	1		T751	1
values[57]	249	1			T502	2		T501	3		T751	1
values[58]	261	1			T502	2		T501	3		T751	1
values[59]	244	1			T502	3		T501	3		T751	1
values[60]	230	1			T502	6		T501	1		T751	1
values[61]	206	1			T502	1		T751	1		T754	2
values[62]	161	1			T502	2		T751	1		T754	1
values[63]	195	1			T502	3		T751	1		T754	6
values[64]	202	1			T502	4		T751	1		T754	3
values[65]	173	1			T502	5		T751	1		T754	6
values[66]	169	1			T502	6		T751	1		T754	1
values[67]	195	1			T502	8		T751	1		T754	2
values[68]	167	1			T502	17		T751	1		T754	2
values[69]	166	1			T502	4		T751	1		T754	1
values[70]	151	1			T502	6		T751	1		T754	4
values[71]	146	1			T502	1		T751	1		T754	4
values[72]	123	1			T502	3		T751	1		T754	2
values[73]	97	1			T502	2		T751	1		T754	2
values[74]	100	1			T502	2		T751	1		T754	1
values[75]	97	1			T502	1		T751	1		T754	1
values[76]	100	1			T502	6		T751	1		T754	1
values[77]	82	1			T502	4		T751	1		T754	2
values[78]	83	1			T502	7		T751	1		T754	6
values[79]	104	1			T502	14		T751	1		T754	15
values[80]	76	1			T502	5		T751	1		T754	2
values[81]	103	1			T502	6		T751	1		T754	10
values[82]	91	1			T502	3		T751	1		T754	6
values[83]	81	1			T502	1		T751	1		T754	3
values[84]	89	1			T502	2		T751	1		T754	3
values[85]	90	1			T502	7		T751	1		T754	5
values[86]	98	1			T502	7		T751	1		T754	6
values[87]	104	1			T502	3		T751	1		T754	12
values[88]	98	1			T502	3		T751	1		T754	4
values[89]	104	1			T502	3		T751	1		T754	4
values[90]	86	1			T502	9		T751	1		T754	7
values[91]	86	1			T502	5		T751	1		T754	14
values[92]	80	1			T502	1		T751	1		T754	9
values[93]	97	1			T502	3		T751	1		T754	18
values[94]	102	1			T751	1		T754	13		T772	1
values[95]	97	1			T751	1		T754	9		T772	1
values[96]	74	1			T751	1		T754	2		T772	1
values[97]	72	1			T751	1		T754	6		T772	1
values[98]	97	1			T751	1		T754	3		T772	1
values[99]	86	1			T751	1		T754	9		T772	1
values[100]	82	1			T751	1		T754	5		T772	1
values[101]	85	1			T751	1		T754	5		T772	1
values[102]	71	1			T751	1		T754	1		T772	1
values[103]	73	1			T751	1		T754	4		T772	1
values[104]	85	1			T751	1		T754	3		T772	1
values[105]	75	1			T751	1		T754	2		T772	1
values[106]	80	1			T751	1		T754	2		T772	1
values[107]	103	1			T751	1		T754	4		T772	2
values[108]	90	1			T751	1		T754	2		T772	1
values[109]	73	1			T751	2		T772	1		T462	1
values[110]	85	1			T751	7		T772	2		T462	1
values[111]	90	1			T751	2		T772	1		T462	2
values[112]	100	1			T751	2		T772	1		T462	1
values[113]	65	1			T751	2		T772	1		T462	1
values[114]	81	1			T751	1		T772	1		T462	1
values[115]	77	1			T751	1		T772	1		T462	1
values[116]	64	1			T751	3		T772	1		T462	1
values[117]	74	1			T751	1		T772	1		T462	1
values[118]	73	1			T751	1		T772	2		T462	1
values[119]	67	1			T751	2		T772	1		T462	1
values[120]	70	1			T751	2		T772	1		T462	1
values[121]	68	1			T751	2		T772	1		T462	2
values[122]	69	1			T751	1		T772	4		T462	3
values[123]	68	1			T751	1		T772	1		T462	2
values[124]	69	1			T751	1		T772	1		T462	4
values[125]	83	1			T751	1		T772	2		T462	4
values[126]	84	1			T751	2		T772	3		T462	3
values[127]	1023	1			T751	32		T772	26		T462	32
values[128]	10412	1			T751	401		T772	291		T462	305