Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.sysrst_ctrl_aon_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	139688	1			T31	86		T32	107		T53	86
values[2]	9318	1			T31	1		T32	2		T54	1
values[3]	3402	1			T102	9		T352	1		T394	77
values[4]	1942	1			T102	2		T394	26		T766	9
values[5]	1261	1			T102	3		T394	11		T766	4
values[6]	772	1			T102	3		T394	12		T766	6
values[7]	582	1			T394	13		T766	7		T406	10
values[8]	469	1			T394	9		T766	4		T406	6
values[9]	506	1			T394	16		T766	5		T406	7
values[10]	488	1			T394	5		T766	6		T406	8
values[11]	380	1			T406	5		T402	3		T779	2
values[12]	357	1			T406	7		T746	2		T462	1
values[13]	289	1			T406	3		T746	2		T462	1
values[14]	331	1			T406	11		T746	2		T462	1
values[15]	272	1			T406	11		T746	2		T462	1
values[16]	322	1			T406	5		T746	2		T462	1
values[17]	287	1			T406	11		T746	2		T462	1
values[18]	281	1			T406	5		T746	2		T462	1
values[19]	251	1			T406	6		T746	2		T462	1
values[20]	268	1			T406	3		T746	2		T462	1
values[21]	282	1			T406	6		T746	2		T462	1
values[22]	285	1			T406	11		T746	2		T462	1
values[23]	256	1			T406	8		T746	2		T462	1
values[24]	281	1			T406	13		T746	2		T462	1
values[25]	251	1			T406	20		T746	2		T462	1
values[26]	264	1			T406	6		T746	2		T462	1
values[27]	263	1			T406	7		T746	2		T462	1
values[28]	305	1			T406	3		T746	2		T462	1
values[29]	320	1			T406	4		T746	2		T462	1
values[30]	256	1			T406	3		T746	2		T462	1
values[31]	256	1			T406	3		T746	2		T462	1
values[32]	305	1			T406	9		T746	2		T462	1
values[33]	247	1			T406	9		T746	2		T462	2
values[34]	264	1			T406	9		T746	2		T462	1
values[35]	271	1			T406	11		T746	2		T462	1
values[36]	234	1			T406	7		T746	2		T462	1
values[37]	257	1			T406	7		T746	2		T462	1
values[38]	267	1			T406	4		T746	2		T462	1
values[39]	282	1			T406	13		T746	2		T462	1
values[40]	264	1			T406	8		T746	2		T462	1
values[41]	291	1			T406	16		T746	2		T462	1
values[42]	257	1			T406	14		T746	2		T462	1
values[43]	198	1			T406	7		T746	2		T462	1
values[44]	254	1			T406	6		T746	2		T462	1
values[45]	255	1			T406	3		T746	2		T462	1
values[46]	295	1			T406	9		T746	2		T462	1
values[47]	272	1			T406	5		T746	3		T462	1
values[48]	244	1			T406	5		T746	2		T462	1
values[49]	241	1			T406	5		T746	2		T462	1
values[50]	219	1			T406	3		T746	2		T462	1
values[51]	217	1			T406	4		T746	2		T462	1
values[52]	204	1			T406	9		T746	2		T462	1
values[53]	201	1			T406	7		T746	2		T462	1
values[54]	197	1			T406	11		T746	2		T462	1
values[55]	220	1			T406	15		T746	2		T462	1
values[56]	246	1			T406	14		T746	2		T462	1
values[57]	208	1			T406	4		T746	2		T462	1
values[58]	172	1			T406	5		T746	2		T462	1
values[59]	183	1			T406	5		T746	2		T462	1
values[60]	142	1			T406	3		T746	2		T462	1
values[61]	147	1			T406	9		T746	3		T462	1
values[62]	131	1			T406	5		T746	2		T462	1
values[63]	140	1			T406	8		T746	2		T462	1
values[64]	171	1			T406	9		T746	2		T462	1
values[65]	143	1			T406	3		T746	2		T462	1
values[66]	136	1			T406	7		T746	2		T462	1
values[67]	112	1			T406	3		T746	2		T462	1
values[68]	121	1			T406	25		T746	2		T462	1
values[69]	77	1			T406	7		T746	2		T462	1
values[70]	83	1			T406	2		T746	2		T462	1
values[71]	90	1			T406	5		T746	2		T462	1
values[72]	84	1			T406	5		T746	2		T462	1
values[73]	78	1			T406	7		T746	2		T462	1
values[74]	90	1			T406	3		T746	3		T462	1
values[75]	107	1			T406	11		T746	2		T462	1
values[76]	107	1			T406	3		T746	2		T462	1
values[77]	73	1			T746	2		T462	1		T780	1
values[78]	71	1			T746	2		T462	1		T780	1
values[79]	65	1			T746	2		T462	1		T780	1
values[80]	60	1			T746	2		T462	1		T780	1
values[81]	70	1			T746	2		T462	1		T780	1
values[82]	75	1			T746	2		T462	1		T780	1
values[83]	85	1			T746	2		T462	1		T780	1
values[84]	82	1			T746	2		T462	1		T780	1
values[85]	66	1			T746	2		T462	1		T780	1
values[86]	67	1			T746	2		T462	1		T780	1
values[87]	69	1			T746	2		T462	1		T780	1
values[88]	87	1			T746	2		T462	1		T780	1
values[89]	70	1			T746	2		T462	1		T780	1
values[90]	85	1			T746	2		T462	1		T780	1
values[91]	74	1			T746	2		T462	1		T780	2
values[92]	103	1			T746	2		T462	1		T780	8
values[93]	72	1			T746	2		T462	1		T780	3
values[94]	75	1			T746	2		T462	1		T780	2
values[95]	81	1			T746	2		T462	1		T780	5
values[96]	55	1			T746	2		T462	1		T780	4
values[97]	76	1			T746	2		T462	1		T780	5
values[98]	69	1			T746	2		T462	1		T780	1
values[99]	72	1			T746	2		T462	1		T780	1
values[100]	76	1			T746	3		T462	1		T780	4
values[101]	78	1			T746	2		T462	1		T780	1
values[102]	87	1			T746	2		T462	1		T780	1
values[103]	89	1			T746	2		T462	1		T780	1
values[104]	99	1			T746	2		T462	1		T780	1
values[105]	77	1			T746	2		T462	1		T780	1
values[106]	105	1			T746	2		T462	1		T780	1
values[107]	70	1			T746	2		T462	1		T780	3
values[108]	76	1			T746	2		T462	1		T780	4
values[109]	64	1			T746	2		T462	1		T780	1
values[110]	73	1			T746	2		T462	1		T780	2
values[111]	79	1			T746	2		T462	1		T780	1
values[112]	65	1			T746	2		T462	1		T780	1
values[113]	80	1			T746	2		T462	1		T780	3
values[114]	74	1			T746	7		T462	3		T780	1
values[115]	68	1			T746	2		T462	2		T780	2
values[116]	87	1			T746	2		T462	2		T780	6
values[117]	89	1			T746	2		T462	1		T780	3
values[118]	85	1			T746	2		T462	1		T780	1
values[119]	71	1			T746	3		T462	2		T780	1
values[120]	77	1			T746	4		T462	1		T780	3
values[121]	62	1			T746	3		T462	2		T780	3
values[122]	69	1			T746	2		T462	4		T780	2
values[123]	86	1			T746	4		T462	1		T780	1
values[124]	73	1			T746	3		T462	1		T780	1
values[125]	79	1			T746	8		T462	1		T780	1
values[126]	144	1			T746	7		T462	2		T780	1
values[127]	928	1			T746	75		T462	30		T780	33
values[128]	7195	1			T746	672		T462	287		T780	289