Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.uart3_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	138088	1			T31	81		T32	107		T53	82
values[2]	9596	1			T32	3		T54	1		T223	1
values[3]	3670	1			T369	102		T394	133		T650	163
values[4]	1944	1			T369	46		T394	65		T650	76
values[5]	1198	1			T369	13		T394	45		T650	47
values[6]	781	1			T369	6		T394	21		T650	48
values[7]	553	1			T369	1		T394	10		T650	45
values[8]	450	1			T394	3		T650	29		T413	12
values[9]	361	1			T394	7		T650	11		T413	6
values[10]	313	1			T394	1		T650	12		T406	4
values[11]	285	1			T650	20		T406	6		T755	3
values[12]	334	1			T650	14		T406	9		T755	1
values[13]	310	1			T650	5		T406	3		T755	1
values[14]	299	1			T406	4		T755	1		T402	32
values[15]	275	1			T406	4		T755	5		T402	13
values[16]	265	1			T406	8		T755	1		T402	8
values[17]	258	1			T406	25		T755	6		T402	8
values[18]	255	1			T406	7		T755	7		T402	6
values[19]	254	1			T406	7		T755	5		T402	11
values[20]	262	1			T406	5		T755	2		T402	30
values[21]	235	1			T406	12		T755	2		T402	20
values[22]	227	1			T406	4		T755	3		T402	29
values[23]	239	1			T406	4		T755	6		T402	23
values[24]	231	1			T406	10		T755	8		T402	8
values[25]	271	1			T406	10		T755	5		T402	8
values[26]	251	1			T406	10		T755	4		T402	9
values[27]	253	1			T406	9		T755	14		T402	7
values[28]	236	1			T406	7		T755	16		T402	10
values[29]	185	1			T406	19		T755	7		T402	7
values[30]	210	1			T406	16		T755	1		T402	11
values[31]	220	1			T406	10		T755	3		T402	14
values[32]	225	1			T406	6		T755	4		T402	33
values[33]	188	1			T406	2		T755	10		T402	7
values[34]	212	1			T406	6		T755	10		T402	20
values[35]	226	1			T406	6		T755	6		T402	15
values[36]	207	1			T406	11		T755	3		T402	21
values[37]	214	1			T406	3		T755	1		T402	13
values[38]	227	1			T406	4		T755	3		T402	15
values[39]	214	1			T406	13		T755	4		T402	16
values[40]	223	1			T406	5		T755	3		T402	28
values[41]	251	1			T406	11		T755	5		T402	21
values[42]	182	1			T406	3		T755	3		T402	7
values[43]	214	1			T406	7		T755	2		T402	10
values[44]	220	1			T406	6		T755	1		T402	11
values[45]	232	1			T406	9		T755	4		T402	15
values[46]	201	1			T406	12		T755	1		T402	15
values[47]	214	1			T406	6		T755	4		T402	16
values[48]	204	1			T406	9		T755	1		T402	15
values[49]	195	1			T406	5		T755	8		T402	6
values[50]	189	1			T406	5		T755	6		T402	4
values[51]	182	1			T406	7		T755	4		T402	12
values[52]	224	1			T406	13		T755	1		T402	6
values[53]	214	1			T406	6		T755	1		T402	8
values[54]	247	1			T406	9		T755	2		T402	9
values[55]	191	1			T406	7		T755	4		T402	4
values[56]	211	1			T406	10		T755	3		T402	18
values[57]	202	1			T406	12		T755	5		T402	6
values[58]	179	1			T406	10		T755	5		T770	1
values[59]	173	1			T406	4		T755	4		T770	1
values[60]	173	1			T406	4		T755	1		T770	1
values[61]	148	1			T406	9		T755	2		T770	1
values[62]	162	1			T406	14		T755	1		T770	1
values[63]	136	1			T406	5		T755	1		T770	1
values[64]	126	1			T406	6		T755	6		T770	1
values[65]	140	1			T755	5		T770	1		T462	2
values[66]	104	1			T755	5		T770	1		T462	1
values[67]	89	1			T755	4		T770	1		T462	1
values[68]	87	1			T755	3		T770	1		T462	1
values[69]	130	1			T755	3		T770	1		T462	1
values[70]	103	1			T755	1		T770	1		T462	1
values[71]	85	1			T755	2		T770	1		T462	1
values[72]	90	1			T755	1		T770	1		T462	1
values[73]	98	1			T755	2		T770	1		T462	1
values[74]	95	1			T755	1		T770	1		T462	1
values[75]	83	1			T755	3		T770	1		T462	1
values[76]	65	1			T755	2		T770	1		T462	1
values[77]	55	1			T755	11		T770	1		T462	1
values[78]	94	1			T755	12		T770	1		T462	1
values[79]	77	1			T755	4		T770	1		T462	1
values[80]	80	1			T755	7		T770	1		T462	1
values[81]	65	1			T755	5		T770	1		T462	1
values[82]	71	1			T755	2		T770	1		T462	1
values[83]	67	1			T755	1		T770	1		T462	1
values[84]	71	1			T770	1		T462	1		T496	2
values[85]	70	1			T770	1		T462	1		T496	2
values[86]	64	1			T770	1		T462	1		T496	2
values[87]	63	1			T770	1		T462	1		T496	2
values[88]	74	1			T770	1		T462	1		T496	7
values[89]	81	1			T770	1		T462	1		T496	10
values[90]	59	1			T770	1		T462	2		T496	5
values[91]	59	1			T770	1		T462	1		T496	5
values[92]	57	1			T770	1		T462	1		T496	2
values[93]	47	1			T770	1		T462	1		T496	3
values[94]	63	1			T770	1		T462	1		T496	9
values[95]	57	1			T770	1		T462	1		T496	2
values[96]	52	1			T770	1		T462	1		T496	3
values[97]	53	1			T770	1		T462	1		T496	5
values[98]	69	1			T770	1		T462	1		T496	3
values[99]	70	1			T770	1		T462	1		T496	8
values[100]	56	1			T770	1		T462	1		T496	1
values[101]	73	1			T770	1		T462	1		T496	7
values[102]	62	1			T770	1		T462	1		T496	7
values[103]	83	1			T770	1		T462	1		T496	11
values[104]	77	1			T770	1		T462	1		T496	14
values[105]	67	1			T770	1		T462	1		T496	10
values[106]	73	1			T770	1		T462	1		T496	5
values[107]	63	1			T770	1		T462	1		T496	4
values[108]	45	1			T770	2		T462	1		T496	2
values[109]	53	1			T770	2		T462	1		T496	9
values[110]	54	1			T770	2		T462	1		T496	8
values[111]	59	1			T770	2		T462	1		T496	7
values[112]	62	1			T770	4		T462	1		T496	2
values[113]	57	1			T770	3		T462	1		T496	5
values[114]	71	1			T770	2		T462	1		T496	12
values[115]	44	1			T770	1		T462	1		T496	3
values[116]	41	1			T770	1		T462	1		T496	7
values[117]	58	1			T770	1		T462	1		T496	12
values[118]	39	1			T770	3		T462	1		T496	1
values[119]	45	1			T770	4		T462	3		T782	1
values[120]	37	1			T770	1		T462	1		T782	1
values[121]	31	1			T770	1		T462	3		T782	2
values[122]	28	1			T770	2		T462	1		T782	1
values[123]	36	1			T770	3		T462	5		T782	5
values[124]	33	1			T770	2		T462	1		T782	1
values[125]	30	1			T770	1		T462	1		T782	2
values[126]	37	1			T770	4		T462	3		T782	2
values[127]	456	1			T770	33		T462	30		T782	18
values[128]	4453	1			T770	384		T462	355		T782	247