Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	453	1			T102	1		T352	1		T369	1
all_values[1]	475	1			T102	3		T387	1		T369	1
all_values[2]	469	1			T102	1		T387	2		T369	2
all_values[3]	457	1			T221	1		T102	3		T387	3
all_values[4]	426	1			T102	3		T387	3		T393	1
all_values[5]	441	1			T221	1		T102	4		T340	1
all_values[6]	471	1			T102	2		T340	1		T352	1
all_values[7]	432	1			T388	1		T387	1		T369	2
all_values[8]	426	1			T102	4		T387	5		T369	2
all_values[9]	430	1			T387	2		T369	1		T393	1
all_values[10]	442	1			T102	3		T352	1		T387	3
all_values[11]	420	1			T221	1		T387	4		T369	1
all_values[12]	446	1			T102	1		T340	1		T387	5
all_values[13]	442	1			T102	2		T352	1		T388	1
all_values[14]	485	1			T102	1		T388	1		T387	2
all_values[15]	478	1			T102	1		T387	2		T369	1
all_values[16]	450	1			T102	1		T340	1		T387	7
all_values[17]	414	1			T102	2		T605	1		T387	1
all_values[18]	493	1			T221	1		T102	8		T352	1
all_values[19]	419	1			T102	3		T387	1		T369	1
all_values[20]	437	1			T221	1		T102	4		T605	1
all_values[21]	445	1			T221	3		T102	2		T340	2
all_values[22]	444	1			T221	1		T340	1		T387	2
all_values[23]	414	1			T221	1		T387	3		T394	1
all_values[24]	463	1			T102	4		T352	1		T387	1
all_values[25]	443	1			T102	3		T387	4		T369	2
all_values[26]	445	1			T102	2		T387	2		T369	2
all_values[27]	443	1			T102	1		T340	1		T387	3
all_values[28]	427	1			T387	4		T393	3		T650	1
all_values[29]	484	1			T102	2		T388	1		T387	4
all_values[30]	473	1			T102	3		T387	1		T393	2
all_values[31]	462	1			T102	1		T340	1		T387	4
all_values[32]	431	1			T221	1		T340	1		T388	1
all_values[33]	454	1			T102	4		T388	1		T387	2
all_values[34]	455	1			T102	3		T352	1		T388	1
all_values[35]	424	1			T102	2		T394	1		T774	1
all_values[36]	428	1			T387	1		T393	2		T502	1
all_values[37]	444	1			T102	1		T352	2		T387	1
all_values[38]	452	1			T340	2		T352	1		T387	1
all_values[39]	405	1			T387	3		T369	1		T393	3
all_values[40]	448	1			T387	1		T369	2		T393	1
all_values[41]	448	1			T221	1		T102	2		T393	2
all_values[42]	492	1			T102	3		T340	1		T352	1
all_values[43]	430	1			T102	3		T387	2		T369	1
all_values[44]	453	1			T102	1		T352	1		T388	1
all_values[45]	477	1			T221	2		T102	4		T340	1
all_values[46]	460	1			T221	2		T102	3		T352	1
all_values[47]	461	1			T102	2		T352	1		T387	1
all_values[48]	482	1			T102	3		T387	3		T369	1
all_values[49]	433	1			T387	4		T369	2		T502	2