Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3475	1			T102	20		T339	2		T352	1
all_values[1]	3518	1			T102	12		T339	1		T352	2
all_values[2]	3507	1			T102	13		T339	1		T387	5
all_values[3]	3442	1			T102	11		T352	3		T387	7
all_values[4]	3402	1			T102	10		T352	1		T387	3
all_values[5]	3334	1			T102	10		T352	1		T387	10
all_values[6]	3412	1			T102	20		T387	8		T369	2
all_values[7]	3480	1			T102	10		T339	2		T387	4
all_values[8]	3373	1			T102	14		T387	7		T369	2
all_values[9]	3552	1			T102	23		T352	1		T387	3
all_values[10]	3419	1			T102	17		T339	1		T387	3
all_values[11]	3450	1			T102	8		T339	1		T387	4
all_values[12]	3541	1			T102	15		T339	1		T352	1
all_values[13]	3568	1			T102	18		T352	1		T387	6
all_values[14]	3526	1			T102	15		T387	7		T369	1
all_values[15]	3506	1			T102	18		T387	3		T376	1
all_values[16]	3435	1			T102	17		T339	1		T387	8
all_values[17]	3503	1			T102	14		T339	3		T352	5
all_values[18]	3460	1			T102	19		T339	1		T352	2
all_values[19]	3594	1			T102	13		T339	3		T352	1
all_values[20]	3474	1			T102	16		T339	2		T387	3
all_values[21]	3503	1			T102	11		T339	1		T387	4
all_values[22]	3422	1			T102	8		T339	2		T387	3
all_values[23]	3482	1			T102	11		T339	1		T352	1
all_values[24]	3493	1			T102	10		T387	8		T369	1
all_values[25]	3512	1			T102	18		T339	4		T352	3
all_values[26]	3525	1			T102	16		T352	1		T387	5
all_values[27]	3411	1			T102	13		T352	1		T387	4
all_values[28]	3526	1			T102	12		T339	1		T352	2
all_values[29]	3385	1			T102	14		T339	1		T352	1
all_values[30]	3492	1			T102	5		T352	2		T387	4
all_values[31]	3531	1			T102	12		T352	1		T387	2
all_values[32]	3472	1			T102	12		T352	1		T387	7
all_values[33]	3545	1			T102	13		T339	1		T352	1
all_values[34]	3401	1			T102	12		T339	1		T352	4
all_values[35]	3502	1			T102	13		T339	1		T387	2
all_values[36]	3492	1			T102	11		T352	1		T387	7
all_values[37]	3426	1			T102	9		T339	1		T352	1
all_values[38]	3479	1			T102	16		T387	3		T376	1
all_values[39]	3404	1			T102	8		T387	7		T376	2
all_values[40]	3485	1			T102	13		T339	1		T352	1
all_values[41]	3518	1			T102	14		T339	1		T387	4
all_values[42]	3480	1			T102	14		T339	2		T387	2
all_values[43]	3513	1			T102	12		T339	1		T352	2
all_values[44]	3379	1			T102	12		T387	3		T369	2
all_values[45]	3459	1			T102	6		T339	1		T352	5
all_values[46]	3383	1			T102	11		T387	6		T369	1
all_values[47]	3465	1			T102	14		T387	6		T376	3
all_values[48]	3432	1			T102	13		T352	3		T387	2
all_values[49]	3478	1			T102	14		T387	6		T369	2
all_values[50]	3441	1			T102	17		T352	1		T387	5
all_values[51]	3578	1			T102	9		T339	2		T352	1
all_values[52]	3405	1			T102	9		T339	1		T387	1
all_values[53]	3475	1			T102	14		T339	1		T352	4
all_values[54]	3514	1			T102	9		T352	1		T387	6
all_values[55]	3466	1			T102	16		T339	1		T352	3
all_values[56]	3480	1			T102	9		T339	1		T352	1
all_values[57]	3418	1			T102	11		T352	1		T387	7
all_values[58]	3391	1			T102	21		T339	1		T352	1
all_values[59]	3421	1			T102	18		T352	1		T387	5
all_values[60]	3471	1			T102	12		T352	1		T387	6
all_values[61]	3508	1			T102	10		T387	9		T376	1
all_values[62]	3404	1			T102	9		T387	4		T376	1
all_values[63]	3500	1			T102	13		T387	4		T376	2