LINE 17913
EXPRESSION (addr_hit[199] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|---|---|---|---|
| 0 | 1 | 1 | Covered | T28,T17,T20 |
| 1 | 0 | 1 | Covered | T28,T29,T122 |
| 1 | 1 | 0 | Covered | T409,T422,T429 |
| 1 | 1 | 1 | Covered | T28,T253,T110 |
LINE 17916
EXPRESSION (addr_hit[200] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|---|---|---|---|
| 0 | 1 | 1 | Covered | T28,T17,T20 |
| 1 | 0 | 1 | Covered | T28,T29,T122 |
| 1 | 1 | 0 | Covered | T409,T422,T482 |
| 1 | 1 | 1 | Covered | T28,T110,T22 |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |