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 LINE       29309
 EXPRESSION (dio_pad_sleep_mode_11_we & dio_pad_sleep_regwen_11_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T10,T302,T342
1	1	Covered	T28,T8,T4

 LINE       29341
 EXPRESSION (dio_pad_sleep_mode_12_we & dio_pad_sleep_regwen_12_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T112,T113,T302
1	1	Covered	T28,T340,T8

 LINE       29373
 EXPRESSION (dio_pad_sleep_mode_13_we & dio_pad_sleep_regwen_13_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T8,T302
1	1	Covered	T4,T10,T5

 LINE       29405
 EXPRESSION (dio_pad_sleep_mode_14_we & dio_pad_sleep_regwen_14_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T10,T300
1	1	Covered	T338,T8,T4

 LINE       29437
 EXPRESSION (dio_pad_sleep_mode_15_we & dio_pad_sleep_regwen_15_qs)
             ------------1-----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T113,T344
1	1	Covered	T340,T338,T8

 LINE       29701
 EXPRESSION (aon_wkup_detector_en_0_we & aon_wkup_detector_en_0_regwen)
             ------------1------------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T300,T343,T344
1	1	Covered	T28,T8,T10

 LINE       29734
 EXPRESSION (aon_wkup_detector_en_1_we & aon_wkup_detector_en_1_regwen)
             ------------1------------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T8,T10,T112
1	1	Covered	T28,T7,T9

 LINE       29767
 EXPRESSION (aon_wkup_detector_en_2_we & aon_wkup_detector_en_2_regwen)
             ------------1------------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T10,T112,T300
1	1	Covered	T28,T8,T13

 LINE       29800
 EXPRESSION (aon_wkup_detector_en_3_we & aon_wkup_detector_en_3_regwen)
             ------------1------------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T113,T302,T300
1	1	Covered	T28,T8,T10

 LINE       29833
 EXPRESSION (aon_wkup_detector_en_4_we & aon_wkup_detector_en_4_regwen)
             ------------1------------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T28,T10,T302
1	1	Covered	T8,T112,T113

 LINE       29866
 EXPRESSION (aon_wkup_detector_en_5_we & aon_wkup_detector_en_5_regwen)
             ------------1------------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T10,T302,T300
1	1	Covered	T28,T8,T112

 LINE       29899
 EXPRESSION (aon_wkup_detector_en_6_we & aon_wkup_detector_en_6_regwen)
             ------------1------------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T28,T300,T343
1	1	Covered	T8,T10,T112

 LINE       29932
 EXPRESSION (aon_wkup_detector_en_7_we & aon_wkup_detector_en_7_regwen)
             ------------1------------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T10,T113,T343
1	1	Covered	T28,T8,T112

 LINE       29965
 EXPRESSION (aon_wkup_detector_0_we & aon_wkup_detector_0_regwen)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T113,T342,T300
1	1	Covered	T28,T8,T10

 LINE       30052
 EXPRESSION (aon_wkup_detector_1_we & aon_wkup_detector_1_regwen)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T8,T10,T112
1	1	Covered	T28,T7,T9

 LINE       30139
 EXPRESSION (aon_wkup_detector_2_we & aon_wkup_detector_2_regwen)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T28,T10,T112
1	1	Covered	T8,T13,T113

 LINE       30226
 EXPRESSION (aon_wkup_detector_3_we & aon_wkup_detector_3_regwen)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T113,T302,T300
1	1	Covered	T28,T8,T10

 LINE       30313
 EXPRESSION (aon_wkup_detector_4_we & aon_wkup_detector_4_regwen)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T112,T302,T343
1	1	Covered	T28,T8,T10

 LINE       30400
 EXPRESSION (aon_wkup_detector_5_we & aon_wkup_detector_5_regwen)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T10,T302,T342
1	1	Covered	T28,T8,T112

 LINE       30487
 EXPRESSION (aon_wkup_detector_6_we & aon_wkup_detector_6_regwen)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T28,T343,T344
1	1	Covered	T8,T10,T112

 LINE       30574
 EXPRESSION (aon_wkup_detector_7_we & aon_wkup_detector_7_regwen)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T113,T342,T343
1	1	Covered	T28,T8,T10

 LINE       30661
 EXPRESSION (aon_wkup_detector_cnt_th_0_we & aon_wkup_detector_cnt_th_0_regwen)
             --------------1--------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T113,T342,T300
1	1	Covered	T28,T8,T10

 LINE       30694
 EXPRESSION (aon_wkup_detector_cnt_th_1_we & aon_wkup_detector_cnt_th_1_regwen)
             --------------1--------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T8,T10,T112
1	1	Covered	T28,T11,T16

 LINE       30727
 EXPRESSION (aon_wkup_detector_cnt_th_2_we & aon_wkup_detector_cnt_th_2_regwen)
             --------------1--------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T28,T10,T342
1	1	Covered	T8,T112,T113

 LINE       30760
 EXPRESSION (aon_wkup_detector_cnt_th_3_we & aon_wkup_detector_cnt_th_3_regwen)
             --------------1--------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T113,T302,T300
1	1	Covered	T28,T8,T10

 LINE       30793
 EXPRESSION (aon_wkup_detector_cnt_th_4_we & aon_wkup_detector_cnt_th_4_regwen)
             --------------1--------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T28,T10,T112
1	1	Covered	T8,T113,T300

 LINE       30826
 EXPRESSION (aon_wkup_detector_cnt_th_5_we & aon_wkup_detector_cnt_th_5_regwen)
             --------------1--------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T10,T302,T342
1	1	Covered	T28,T8,T112

 LINE       30859
 EXPRESSION (aon_wkup_detector_cnt_th_6_we & aon_wkup_detector_cnt_th_6_regwen)
             --------------1--------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T28,T8,T343
1	1	Covered	T10,T112,T113

 LINE       30892
 EXPRESSION (aon_wkup_detector_cnt_th_7_we & aon_wkup_detector_cnt_th_7_regwen)
             --------------1--------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T113,T342,T343
1	1	Covered	T28,T8,T10

 LINE       30925
 EXPRESSION (wkup_detector_padsel_0_we & wkup_detector_regwen_0_qs)
             ------------1------------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T342,T300,T344
1	1	Covered	T28,T340,T8

 LINE       30957
 EXPRESSION (wkup_detector_padsel_1_we & wkup_detector_regwen_1_qs)
             ------------1------------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T8,T10,T112
1	1	Covered	T28,T340,T338

 LINE       30989
 EXPRESSION (wkup_detector_padsel_2_we & wkup_detector_regwen_2_qs)
             ------------1------------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T10,T112
1	1	Covered	T8,T13,T113

 LINE       31021
 EXPRESSION (wkup_detector_padsel_3_we & wkup_detector_regwen_3_qs)
             ------------1------------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T8,T302
1	1	Covered	T10,T112,T113

 LINE       31053
 EXPRESSION (wkup_detector_padsel_4_we & wkup_detector_regwen_4_qs)
             ------------1------------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T112,T113
1	1	Covered	T8,T10,T380

 LINE       31085
 EXPRESSION (wkup_detector_padsel_5_we & wkup_detector_regwen_5_qs)
             ------------1------------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T10,T302,T342
1	1	Covered	T28,T8,T112

 LINE       31117
 EXPRESSION (wkup_detector_padsel_6_we & wkup_detector_regwen_6_qs)
             ------------1------------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T300,T343
1	1	Covered	T338,T8,T10

 LINE       31149
 EXPRESSION (wkup_detector_padsel_7_we & wkup_detector_regwen_7_qs)
             ------------1------------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T342,T343,T344
1	1	Covered	T28,T8,T10

 LINE       31402
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_ALERT_TEST_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31403
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_0_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31404
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_1_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31405
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_2_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31406
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_3_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31407
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_4_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31408
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_5_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31409
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_6_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31410
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_7_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31411
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_8_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31412
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_9_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31413
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_10_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31414
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_11_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31415
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_12_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31416
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_13_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31417
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_14_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31418
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_15_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31419
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_16_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31420
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_17_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31421
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_18_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31422
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_19_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31423
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_20_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31424
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_21_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31425
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_22_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31426
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_23_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31427
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_24_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31428
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_25_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31429
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_26_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31430
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_27_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31431
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_28_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31432
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_29_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31433
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_30_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31434
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_31_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31435
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_32_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31436
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_33_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31437
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_34_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31438
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_35_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31439
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_36_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31440
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_37_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31441
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_38_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31442
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_39_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31443
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_40_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31444
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_41_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31445
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_42_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31446
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_43_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31447
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_44_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31448
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_45_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31449
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_46_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31450
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_47_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31451
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_48_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31452
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_49_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31453
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_50_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31454
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_51_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31455
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_52_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T32,T28,T53

 LINE       31456
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_53_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31457
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_54_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T32,T28,T53

 LINE       31458
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_55_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31459
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_56_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31460
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_0_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T32,T28,T53

 LINE       31461
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_1_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31462
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_2_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31463
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_3_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31464
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_4_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31465
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_5_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31466
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_6_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T32,T28,T53

 LINE       31467
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_7_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31468
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_8_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T32,T28,T102

 LINE       31469
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_9_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31470
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_10_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31471
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_11_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31472
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_12_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T32,T28,T53

 LINE       31473
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_13_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31474
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_14_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31475
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_15_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T28,T223

 LINE       31476
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_16_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31477
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_17_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31478
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_18_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31479
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_19_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31480
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_20_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T32,T28,T53

 LINE       31481
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_21_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31482
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_22_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T32,T28,T53

 LINE       31483
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_23_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T32,T28,T53

 LINE       31484
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_24_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31485
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_25_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T32,T28,T221

 LINE       31486
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_26_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31487
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_27_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31488
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_28_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31489
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_29_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31490
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_30_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T28,T54

 LINE       31491
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_31_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31492
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_32_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31493
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_33_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T32,T28,T222

 LINE       31494
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_34_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T28,T53

 LINE       31495
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_35_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T28,T53

 LINE       31496
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_36_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31497
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_37_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T28,T53

 LINE       31498
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_38_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T28,T222

 LINE       31499
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_39_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T28,T53

 LINE       31500
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_40_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31501
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_41_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31502
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_42_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31503
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_43_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T32,T28,T53

 LINE       31504
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_44_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T28,T53

 LINE       31505
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_45_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31506
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_46_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31507
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_47_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31508
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_48_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31509
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_49_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T32,T28,T53

 LINE       31510
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_50_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31511
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_51_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31512
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_52_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31513
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_53_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31514
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_54_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31515
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_55_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T28,T53

 LINE       31516
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_56_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31517
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_REGWEN_0_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T28,T53

 LINE       31518
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_REGWEN_1_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31519
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_REGWEN_2_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31520
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_REGWEN_3_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T28,T54

 LINE       31521
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_REGWEN_4_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31522
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_REGWEN_5_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31523
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_REGWEN_6_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31524
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_REGWEN_7_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T32,T28,T53

 LINE       31525
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_REGWEN_8_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31526
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_REGWEN_9_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31527
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_REGWEN_10_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31528
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_REGWEN_11_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T32,T28,T53

 LINE       31529
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_REGWEN_12_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31530
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_REGWEN_13_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T28,T53

 LINE       31531
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_REGWEN_14_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T32,T28,T53

 LINE       31532
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_REGWEN_15_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31533
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_REGWEN_16_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T28,T224,T29

 LINE       31534
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_REGWEN_17_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31535
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_REGWEN_18_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T32,T28,T53

 LINE       31536
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_REGWEN_19_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T32,T28,T53

 LINE       31537
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_REGWEN_20_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T28,T102

 LINE       31538
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_REGWEN_21_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T32,T28,T53

 LINE       31539
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_REGWEN_22_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T32,T28,T53

 LINE       31540
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_REGWEN_23_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T32,T28,T53

 LINE       31541
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_REGWEN_24_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T32,T28

 LINE       31542
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_REGWEN_25_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T31,T32,T28
1	Covered	T31,T28,T221