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 LINE       31976
 SUB-EXPRESSION (addr_hit[270] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T340,T122
1	1	Covered	T28,T53,T221

 LINE       31976
 SUB-EXPRESSION (addr_hit[271] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T53,T381
1	1	Covered	T31,T32,T28

 LINE       31976
 SUB-EXPRESSION (addr_hit[272] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T32,T28,T340
1	1	Covered	T32,T28,T53

 LINE       31976
 SUB-EXPRESSION (addr_hit[273] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T393,T122
1	1	Covered	T28,T221,T29

 LINE       31976
 SUB-EXPRESSION (addr_hit[274] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T371,T394
1	1	Covered	T31,T32,T28

 LINE       31976
 SUB-EXPRESSION (addr_hit[275] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T221,T384
1	1	Covered	T32,T28,T29

 LINE       31976
 SUB-EXPRESSION (addr_hit[276] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T395,T369
1	1	Covered	T28,T102,T29

 LINE       31976
 SUB-EXPRESSION (addr_hit[277] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T221,T222
1	1	Covered	T28,T221,T222

 LINE       31976
 SUB-EXPRESSION (addr_hit[278] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T102,T224
1	1	Covered	T32,T28,T221

 LINE       31976
 SUB-EXPRESSION (addr_hit[279] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T387,T389,T122
1	1	Covered	T32,T28,T54

 LINE       31976
 SUB-EXPRESSION (addr_hit[280] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T340,T389
1	1	Covered	T31,T28,T53

 LINE       31976
 SUB-EXPRESSION (addr_hit[281] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T221,T340
1	1	Covered	T28,T102,T29

 LINE       31976
 SUB-EXPRESSION (addr_hit[282] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T221,T352
1	1	Covered	T28,T29,T339

 LINE       31976
 SUB-EXPRESSION (addr_hit[283] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T32,T28,T381
1	1	Covered	T32,T28,T221

 LINE       31976
 SUB-EXPRESSION (addr_hit[284] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T102,T382
1	1	Covered	T31,T32,T28

 LINE       31976
 SUB-EXPRESSION (addr_hit[285] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T53,T102
1	1	Covered	T28,T53,T221

 LINE       31976
 SUB-EXPRESSION (addr_hit[286] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T377,T340
1	1	Covered	T31,T28,T102

 LINE       31976
 SUB-EXPRESSION (addr_hit[287] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T352,T388
1	1	Covered	T28,T221,T102

 LINE       31976
 SUB-EXPRESSION (addr_hit[288] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T222,T387
1	1	Covered	T32,T28,T102

 LINE       31976
 SUB-EXPRESSION (addr_hit[289] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T102,T378
1	1	Covered	T28,T53,T221

 LINE       31976
 SUB-EXPRESSION (addr_hit[290] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T32,T28,T102
1	1	Covered	T31,T28,T102

 LINE       31976
 SUB-EXPRESSION (addr_hit[291] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T382,T340
1	1	Covered	T29,T381,T382

 LINE       31976
 SUB-EXPRESSION (addr_hit[292] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T102,T374
1	1	Covered	T53,T221,T102

 LINE       31976
 SUB-EXPRESSION (addr_hit[293] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T32,T28,T384
1	1	Covered	T28,T53,T222

 LINE       31976
 SUB-EXPRESSION (addr_hit[294] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T102,T378
1	1	Covered	T31,T32,T28

 LINE       31976
 SUB-EXPRESSION (addr_hit[295] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T122,T1
1	1	Covered	T31,T32,T28

 LINE       31976
 SUB-EXPRESSION (addr_hit[296] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T389,T393,T122
1	1	Covered	T28,T29,T379

 LINE       31976
 SUB-EXPRESSION (addr_hit[297] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T340,T352
1	1	Covered	T31,T28,T53

 LINE       31976
 SUB-EXPRESSION (addr_hit[298] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T367,T340
1	1	Covered	T28,T221,T223

 LINE       31976
 SUB-EXPRESSION (addr_hit[299] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T31,T28,T381
1	1	Covered	T32,T28,T53

 LINE       31976
 SUB-EXPRESSION (addr_hit[300] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T381,T369
1	1	Covered	T31,T32,T28

 LINE       31976
 SUB-EXPRESSION (addr_hit[301] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T32,T28,T222
1	1	Covered	T28,T102,T29

 LINE       31976
 SUB-EXPRESSION (addr_hit[302] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T352,T393
1	1	Covered	T31,T32,T28

 LINE       31976
 SUB-EXPRESSION (addr_hit[303] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T53,T102
1	1	Covered	T31,T28,T53

 LINE       31976
 SUB-EXPRESSION (addr_hit[304] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T29,T367
1	1	Covered	T28,T222,T29

 LINE       31976
 SUB-EXPRESSION (addr_hit[305] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T53,T29
1	1	Covered	T31,T28,T221

 LINE       31976
 SUB-EXPRESSION (addr_hit[306] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T29,T367
1	1	Covered	T222,T29,T340

 LINE       31976
 SUB-EXPRESSION (addr_hit[307] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T53,T382
1	1	Covered	T102,T29,T378

 LINE       31976
 SUB-EXPRESSION (addr_hit[308] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T222,T368
1	1	Covered	T32,T28,T53

 LINE       31976
 SUB-EXPRESSION (addr_hit[309] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T31,T28,T29
1	1	Covered	T31,T223,T102

 LINE       31976
 SUB-EXPRESSION (addr_hit[310] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T340,T368
1	1	Covered	T32,T28,T53

 LINE       31976
 SUB-EXPRESSION (addr_hit[311] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T53,T102
1	1	Covered	T102,T224,T29

 LINE       31976
 SUB-EXPRESSION (addr_hit[312] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T31,T32,T28
1	1	Covered	T28,T221,T29

 LINE       31976
 SUB-EXPRESSION (addr_hit[313] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T29,T340
1	1	Covered	T31,T221,T102

 LINE       31976
 SUB-EXPRESSION (addr_hit[314] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T102,T224
1	1	Covered	T31,T32,T28

 LINE       31976
 SUB-EXPRESSION (addr_hit[315] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T54,T221
1	1	Covered	T32,T53,T54

 LINE       31976
 SUB-EXPRESSION (addr_hit[316] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T102,T384
1	1	Covered	T28,T29,T384

 LINE       31976
 SUB-EXPRESSION (addr_hit[317] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T222,T102
1	1	Covered	T28,T29,T384

 LINE       31976
 SUB-EXPRESSION (addr_hit[318] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T221,T340
1	1	Covered	T28,T224,T29

 LINE       31976
 SUB-EXPRESSION (addr_hit[319] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T32,T28,T396
1	1	Covered	T28,T102,T29

 LINE       31976
 SUB-EXPRESSION (addr_hit[320] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T122,T1
1	1	Covered	T31,T32,T28

 LINE       31976
 SUB-EXPRESSION (addr_hit[321] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T375,T122
1	1	Covered	T31,T32,T28

 LINE       31976
 SUB-EXPRESSION (addr_hit[322] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T32,T28,T102
1	1	Covered	T31,T28,T29

 LINE       31976
 SUB-EXPRESSION (addr_hit[323] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T102,T340
1	1	Covered	T32,T28,T222

 LINE       31976
 SUB-EXPRESSION (addr_hit[324] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T381,T393
1	1	Covered	T32,T28,T221

 LINE       31976
 SUB-EXPRESSION (addr_hit[325] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T32,T28,T389
1	1	Covered	T32,T28,T53

 LINE       31976
 SUB-EXPRESSION (addr_hit[326] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T102,T387
1	1	Covered	T53,T54,T29

 LINE       31976
 SUB-EXPRESSION (addr_hit[327] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T31,T28,T102
1	1	Covered	T28,T222,T102

 LINE       31976
 SUB-EXPRESSION (addr_hit[328] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T32,T28,T371
1	1	Covered	T31,T32,T28

 LINE       31976
 SUB-EXPRESSION (addr_hit[329] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T102,T384
1	1	Covered	T28,T102,T224

 LINE       31976
 SUB-EXPRESSION (addr_hit[330] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T29,T375
1	1	Covered	T28,T29,T382

 LINE       31976
 SUB-EXPRESSION (addr_hit[331] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T352,T396
1	1	Covered	T31,T28,T221

 LINE       31976
 SUB-EXPRESSION (addr_hit[332] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T53,T352
1	1	Covered	T28,T53,T221

 LINE       31976
 SUB-EXPRESSION (addr_hit[333] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T222,T29
1	1	Covered	T31,T32,T53

 LINE       31976
 SUB-EXPRESSION (addr_hit[334] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T53,T352
1	1	Covered	T28,T221,T29

 LINE       31976
 SUB-EXPRESSION (addr_hit[335] & ((|(4'b1111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T221,T367
1	1	Covered	T28,T53,T29

 LINE       31976
 SUB-EXPRESSION (addr_hit[336] & ((|(4'b0011 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T224,T381
1	1	Covered	T28,T221,T102

 LINE       31976
 SUB-EXPRESSION (addr_hit[337] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T32,T28,T375
1	1	Covered	T28,T53,T29

 LINE       31976
 SUB-EXPRESSION (addr_hit[338] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T32,T28,T102
1	1	Covered	T28,T221,T102

 LINE       31976
 SUB-EXPRESSION (addr_hit[339] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T340,T396
1	1	Covered	T28,T29,T382

 LINE       31976
 SUB-EXPRESSION (addr_hit[340] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T53,T223
1	1	Covered	T31,T54,T221

 LINE       31976
 SUB-EXPRESSION (addr_hit[341] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T102,T29
1	1	Covered	T31,T28,T102

 LINE       31976
 SUB-EXPRESSION (addr_hit[342] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T31,T28,T224
1	1	Covered	T28,T53,T29

 LINE       31976
 SUB-EXPRESSION (addr_hit[343] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T102,T389
1	1	Covered	T28,T221,T222

 LINE       31976
 SUB-EXPRESSION (addr_hit[344] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T31,T28,T395
1	1	Covered	T28,T53,T29

 LINE       31976
 SUB-EXPRESSION (addr_hit[345] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T31,T28,T102
1	1	Covered	T31,T28,T29

 LINE       31976
 SUB-EXPRESSION (addr_hit[346] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T384,T390
1	1	Covered	T32,T28,T53

 LINE       31976
 SUB-EXPRESSION (addr_hit[347] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T32,T28,T221
1	1	Covered	T28,T53,T221

 LINE       31976
 SUB-EXPRESSION (addr_hit[348] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T32,T28,T102
1	1	Covered	T28,T221,T102

 LINE       31976
 SUB-EXPRESSION (addr_hit[349] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T32,T28,T221
1	1	Covered	T31,T28,T224

 LINE       31976
 SUB-EXPRESSION (addr_hit[350] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T102,T224
1	1	Covered	T53,T222,T29

 LINE       31976
 SUB-EXPRESSION (addr_hit[351] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T102,T340
1	1	Covered	T31,T32,T221

 LINE       31976
 SUB-EXPRESSION (addr_hit[352] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T31,T32,T28
1	1	Covered	T32,T28,T53

 LINE       31976
 SUB-EXPRESSION (addr_hit[353] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T102,T340
1	1	Covered	T28,T53,T29

 LINE       31976
 SUB-EXPRESSION (addr_hit[354] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T221,T102
1	1	Covered	T28,T102,T29

 LINE       31976
 SUB-EXPRESSION (addr_hit[355] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T102,T389
1	1	Covered	T31,T28,T102

 LINE       31976
 SUB-EXPRESSION (addr_hit[356] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T53,T221
1	1	Covered	T31,T28,T221

 LINE       31976
 SUB-EXPRESSION (addr_hit[357] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T374,T371
1	1	Covered	T32,T29,T382

 LINE       31976
 SUB-EXPRESSION (addr_hit[358] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T223,T340
1	1	Covered	T32,T53,T102

 LINE       31976
 SUB-EXPRESSION (addr_hit[359] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T32,T28,T53
1	1	Covered	T32,T28,T221

 LINE       31976
 SUB-EXPRESSION (addr_hit[360] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T102,T387
1	1	Covered	T32,T29,T367

 LINE       31976
 SUB-EXPRESSION (addr_hit[361] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T31,T32,T28
1	1	Covered	T32,T28,T221

 LINE       31976
 SUB-EXPRESSION (addr_hit[362] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T339,T384
1	1	Covered	T31,T32,T28

 LINE       31976
 SUB-EXPRESSION (addr_hit[363] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T221,T337
1	1	Covered	T28,T53,T221

 LINE       31976
 SUB-EXPRESSION (addr_hit[364] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T31,T32,T28
1	1	Covered	T31,T28,T102

 LINE       31976
 SUB-EXPRESSION (addr_hit[365] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T222,T352
1	1	Covered	T53,T29,T340

 LINE       31976
 SUB-EXPRESSION (addr_hit[366] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T382,T397
1	1	Covered	T28,T222,T102

 LINE       31976
 SUB-EXPRESSION (addr_hit[367] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T382,T352
1	1	Covered	T32,T28,T221

 LINE       31976
 SUB-EXPRESSION (addr_hit[368] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T32,T28,T102
1	1	Covered	T32,T28,T221

 LINE       31976
 SUB-EXPRESSION (addr_hit[369] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T223,T29
1	1	Covered	T32,T221,T29

 LINE       31976
 SUB-EXPRESSION (addr_hit[370] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T382,T340
1	1	Covered	T31,T29,T352

 LINE       31976
 SUB-EXPRESSION (addr_hit[371] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T53,T384
1	1	Covered	T28,T53,T102

 LINE       31976
 SUB-EXPRESSION (addr_hit[372] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T221,T379
1	1	Covered	T221,T102,T224

 LINE       31976
 SUB-EXPRESSION (addr_hit[373] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T32,T28,T221
1	1	Covered	T28,T102,T224

 LINE       31976
 SUB-EXPRESSION (addr_hit[374] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T53,T352
1	1	Covered	T31,T32,T28

 LINE       31976
 SUB-EXPRESSION (addr_hit[375] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T32,T28,T221
1	1	Covered	T28,T53,T221

 LINE       31976
 SUB-EXPRESSION (addr_hit[376] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T53,T222
1	1	Covered	T31,T32,T28

 LINE       31976
 SUB-EXPRESSION (addr_hit[377] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T223,T367
1	1	Covered	T221,T29,T340

 LINE       31976
 SUB-EXPRESSION (addr_hit[378] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T31,T28,T122
1	1	Covered	T31,T222,T102

 LINE       31976
 SUB-EXPRESSION (addr_hit[379] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T221,T102
1	1	Covered	T32,T222,T102

 LINE       31976
 SUB-EXPRESSION (addr_hit[380] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T224,T340
1	1	Covered	T222,T102,T29

 LINE       31976
 SUB-EXPRESSION (addr_hit[381] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T368,T389
1	1	Covered	T31,T221,T29

 LINE       31976
 SUB-EXPRESSION (addr_hit[382] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T340,T369
1	1	Covered	T53,T224,T29

 LINE       31976
 SUB-EXPRESSION (addr_hit[383] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T32,T28,T224
1	1	Covered	T29,T340,T352

 LINE       31976
 SUB-EXPRESSION (addr_hit[384] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T32,T28,T102
1	1	Covered	T32,T28,T29

 LINE       31976
 SUB-EXPRESSION (addr_hit[385] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T221,T340
1	1	Covered	T28,T221,T29

 LINE       31976
 SUB-EXPRESSION (addr_hit[386] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T102,T29
1	1	Covered	T102,T29,T340

 LINE       31976
 SUB-EXPRESSION (addr_hit[387] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T339,T369
1	1	Covered	T221,T29,T340

 LINE       31976
 SUB-EXPRESSION (addr_hit[388] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T340,T369
1	1	Covered	T32,T102,T29

 LINE       31976
 SUB-EXPRESSION (addr_hit[389] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T31,T28,T53
1	1	Covered	T32,T28,T53

 LINE       31976
 SUB-EXPRESSION (addr_hit[390] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T31,T32,T28
1	1	Covered	T32,T222,T29

 LINE       31976
 SUB-EXPRESSION (addr_hit[391] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T53,T102
1	1	Covered	T28,T222,T29

 LINE       31976
 SUB-EXPRESSION (addr_hit[392] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T221,T102
1	1	Covered	T31,T28,T222

 LINE       31976
 SUB-EXPRESSION (addr_hit[393] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T102,T382
1	1	Covered	T32,T221,T29

 LINE       31976
 SUB-EXPRESSION (addr_hit[394] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T340,T389
1	1	Covered	T29,T367,T352

 LINE       31976
 SUB-EXPRESSION (addr_hit[395] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T102,T381
1	1	Covered	T31,T28,T29

 LINE       31976
 SUB-EXPRESSION (addr_hit[396] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T367,T340
1	1	Covered	T221,T102,T224

 LINE       31976
 SUB-EXPRESSION (addr_hit[397] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T53,T223
1	1	Covered	T31,T32,T29

 LINE       31976
 SUB-EXPRESSION (addr_hit[398] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T221,T222
1	1	Covered	T32,T53,T224

 LINE       31976
 SUB-EXPRESSION (addr_hit[399] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T31,T32,T28
1	1	Covered	T32,T28,T53

 LINE       31976
 SUB-EXPRESSION (addr_hit[400] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T340,T376
1	1	Covered	T28,T221,T222

 LINE       31976
 SUB-EXPRESSION (addr_hit[401] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T221,T352
1	1	Covered	T32,T28,T221

 LINE       31976
 SUB-EXPRESSION (addr_hit[402] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T339,T340
1	1	Covered	T31,T32,T53

 LINE       31976
 SUB-EXPRESSION (addr_hit[403] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T31,T28,T222
1	1	Covered	T31,T32,T53

 LINE       31976
 SUB-EXPRESSION (addr_hit[404] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T32,T28,T102
1	1	Covered	T32,T29,T381