Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.flash_ctrl__prim_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	161687	1			T29	51		T30	80		T31	7
values[2]	4302	1			T31	1		T60	1		T115	1
values[3]	2002	1			T376	1		T722	36		T430	1
values[4]	1392	1			T722	23		T505	3		T448	13
values[5]	1081	1			T722	30		T505	1		T448	16
values[6]	942	1			T722	22		T505	4		T448	12
values[7]	817	1			T722	25		T505	4		T448	8
values[8]	721	1			T722	4		T505	2		T448	9
values[9]	659	1			T505	2		T448	12		T449	59
values[10]	566	1			T505	3		T448	19		T449	45
values[11]	493	1			T505	5		T448	12		T449	29
values[12]	526	1			T505	5		T448	15		T449	7
values[13]	528	1			T505	2		T448	9		T449	10
values[14]	460	1			T505	1		T448	19		T449	9
values[15]	465	1			T505	5		T448	29		T433	19
values[16]	386	1			T505	6		T448	8		T433	7
values[17]	340	1			T505	8		T448	3		T433	9
values[18]	342	1			T505	8		T448	9		T433	9
values[19]	296	1			T505	7		T448	16		T433	5
values[20]	335	1			T505	6		T448	32		T433	4
values[21]	238	1			T505	3		T448	27		T433	5
values[22]	219	1			T505	3		T448	27		T433	22
values[23]	242	1			T505	1		T448	31		T433	43
values[24]	206	1			T505	3		T448	25		T433	50
values[25]	212	1			T505	2		T448	22		T433	42
values[26]	208	1			T505	1		T448	19		T433	31
values[27]	207	1			T505	3		T448	11		T433	21
values[28]	205	1			T505	2		T448	10		T433	25
values[29]	164	1			T505	1		T448	3		T433	26
values[30]	181	1			T505	2		T448	6		T433	35
values[31]	140	1			T505	1		T448	4		T433	20
values[32]	150	1			T505	2		T448	6		T433	15
values[33]	164	1			T505	1		T448	2		T433	24
values[34]	158	1			T505	3		T433	17		T884	37
values[35]	155	1			T505	2		T433	5		T884	45
values[36]	148	1			T505	4		T433	1		T884	33
values[37]	143	1			T505	3		T884	27		T541	1
values[38]	110	1			T505	10		T884	17		T541	2
values[39]	104	1			T505	5		T884	8		T541	1
values[40]	87	1			T505	2		T884	2		T541	1
values[41]	65	1			T505	3		T884	1		T541	1
values[42]	88	1			T505	1		T884	5		T541	2
values[43]	85	1			T505	1		T884	9		T541	3
values[44]	100	1			T505	1		T884	5		T541	3
values[45]	75	1			T505	6		T541	2		T467	3
values[46]	69	1			T505	3		T541	4		T467	3
values[47]	70	1			T505	3		T541	4		T467	3
values[48]	53	1			T505	3		T541	1		T467	3
values[49]	52	1			T505	2		T541	2		T467	3
values[50]	44	1			T505	1		T541	6		T467	3
values[51]	54	1			T505	2		T541	11		T467	3
values[52]	46	1			T505	1		T541	6		T467	3
values[53]	47	1			T505	5		T541	2		T467	3
values[54]	41	1			T505	3		T541	1		T467	3
values[55]	45	1			T505	1		T541	3		T467	3
values[56]	40	1			T505	1		T541	2		T467	3
values[57]	49	1			T505	2		T541	2		T467	3
values[58]	51	1			T505	1		T541	1		T467	3
values[59]	38	1			T505	2		T541	2		T467	3
values[60]	52	1			T505	5		T541	1		T467	3
values[61]	43	1			T505	8		T541	2		T467	3
values[62]	54	1			T505	7		T541	6		T467	3
values[63]	44	1			T505	4		T541	6		T467	3
values[64]	40	1			T505	1		T541	1		T467	3
values[65]	50	1			T505	2		T541	4		T467	3
values[66]	51	1			T505	4		T541	4		T467	3
values[67]	56	1			T505	3		T541	1		T467	3
values[68]	50	1			T505	1		T541	2		T467	3
values[69]	51	1			T505	2		T541	3		T467	3
values[70]	50	1			T505	1		T541	2		T467	3
values[71]	40	1			T505	1		T541	4		T467	3
values[72]	49	1			T505	1		T541	5		T467	3
values[73]	44	1			T505	4		T541	2		T467	3
values[74]	48	1			T505	4		T541	8		T467	3
values[75]	59	1			T505	6		T541	10		T467	3
values[76]	45	1			T505	4		T541	5		T467	3
values[77]	57	1			T505	1		T541	4		T467	3
values[78]	58	1			T505	2		T541	2		T467	3
values[79]	54	1			T505	3		T541	1		T467	3
values[80]	56	1			T505	2		T541	2		T467	3
values[81]	64	1			T505	3		T541	4		T467	4
values[82]	62	1			T505	6		T541	6		T467	5
values[83]	76	1			T505	4		T541	8		T467	4
values[84]	78	1			T505	3		T541	2		T467	4
values[85]	74	1			T505	2		T541	4		T467	6
values[86]	79	1			T505	2		T541	1		T467	5
values[87]	63	1			T505	6		T541	2		T467	6
values[88]	73	1			T505	7		T541	1		T467	5
values[89]	59	1			T505	2		T541	5		T467	3
values[90]	73	1			T505	1		T541	10		T467	5
values[91]	89	1			T505	4		T541	5		T467	9
values[92]	90	1			T505	1		T541	5		T467	11
values[93]	73	1			T505	3		T541	8		T467	3
values[94]	72	1			T505	3		T541	4		T467	5
values[95]	70	1			T505	1		T541	10		T467	6
values[96]	83	1			T505	1		T541	4		T467	4
values[97]	83	1			T505	2		T541	7		T467	6
values[98]	82	1			T505	1		T541	1		T467	5
values[99]	68	1			T505	2		T541	7		T467	5
values[100]	67	1			T505	2		T541	5		T467	5
values[101]	73	1			T505	3		T541	3		T467	10
values[102]	61	1			T505	2		T541	3		T467	5
values[103]	75	1			T505	3		T541	6		T467	4
values[104]	76	1			T505	4		T541	3		T467	4
values[105]	81	1			T505	2		T541	3		T467	4
values[106]	94	1			T505	1		T541	5		T467	3
values[107]	77	1			T505	1		T541	7		T467	3
values[108]	68	1			T505	5		T541	6		T467	5
values[109]	83	1			T505	2		T541	4		T467	8
values[110]	79	1			T505	5		T541	5		T467	5
values[111]	52	1			T505	2		T541	3		T467	4
values[112]	81	1			T505	1		T541	6		T467	6
values[113]	67	1			T505	2		T541	9		T467	4
values[114]	76	1			T505	3		T541	4		T467	5
values[115]	94	1			T505	5		T541	4		T467	7
values[116]	89	1			T505	9		T541	2		T467	5
values[117]	79	1			T505	6		T541	5		T467	8
values[118]	101	1			T505	13		T541	9		T467	6
values[119]	89	1			T505	8		T541	3		T467	4
values[120]	88	1			T505	6		T541	7		T467	5
values[121]	87	1			T505	4		T541	10		T467	5
values[122]	107	1			T505	6		T541	5		T467	4
values[123]	97	1			T505	7		T541	2		T467	5
values[124]	149	1			T505	18		T467	6		T885	4
values[125]	307	1			T505	39		T467	5		T885	3
values[126]	574	1			T505	60		T467	55		T885	17
values[127]	2261	1			T505	45		T467	336		T885	100
values[128]	4176	1			T505	3		T467	634		T885	161