Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.71	95.40	94.49	98.01		95.22	97.57	99.58

Total tests in report: 2848

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
26.06	26.06	28.84	28.84	20.67	20.67	15.34	15.34			41.92	41.92	49.44	49.44	0.13	0.13	/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.1392582250
49.16	23.10	69.68	40.83	48.94	28.26	50.46	35.12			61.02	19.10	55.19	5.74	9.67	9.54	/workspace/coverage/cover_reg_top/6.xbar_error_random.8697912
58.63	9.47	75.43	5.75	61.26	12.32	50.62	0.16			71.12	10.10	82.96	27.78	10.36	0.69	/workspace/coverage/cover_reg_top/6.chip_csr_rw.571599950
67.68	9.05	87.37	11.94	72.39	11.13	59.94	9.32			85.19	14.08	90.74	7.78	10.41	0.05	/workspace/coverage/default/0.chip_plic_all_irqs_0.2210442922
72.73	5.06	88.14	0.77	77.39	5.00	59.94	0.00			86.51	1.32	90.74	0.00	33.67	23.25	/workspace/coverage/cover_reg_top/59.xbar_access_same_device_slow_rsp.365452761
75.47	2.74	88.14	0.00	77.39	0.00	59.94	0.00			86.51	0.00	90.74	0.00	50.09	16.43	/workspace/coverage/cover_reg_top/36.xbar_access_same_device_slow_rsp.105808324
78.06	2.59	88.14	0.00	77.39	0.00	75.48	15.54			86.51	0.00	90.74	0.00	50.09	0.00	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.1204502369
80.51	2.45	88.14	0.00	77.39	0.00	75.48	0.00			86.51	0.00	90.74	0.00	64.79	14.70	/workspace/coverage/cover_reg_top/48.xbar_access_same_device_slow_rsp.171785165
82.64	2.13	88.70	0.56	79.97	2.58	75.49	0.01			87.63	1.11	90.74	0.00	73.31	8.52	/workspace/coverage/cover_reg_top/83.xbar_stress_all_with_rand_reset.3535880117
83.91	1.27	88.70	0.00	80.23	0.26	75.49	0.00			87.69	0.07	90.74	0.00	80.61	7.30	/workspace/coverage/cover_reg_top/40.xbar_stress_all.1186665250
85.07	1.16	88.76	0.06	80.23	0.00	82.38	6.89			87.69	0.00	90.74	0.00	80.61	0.00	/workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.441651992
86.00	0.93	89.55	0.79	82.68	2.45	82.41	0.03			90.03	2.33	90.74	0.00	80.61	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.3830412685
86.86	0.86	90.30	0.74	82.83	0.15	82.42	0.02			90.18	0.16	94.81	4.07	80.61	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.234761763
87.70	0.84	90.30	0.00	82.93	0.10	82.42	0.00			90.18	0.00	94.81	0.00	85.55	4.94	/workspace/coverage/cover_reg_top/45.xbar_access_same_device_slow_rsp.622034699
88.40	0.70	90.31	0.01	82.93	0.01	86.44	4.02			90.18	0.00	95.00	0.19	85.55	0.00	/workspace/coverage/default/2.chip_sw_edn_auto_mode.1681739
89.02	0.62	91.51	1.21	84.00	1.07	86.68	0.24			91.40	1.21	95.00	0.00	85.55	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_20.2625462717
89.62	0.60	91.51	0.00	84.00	0.01	88.41	1.73			91.40	0.00	95.00	0.00	87.43	1.88	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.1098631172
90.17	0.54	91.52	0.01	86.82	2.81	88.41	0.00			91.40	0.00	95.00	0.00	87.85	0.42	/workspace/coverage/cover_reg_top/1.chip_tl_errors.1943618387
90.69	0.52	91.52	0.00	86.82	0.00	88.41	0.00			91.40	0.00	95.00	0.00	90.99	3.14	/workspace/coverage/cover_reg_top/44.xbar_access_same_device_slow_rsp.2635144409
91.19	0.50	91.52	0.00	86.82	0.00	91.39	2.98			91.40	0.00	95.00	0.00	90.99	0.00	/workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.1823135543
91.64	0.45	92.25	0.72	87.55	0.73	91.96	0.57			91.88	0.49	95.19	0.19	91.01	0.02	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3893075083
92.08	0.44	92.69	0.45	88.47	0.92	92.07	0.11			92.68	0.79	95.19	0.00	91.39	0.38	/workspace/coverage/default/2.chip_jtag_csr_rw.1963250990
92.47	0.39	93.19	0.50	90.09	1.62	92.13	0.06			92.71	0.03	95.19	0.00	91.49	0.11	/workspace/coverage/cover_reg_top/2.chip_same_csr_outstanding.3822014018
92.79	0.33	93.19	0.00	90.09	0.00	92.13	0.00			92.71	0.00	95.19	0.00	93.45	1.96	/workspace/coverage/cover_reg_top/65.xbar_access_same_device_slow_rsp.2135083930
93.11	0.31	93.26	0.07	90.15	0.05	93.25	1.12			92.75	0.04	95.74	0.56	93.49	0.04	/workspace/coverage/default/2.chip_sw_data_integrity_escalation.2124658555
93.41	0.31	93.92	0.66	90.66	0.51	93.39	0.14			93.27	0.52	95.74	0.00	93.49	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_10.1122073643
93.68	0.26	93.93	0.01	90.87	0.21	93.39	0.00			93.29	0.02	95.74	0.00	94.84	1.35	/workspace/coverage/cover_reg_top/1.xbar_access_same_device.4215745066
93.87	0.20	94.10	0.17	91.13	0.25	93.40	0.02			93.47	0.18	96.30	0.56	94.84	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_retention.2319421959
94.07	0.19	94.13	0.03	91.20	0.07	94.10	0.70			93.64	0.17	96.48	0.19	94.84	0.00	/workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.2649575410
94.25	0.18	94.14	0.01	91.31	0.11	94.10	0.00			93.67	0.03	96.48	0.00	95.77	0.93	/workspace/coverage/cover_reg_top/48.xbar_smoke_large_delays.513195725
94.41	0.17	94.14	0.00	91.40	0.09	94.10	0.00			93.67	0.00	96.48	0.00	96.69	0.92	/workspace/coverage/cover_reg_top/65.xbar_stress_all_with_reset_error.859499162
94.57	0.16	94.22	0.08	91.80	0.40	94.11	0.01			94.13	0.45	96.48	0.00	96.69	0.00	/workspace/coverage/default/1.chip_jtag_csr_rw.1638746261
94.71	0.14	94.22	0.00	91.82	0.02	94.11	0.00			94.13	0.00	96.48	0.00	97.52	0.83	/workspace/coverage/cover_reg_top/97.xbar_access_same_device_slow_rsp.1234645360
94.85	0.13	94.46	0.24	92.03	0.21	94.11	0.00			94.45	0.32	96.48	0.00	97.56	0.04	/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.2898428277
94.97	0.13	94.46	0.01	92.05	0.02	94.65	0.54			94.46	0.01	96.67	0.19	97.56	0.00	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.2220568617
95.08	0.10	94.50	0.04	92.11	0.06	95.14	0.49			94.48	0.02	96.67	0.00	97.57	0.01	/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.3811702641
95.17	0.09	94.50	0.00	92.11	0.00	95.70	0.56			94.48	0.00	96.67	0.00	97.57	0.00	/workspace/coverage/default/53.chip_sw_all_escalation_resets.3301226441
95.24	0.07	94.50	0.00	92.31	0.20	95.70	0.00			94.71	0.23	96.67	0.00	97.57	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.2130998218
95.31	0.07	94.52	0.02	92.40	0.09	95.73	0.03			94.76	0.05	96.67	0.00	97.79	0.22	/workspace/coverage/cover_reg_top/99.xbar_stress_all_with_reset_error.1992687348
95.38	0.07	94.52	0.00	92.40	0.00	96.13	0.40			94.76	0.00	96.67	0.00	97.79	0.00	/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.2393143007
95.44	0.06	94.53	0.01	92.42	0.03	96.26	0.13			94.79	0.02	96.85	0.19	97.80	0.01	/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.3225580161
95.49	0.05	94.53	0.00	92.72	0.30	96.26	0.00			94.79	0.00	96.85	0.00	97.81	0.01	/workspace/coverage/cover_reg_top/28.chip_tl_errors.2113035049
95.55	0.05	94.53	0.00	92.87	0.14	96.26	0.00			94.95	0.16	96.85	0.00	97.81	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.987019770
95.60	0.05	94.55	0.02	92.90	0.03	96.27	0.01			94.95	0.00	96.85	0.00	98.06	0.25	/workspace/coverage/default/0.chip_sw_alert_test.270335254
95.64	0.04	94.57	0.03	92.92	0.02	96.27	0.01			94.97	0.02	97.04	0.19	98.07	0.01	/workspace/coverage/default/31.chip_sw_all_escalation_resets.1781827833
95.68	0.04	94.57	0.00	92.95	0.03	96.27	0.00			94.97	0.00	97.04	0.00	98.28	0.21	/workspace/coverage/cover_reg_top/25.xbar_stress_all_with_rand_reset.2048588530
95.72	0.04	94.71	0.13	92.95	0.00	96.35	0.08			94.99	0.02	97.04	0.00	98.28	0.00	/workspace/coverage/default/2.chip_tap_straps_testunlock0.4101883505
95.76	0.04	94.71	0.01	92.96	0.01	96.35	0.01			94.99	0.01	97.22	0.19	98.30	0.01	/workspace/coverage/default/14.chip_sw_all_escalation_resets.1045080859
95.79	0.04	94.71	0.01	92.97	0.01	96.36	0.01			95.00	0.01	97.41	0.19	98.31	0.01	/workspace/coverage/default/15.chip_sw_all_escalation_resets.2375924295
95.83	0.04	94.72	0.01	92.98	0.01	96.36	0.00			95.01	0.01	97.59	0.19	98.32	0.01	/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.1683723180
95.87	0.03	94.73	0.01	93.04	0.05	96.50	0.14			95.02	0.01	97.59	0.00	98.32	0.00	/workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.915832616
95.90	0.03	94.73	0.00	93.04	0.00	96.71	0.21			95.02	0.00	97.59	0.00	98.32	0.00	/workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.3864681275
95.93	0.03	94.73	0.00	93.04	0.00	96.91	0.20			95.02	0.00	97.59	0.00	98.32	0.00	/workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.1309975824
95.97	0.03	94.73	0.00	93.23	0.19	96.91	0.00			95.02	0.00	97.59	0.00	98.32	0.00	/workspace/coverage/cover_reg_top/20.chip_tl_errors.1156328942
96.00	0.03	94.73	0.00	93.23	0.00	97.10	0.18			95.02	0.00	97.59	0.00	98.32	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.884164153
96.03	0.03	94.73	0.00	93.29	0.07	97.10	0.00			95.05	0.03	97.59	0.00	98.40	0.08	/workspace/coverage/cover_reg_top/45.xbar_random_slow_rsp.3926443090
96.06	0.03	94.73	0.00	93.47	0.18	97.10	0.00			95.05	0.00	97.59	0.00	98.40	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_0.155374364
96.09	0.03	94.73	0.00	93.47	0.00	97.24	0.14			95.05	0.00	97.59	0.00	98.44	0.04	/workspace/coverage/default/1.chip_sw_edn_entropy_reqs.2197621566
96.11	0.02	94.78	0.05	93.50	0.03	97.25	0.01			95.12	0.07	97.59	0.00	98.44	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.4162511034
96.13	0.02	94.78	0.00	93.50	0.00	97.38	0.13			95.12	0.00	97.59	0.00	98.44	0.00	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.396470721
96.16	0.02	94.87	0.10	93.53	0.03	97.38	0.01			95.12	0.00	97.59	0.00	98.44	0.00	/workspace/coverage/default/0.chip_sw_gpio.3960460119
96.17	0.02	94.87	0.00	93.63	0.10	97.38	0.00			95.12	0.00	97.59	0.00	98.45	0.01	/workspace/coverage/cover_reg_top/8.chip_tl_errors.1768025610
96.19	0.02	94.87	0.00	93.64	0.01	97.38	0.00			95.12	0.00	97.59	0.00	98.54	0.09	/workspace/coverage/cover_reg_top/26.xbar_stress_all_with_reset_error.3271269800
96.21	0.02	94.87	0.00	93.73	0.09	97.38	0.00			95.12	0.00	97.59	0.00	98.54	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_20.3552588678
96.22	0.01	94.87	0.00	93.74	0.01	97.38	0.00			95.12	0.00	97.59	0.00	98.61	0.07	/workspace/coverage/cover_reg_top/52.xbar_stress_all_with_rand_reset.1612813911
96.23	0.01	94.89	0.02	93.77	0.04	97.38	0.01			95.14	0.02	97.59	0.00	98.61	0.00	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.12644134
96.25	0.01	94.89	0.01	93.85	0.08	97.38	0.00			95.14	0.00	97.59	0.00	98.61	0.00	/workspace/coverage/cover_reg_top/18.chip_same_csr_outstanding.2278827617
96.26	0.01	94.89	0.00	93.85	0.00	97.46	0.08			95.14	0.00	97.59	0.00	98.61	0.00	/workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1860371495
96.27	0.01	94.89	0.00	93.85	0.00	97.54	0.08			95.14	0.00	97.59	0.00	98.61	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.3555594278
96.28	0.01	94.89	0.00	93.92	0.08	97.54	0.00			95.14	0.00	97.59	0.00	98.61	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_0.1496383511
96.30	0.01	94.93	0.03	93.94	0.01	97.57	0.03			95.14	0.00	97.59	0.00	98.61	0.00	/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.849755786
96.31	0.01	94.96	0.04	93.96	0.02	97.57	0.00			95.15	0.01	97.59	0.00	98.61	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.785205753
96.32	0.01	95.00	0.04	93.98	0.02	97.57	0.00			95.16	0.01	97.59	0.00	98.61	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.2924064111
96.33	0.01	95.01	0.01	93.99	0.01	97.59	0.02			95.17	0.02	97.59	0.00	98.61	0.00	/workspace/coverage/default/0.chip_sw_usbdev_pincfg.1154112692
96.34	0.01	95.01	0.00	94.05	0.06	97.59	0.00			95.17	0.00	97.59	0.00	98.61	0.00	/workspace/coverage/cover_reg_top/24.chip_tl_errors.1761964460
96.35	0.01	95.03	0.03	94.07	0.01	97.59	0.00			95.19	0.02	97.59	0.00	98.61	0.00	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.3919260811
96.36	0.01	95.06	0.03	94.08	0.01	97.59	0.00			95.21	0.02	97.59	0.00	98.61	0.00	/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.2419234190
96.37	0.01	95.06	0.01	94.09	0.01	97.63	0.04			95.21	0.00	97.59	0.00	98.61	0.00	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.4140224786
96.38	0.01	95.06	0.00	94.15	0.05	97.63	0.00			95.21	0.00	97.59	0.00	98.61	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_10.935896622
96.38	0.01	95.06	0.00	94.15	0.00	97.68	0.05			95.21	0.00	97.59	0.00	98.61	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.330927022
96.39	0.01	95.07	0.01	94.15	0.00	97.71	0.03			95.21	0.00	97.59	0.00	98.63	0.01	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3142975278
96.40	0.01	95.07	0.00	94.15	0.00	97.71	0.00			95.21	0.00	97.59	0.00	98.67	0.05	/workspace/coverage/cover_reg_top/32.xbar_stress_all_with_rand_reset.4235381681
96.41	0.01	95.07	0.00	94.16	0.01	97.74	0.03			95.21	0.00	97.59	0.00	98.67	0.00	/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.1809550147
96.41	0.01	95.07	0.00	94.16	0.00	97.79	0.04			95.21	0.00	97.59	0.00	98.67	0.00	/workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.1533482559
96.42	0.01	95.07	0.00	94.20	0.04	97.79	0.00			95.21	0.00	97.59	0.00	98.67	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.1653259673
96.43	0.01	95.07	0.00	94.20	0.00	97.79	0.00			95.21	0.00	97.59	0.00	98.71	0.04	/workspace/coverage/cover_reg_top/75.xbar_stress_all_with_reset_error.3032507651
96.43	0.01	95.07	0.01	94.22	0.02	97.79	0.01			95.21	0.00	97.59	0.00	98.71	0.00	/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.253585821
96.44	0.01	95.10	0.02	94.22	0.00	97.80	0.01			95.21	0.00	97.59	0.00	98.71	0.00	/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.558595679
96.44	0.01	95.10	0.00	94.22	0.00	97.83	0.03			95.21	0.00	97.59	0.00	98.71	0.00	/workspace/coverage/default/0.chip_sw_kmac_entropy.3659541871
96.45	0.01	95.10	0.00	94.23	0.01	97.85	0.01			95.21	0.00	97.59	0.00	98.71	0.00	/workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.570637569
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96.46	0.01	95.10	0.00	94.26	0.00	97.85	0.00			95.21	0.00	97.59	0.00	98.75	0.02	/workspace/coverage/cover_reg_top/61.xbar_stress_all_with_reset_error.16673152
96.46	0.01	95.10	0.00	94.26	0.00	97.85	0.00			95.21	0.00	97.59	0.00	98.78	0.02	/workspace/coverage/cover_reg_top/7.xbar_stress_all_with_rand_reset.2437874267
96.47	0.01	95.10	0.00	94.28	0.02	97.85	0.00			95.21	0.00	97.59	0.00	98.78	0.00	/workspace/coverage/cover_reg_top/13.chip_tl_errors.3030404189
96.47	0.01	95.10	0.00	94.28	0.00	97.87	0.02			95.21	0.00	97.59	0.00	98.78	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3163644605
96.47	0.01	95.10	0.00	94.28	0.00	97.88	0.02			95.21	0.00	97.59	0.00	98.78	0.00	/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.2530304522
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96.48	0.01	95.12	0.01	94.30	0.00	97.91	0.01			95.21	0.00	97.59	0.00	98.78	0.00	/workspace/coverage/default/0.chip_sw_plic_sw_irq.949923009
96.49	0.01	95.12	0.00	94.30	0.01	97.92	0.01			95.21	0.00	97.59	0.00	98.78	0.00	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3129751027
96.49	0.01	95.12	0.00	94.31	0.01	97.92	0.00			95.21	0.00	97.59	0.00	98.79	0.01	/workspace/coverage/cover_reg_top/17.chip_tl_errors.613843185
96.49	0.01	95.12	0.00	94.31	0.01	97.92	0.00			95.21	0.00	97.59	0.00	98.80	0.01	/workspace/coverage/default/0.chip_sw_all_escalation_resets.2635177003
96.50	0.01	95.12	0.00	94.32	0.01	97.92	0.00			95.21	0.00	97.59	0.00	98.81	0.01	/workspace/coverage/default/26.chip_sw_all_escalation_resets.745196483
96.50	0.01	95.12	0.00	94.32	0.00	97.94	0.01			95.21	0.00	97.59	0.00	98.81	0.00	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.2835548583
96.50	0.01	95.12	0.00	94.33	0.01	97.94	0.00			95.21	0.00	97.59	0.00	98.81	0.00	/workspace/coverage/cover_reg_top/34.xbar_stress_all.812847473
96.50	0.01	95.12	0.00	94.33	0.00	97.94	0.01			95.21	0.00	97.59	0.00	98.82	0.01	/workspace/coverage/default/20.chip_sw_all_escalation_resets.3666705380
96.50	0.01	95.12	0.00	94.33	0.00	97.94	0.01			95.21	0.00	97.59	0.00	98.84	0.01	/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.508430760
96.51	0.01	95.12	0.00	94.33	0.00	97.94	0.00			95.21	0.00	97.59	0.00	98.85	0.01	/workspace/coverage/cover_reg_top/34.xbar_stress_all_with_reset_error.3196558700
96.51	0.01	95.12	0.00	94.33	0.00	97.94	0.00			95.21	0.00	97.59	0.00	98.86	0.01	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.4005582633
96.51	0.01	95.12	0.00	94.33	0.00	97.94	0.00			95.21	0.00	97.59	0.00	98.87	0.01	/workspace/coverage/default/1.chip_sw_all_escalation_resets.3820770632
96.51	0.01	95.12	0.00	94.33	0.00	97.94	0.00			95.21	0.00	97.59	0.00	98.88	0.01	/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.1528550914
96.51	0.01	95.12	0.00	94.33	0.00	97.94	0.00			95.21	0.00	97.59	0.00	98.90	0.01	/workspace/coverage/default/10.chip_sw_all_escalation_resets.2362232132
96.52	0.01	95.12	0.00	94.33	0.00	97.94	0.00			95.21	0.00	97.59	0.00	98.91	0.01	/workspace/coverage/default/11.chip_sw_all_escalation_resets.3780396567
96.52	0.01	95.12	0.00	94.33	0.00	97.94	0.00			95.21	0.00	97.59	0.00	98.92	0.01	/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.1517449117
96.52	0.01	95.12	0.00	94.33	0.00	97.94	0.00			95.21	0.00	97.59	0.00	98.93	0.01	/workspace/coverage/default/12.chip_sw_all_escalation_resets.1261161091
96.52	0.01	95.12	0.00	94.33	0.00	97.94	0.00			95.21	0.00	97.59	0.00	98.94	0.01	/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.3356591963
96.52	0.01	95.12	0.00	94.33	0.00	97.94	0.00			95.21	0.00	97.59	0.00	98.95	0.01	/workspace/coverage/default/13.chip_sw_all_escalation_resets.1109218279
96.53	0.01	95.12	0.00	94.33	0.00	97.94	0.00			95.21	0.00	97.59	0.00	98.97	0.01	/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.3521628188
96.53	0.01	95.12	0.00	94.33	0.00	97.94	0.00			95.21	0.00	97.59	0.00	98.98	0.01	/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.476216372
96.53	0.01	95.12	0.00	94.33	0.00	97.94	0.00			95.21	0.00	97.59	0.00	98.99	0.01	/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.1417885228
96.53	0.01	95.12	0.00	94.33	0.00	97.94	0.00			95.21	0.00	97.59	0.00	99.00	0.01	/workspace/coverage/default/16.chip_sw_all_escalation_resets.3135434583
96.53	0.01	95.12	0.00	94.33	0.00	97.94	0.00			95.21	0.00	97.59	0.00	99.01	0.01	/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.2096391055
96.54	0.01	95.12	0.00	94.33	0.00	97.94	0.00			95.21	0.00	97.59	0.00	99.02	0.01	/workspace/coverage/default/17.chip_sw_all_escalation_resets.3126797495
96.54	0.01	95.12	0.00	94.33	0.00	97.94	0.00			95.21	0.00	97.59	0.00	99.04	0.01	/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.4050194591
96.54	0.01	95.12	0.00	94.33	0.00	97.94	0.00			95.21	0.00	97.59	0.00	99.05	0.01	/workspace/coverage/default/18.chip_sw_all_escalation_resets.3816345102
96.54	0.01	95.12	0.00	94.33	0.00	97.94	0.00			95.21	0.00	97.59	0.00	99.06	0.01	/workspace/coverage/default/19.chip_sw_all_escalation_resets.2699118686
96.54	0.01	95.12	0.00	94.33	0.00	97.94	0.00			95.21	0.00	97.59	0.00	99.07	0.01	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.1762011552
96.55	0.01	95.12	0.00	94.33	0.00	97.94	0.00			95.21	0.00	97.59	0.00	99.08	0.01	/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.4031127866
96.55	0.01	95.12	0.00	94.33	0.00	97.94	0.00			95.21	0.00	97.59	0.00	99.10	0.01	/workspace/coverage/default/21.chip_sw_all_escalation_resets.977775132
96.55	0.01	95.12	0.00	94.33	0.00	97.94	0.00			95.21	0.00	97.59	0.00	99.11	0.01	/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.2346933110
96.55	0.01	95.12	0.00	94.33	0.00	97.94	0.00			95.21	0.00	97.59	0.00	99.12	0.01	/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.381626379
96.55	0.01	95.12	0.00	94.33	0.00	97.94	0.00			95.21	0.00	97.59	0.00	99.13	0.01	/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.1149205196
96.56	0.01	95.12	0.00	94.33	0.00	97.94	0.00			95.21	0.00	97.59	0.00	99.14	0.01	/workspace/coverage/default/24.chip_sw_all_escalation_resets.28988324
96.56	0.01	95.12	0.00	94.33	0.00	97.94	0.00			95.21	0.00	97.59	0.00	99.15	0.01	/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.3679103171
96.56	0.01	95.12	0.00	94.33	0.00	97.94	0.00			95.21	0.00	97.59	0.00	99.17	0.01	/workspace/coverage/default/25.chip_sw_all_escalation_resets.3477604392
96.56	0.01	95.12	0.00	94.33	0.00	97.94	0.00			95.21	0.00	97.59	0.00	99.18	0.01	/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.862775470
96.56	0.01	95.12	0.00	94.33	0.00	97.94	0.00			95.21	0.00	97.59	0.00	99.19	0.01	/workspace/coverage/default/27.chip_sw_all_escalation_resets.1799090159
96.57	0.01	95.12	0.00	94.33	0.00	97.94	0.00			95.21	0.00	97.59	0.00	99.20	0.01	/workspace/coverage/default/28.chip_sw_all_escalation_resets.484948996
96.57	0.01	95.12	0.00	94.33	0.00	97.94	0.00			95.21	0.00	97.59	0.00	99.21	0.01	/workspace/coverage/default/29.chip_sw_all_escalation_resets.3182466052
96.57	0.01	95.12	0.00	94.33	0.00	97.94	0.00			95.21	0.00	97.59	0.00	99.22	0.01	/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.215892179
96.57	0.01	95.12	0.00	94.33	0.00	97.94	0.00			95.21	0.00	97.59	0.00	99.24	0.01	/workspace/coverage/default/34.chip_sw_all_escalation_resets.3017395027
96.57	0.01	95.12	0.00	94.33	0.00	97.94	0.00			95.21	0.00	97.59	0.00	99.25	0.01	/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.373635569
96.58	0.01	95.12	0.00	94.33	0.00	97.94	0.00			95.21	0.00	97.59	0.00	99.26	0.01	/workspace/coverage/default/39.chip_sw_all_escalation_resets.3028636389
96.58	0.01	95.12	0.00	94.33	0.00	97.94	0.00			95.21	0.00	97.59	0.00	99.27	0.01	/workspace/coverage/default/4.chip_sw_all_escalation_resets.1410749104
96.58	0.01	95.12	0.00	94.33	0.00	97.94	0.00			95.21	0.00	97.59	0.00	99.28	0.01	/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.2725759012
96.58	0.01	95.12	0.00	94.33	0.00	97.94	0.00			95.21	0.00	97.59	0.00	99.29	0.01	/workspace/coverage/default/42.chip_sw_all_escalation_resets.2782329166
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96.59	0.01	95.12	0.00	94.33	0.00	97.94	0.00			95.21	0.00	97.59	0.00	99.32	0.01	/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.1242614903
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96.59	0.01	95.12	0.00	94.33	0.00	97.94	0.00			95.21	0.00	97.59	0.00	99.34	0.01	/workspace/coverage/default/48.chip_sw_all_escalation_resets.2828022512
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96.64	0.01	95.13	0.01	94.39	0.01	97.95	0.00			95.21	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_pattgen_ios.3837525689
96.64	0.01	95.13	0.00	94.39	0.00	97.96	0.01			95.21	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.1981069779
96.64	0.01	95.13	0.00	94.39	0.00	97.97	0.01			95.21	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.613540643
96.65	0.01	95.14	0.01	94.39	0.01	97.97	0.01			95.21	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_uart_rand_baudrate.1932595662
96.65	0.01	95.14	0.01	94.39	0.01	97.97	0.01			95.21	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.1797006961
96.65	0.01	95.14	0.00	94.39	0.00	97.97	0.00			95.22	0.01	97.59	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.275191887
96.65	0.01	95.14	0.00	94.40	0.01	97.97	0.00			95.22	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/47.xbar_access_same_device_slow_rsp.2748472533
96.65	0.01	95.14	0.00	94.41	0.01	97.97	0.00			95.22	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/55.xbar_stress_all_with_reset_error.2552853575
96.65	0.01	95.14	0.00	94.42	0.01	97.97	0.00			95.22	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.1798964179
96.65	0.01	95.14	0.00	94.42	0.01	97.97	0.00			95.22	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_spi_device_tx_rx.2480647777
96.65	0.01	95.15	0.01	94.42	0.00	97.97	0.00			95.22	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.2581522310
96.66	0.01	95.15	0.00	94.42	0.00	97.98	0.01			95.22	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_edn_boot_mode.137571448
96.66	0.01	95.15	0.00	94.42	0.00	97.98	0.01			95.22	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.2439155615
96.66	0.01	95.15	0.00	94.42	0.00	97.99	0.01			95.22	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1408647053
96.66	0.01	95.15	0.00	94.42	0.00	97.99	0.01			95.22	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/default/1.chip_sw_flash_init.781021732
96.66	0.01	95.15	0.00	94.42	0.00	98.00	0.01			95.22	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.2426869118
96.66	0.01	95.15	0.00	94.42	0.00	98.00	0.01			95.22	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/default/0.chip_tap_straps_rma.163688925
96.66	0.01	95.15	0.00	94.43	0.01	98.00	0.00			95.22	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.790997305
96.66	0.01	95.15	0.00	94.43	0.01	98.00	0.00			95.22	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.574830256
96.66	0.01	95.15	0.00	94.43	0.01	98.00	0.00			95.22	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/13.xbar_error_random.2652457835
96.66	0.01	95.15	0.00	94.44	0.01	98.00	0.00			95.22	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.4278875812
96.66	0.01	95.15	0.00	94.44	0.01	98.00	0.00			95.22	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/19.xbar_stress_all_with_rand_reset.2366307783
96.66	0.01	95.15	0.00	94.45	0.01	98.00	0.00			95.22	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/2.xbar_error_and_unmapped_addr.298000886
96.66	0.01	95.15	0.00	94.45	0.01	98.00	0.00			95.22	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/27.chip_tl_errors.3778924328
96.66	0.01	95.15	0.00	94.45	0.01	98.00	0.00			95.22	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/43.xbar_stress_all_with_error.1721293162
96.66	0.01	95.15	0.00	94.46	0.01	98.00	0.00			95.22	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/63.xbar_stress_all_with_error.643237307
96.67	0.01	95.15	0.00	94.46	0.01	98.00	0.00			95.22	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/73.xbar_stress_all_with_error.2439626634
96.67	0.01	95.15	0.00	94.46	0.01	98.00	0.00			95.22	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/76.xbar_stress_all_with_error.1021095475
96.67	0.01	95.15	0.00	94.47	0.01	98.00	0.00			95.22	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/8.xbar_error_and_unmapped_addr.213034141
96.67	0.01	95.15	0.00	94.47	0.01	98.00	0.00			95.22	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/81.xbar_stress_all_with_error.3644421254
96.67	0.01	95.15	0.00	94.47	0.01	98.00	0.00			95.22	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_aon_timer_irq.3731619448
96.67	0.01	95.15	0.00	94.48	0.01	98.00	0.00			95.22	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.626162254
96.67	0.01	95.15	0.00	94.48	0.01	98.00	0.00			95.22	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_hmac_enc.1894620732
96.67	0.01	95.15	0.00	94.49	0.01	98.00	0.00			95.22	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.4135113167
96.67	0.01	95.15	0.00	94.49	0.01	98.00	0.00			95.22	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.3272662388
96.67	0.01	95.15	0.00	94.49	0.01	98.00	0.00			95.22	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_20.2364565673
96.67	0.01	95.15	0.00	94.49	0.00	98.00	0.01			95.22	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.1615597074
96.67	0.01	95.15	0.00	94.49	0.00	98.00	0.01			95.22	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.176276544
96.67	0.01	95.15	0.00	94.49	0.00	98.01	0.01			95.22	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.1342719132
96.67	0.01	95.15	0.00	94.49	0.00	98.01	0.01			95.22	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.2459221576
96.67	0.01	95.15	0.00	94.49	0.00	98.01	0.01			95.22	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.1428650035

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.3221827051
/workspace/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.2911391625
/workspace/coverage/cover_reg_top/0.chip_csr_rw.1600002845
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.2448536887
/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.3140540521
/workspace/coverage/cover_reg_top/0.chip_tl_errors.4166661913
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.1397634445
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.765761487
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.2795740272
/workspace/coverage/cover_reg_top/0.xbar_error_random.145089362
/workspace/coverage/cover_reg_top/0.xbar_random.3507177679
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.3604736663
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.3096921690
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.2199452831
/workspace/coverage/cover_reg_top/0.xbar_same_source.2730950416
/workspace/coverage/cover_reg_top/0.xbar_smoke.2399330421
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.3357195225
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.3964166051
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.2731276179
/workspace/coverage/cover_reg_top/0.xbar_stress_all.1567481965
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.2286834229
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.3821852543
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.3711785677
/workspace/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.3810100238
/workspace/coverage/cover_reg_top/1.chip_csr_rw.694214298
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.344874116
/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.4015011718
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.2475654391
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.1441427519
/workspace/coverage/cover_reg_top/1.xbar_error_random.1833239138
/workspace/coverage/cover_reg_top/1.xbar_random.3877662936
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.2580813442
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.244021286
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.3899152211
/workspace/coverage/cover_reg_top/1.xbar_same_source.2046755115
/workspace/coverage/cover_reg_top/1.xbar_smoke.3203592291
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.2067011656
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.3009637645
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.3507080007
/workspace/coverage/cover_reg_top/1.xbar_stress_all.2693810643
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.2075950552
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.1179361185
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.3450958984
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.3434646135
/workspace/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.1819665285
/workspace/coverage/cover_reg_top/10.chip_csr_rw.4289107449
/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.4294207945
/workspace/coverage/cover_reg_top/10.chip_tl_errors.1996697431
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.3685313988
/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.816866990
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.3933795332
/workspace/coverage/cover_reg_top/10.xbar_error_random.1425867223
/workspace/coverage/cover_reg_top/10.xbar_random.1534465303
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.1523394368
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.2132701808
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.3545183899
/workspace/coverage/cover_reg_top/10.xbar_same_source.598505566
/workspace/coverage/cover_reg_top/10.xbar_smoke.1452779826
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.383826814
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.323199989
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.1493525725
/workspace/coverage/cover_reg_top/10.xbar_stress_all.248661940
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.822055308
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.107117760
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.3801002492
/workspace/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.3324370774
/workspace/coverage/cover_reg_top/11.chip_csr_rw.1539003593
/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.2653475521
/workspace/coverage/cover_reg_top/11.chip_tl_errors.523781376
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.1336764416
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.2561856886
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.2527960230
/workspace/coverage/cover_reg_top/11.xbar_error_random.813028683
/workspace/coverage/cover_reg_top/11.xbar_random.2553603168
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.2186986816
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.3083860777
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.315189977
/workspace/coverage/cover_reg_top/11.xbar_same_source.2090283682
/workspace/coverage/cover_reg_top/11.xbar_smoke.2336813666
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.703319070
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.2869009249
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.4097335944
/workspace/coverage/cover_reg_top/11.xbar_stress_all.2963794774
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.3575977679
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.32388821
/workspace/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.1380181520
/workspace/coverage/cover_reg_top/12.chip_csr_rw.4184336282
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.4065831451
/workspace/coverage/cover_reg_top/12.chip_tl_errors.2388116137
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.165441997
/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.368471050
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.2719163473
/workspace/coverage/cover_reg_top/12.xbar_error_random.284843170
/workspace/coverage/cover_reg_top/12.xbar_random.186098611
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.767095573
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.647037466
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.2123902198
/workspace/coverage/cover_reg_top/12.xbar_same_source.245609737
/workspace/coverage/cover_reg_top/12.xbar_smoke.428441178
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.3700070164
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.2765796117
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.518768399
/workspace/coverage/cover_reg_top/12.xbar_stress_all.1780442080
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.2878957443
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.4050297710
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.2460594345
/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.1453614681
/workspace/coverage/cover_reg_top/13.chip_csr_mem_rw_with_rand_reset.3549767676
/workspace/coverage/cover_reg_top/13.chip_csr_rw.3849831226
/workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.2611230440
/workspace/coverage/cover_reg_top/13.xbar_access_same_device.3841464929
/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.2803428802
/workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.4113686621
/workspace/coverage/cover_reg_top/13.xbar_random.707134308
/workspace/coverage/cover_reg_top/13.xbar_random_large_delays.62382705
/workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.3339963391
/workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.2528212783
/workspace/coverage/cover_reg_top/13.xbar_same_source.2226945642
/workspace/coverage/cover_reg_top/13.xbar_smoke.687838769
/workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.78755197
/workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.3692034019
/workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.1275166304
/workspace/coverage/cover_reg_top/13.xbar_stress_all.723470291
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.1319868532
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.3647683199
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.1582239939
/workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.2998404552
/workspace/coverage/cover_reg_top/14.chip_csr_mem_rw_with_rand_reset.720234619
/workspace/coverage/cover_reg_top/14.chip_csr_rw.986404434
/workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.3003387458
/workspace/coverage/cover_reg_top/14.chip_tl_errors.1546893218
/workspace/coverage/cover_reg_top/14.xbar_access_same_device.1780619083
/workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.600002277
/workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.2253403659
/workspace/coverage/cover_reg_top/14.xbar_error_random.1788290068
/workspace/coverage/cover_reg_top/14.xbar_random.881834509
/workspace/coverage/cover_reg_top/14.xbar_random_large_delays.2796616193
/workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.834266573
/workspace/coverage/cover_reg_top/14.xbar_random_zero_delays.1738517191
/workspace/coverage/cover_reg_top/14.xbar_same_source.1587095041
/workspace/coverage/cover_reg_top/14.xbar_smoke.692543582
/workspace/coverage/cover_reg_top/14.xbar_smoke_large_delays.2459257505
/workspace/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.2646428169
/workspace/coverage/cover_reg_top/14.xbar_smoke_zero_delays.2926602968
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/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.3212093146
/workspace/coverage/default/30.chip_sw_all_escalation_resets.3773085939
/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.3173010845
/workspace/coverage/default/32.chip_sw_all_escalation_resets.1379881759
/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.3169683715
/workspace/coverage/default/33.chip_sw_all_escalation_resets.1315300312
/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.1784593732
/workspace/coverage/default/35.chip_sw_all_escalation_resets.1439368555
/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.1131497949
/workspace/coverage/default/36.chip_sw_all_escalation_resets.2378457426
/workspace/coverage/default/37.chip_sw_all_escalation_resets.11997759
/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.2862323992
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.1839911511
/workspace/coverage/default/4.chip_sw_data_integrity_escalation.1015811718
/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.2318188714
/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.164747673
/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.1117414320
/workspace/coverage/default/4.chip_sw_uart_tx_rx.2045961667
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.1336527173
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1607801972
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.1540619459
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.4132899751
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.2022198056
/workspace/coverage/default/4.chip_tap_straps_dev.3925355297
/workspace/coverage/default/4.chip_tap_straps_prod.3651739423
/workspace/coverage/default/4.chip_tap_straps_rma.3279190859
/workspace/coverage/default/4.chip_tap_straps_testunlock0.994123478
/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.430877953
/workspace/coverage/default/40.chip_sw_all_escalation_resets.3056842469
/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.3603815429
/workspace/coverage/default/41.chip_sw_all_escalation_resets.3744410917
/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.158212176
/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.2040313492
/workspace/coverage/default/45.chip_sw_all_escalation_resets.2340766282
/workspace/coverage/default/46.chip_sw_all_escalation_resets.3088027057
/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.2305980147
/workspace/coverage/default/47.chip_sw_all_escalation_resets.2752165284
/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.1507640860
/workspace/coverage/default/49.chip_sw_all_escalation_resets.3720179130
/workspace/coverage/default/5.chip_sw_all_escalation_resets.3452998217
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.1702593803
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.1672802921
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.2931360570
/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.2153356773
/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.333245000
/workspace/coverage/default/51.chip_sw_all_escalation_resets.2973461811
/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.1331466725
/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.1619006336
/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.3657193664
/workspace/coverage/default/54.chip_sw_all_escalation_resets.3651566620
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.2646234399
/workspace/coverage/default/55.chip_sw_all_escalation_resets.1152904741
/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.3514005301
/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.866362120
/workspace/coverage/default/58.chip_sw_all_escalation_resets.3604414550
/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.535235825
/workspace/coverage/default/59.chip_sw_all_escalation_resets.3880370292
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.1586682165
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.89655676
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.4098971414
/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.293428493
/workspace/coverage/default/60.chip_sw_all_escalation_resets.1147546601
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.132254914
/workspace/coverage/default/61.chip_sw_all_escalation_resets.1149872460
/workspace/coverage/default/62.chip_sw_all_escalation_resets.3531834115
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.2933854389
/workspace/coverage/default/63.chip_sw_all_escalation_resets.3256403249
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.1286199615
/workspace/coverage/default/64.chip_sw_all_escalation_resets.3969369233
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.2111041207
/workspace/coverage/default/65.chip_sw_all_escalation_resets.2314926170
/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.818237374
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.1757962834
/workspace/coverage/default/67.chip_sw_all_escalation_resets.3423409274
/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.3380604119
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.340331169
/workspace/coverage/default/7.chip_sw_all_escalation_resets.475883983
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.3579730264
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.3195394671
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.422973316
/workspace/coverage/default/71.chip_sw_all_escalation_resets.2900288474
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.1211300619
/workspace/coverage/default/72.chip_sw_all_escalation_resets.2566951830
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.2335399154
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.1167862057
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.1180636142
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.3376529316
/workspace/coverage/default/76.chip_sw_all_escalation_resets.2688564402
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.42234810
/workspace/coverage/default/77.chip_sw_all_escalation_resets.3372813374
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.602901595
/workspace/coverage/default/78.chip_sw_all_escalation_resets.3513408125
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.3730593182
/workspace/coverage/default/79.chip_sw_all_escalation_resets.1243368747
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.1958545330
/workspace/coverage/default/8.chip_sw_all_escalation_resets.4265516499
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.1638797965
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.3615684037
/workspace/coverage/default/80.chip_sw_all_escalation_resets.2473925204
/workspace/coverage/default/81.chip_sw_all_escalation_resets.3110521247
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.972665360
/workspace/coverage/default/82.chip_sw_all_escalation_resets.3719290603
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.3578268410
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.2831970654
/workspace/coverage/default/84.chip_sw_all_escalation_resets.2379609096
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.1035047629
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.1997613136
/workspace/coverage/default/86.chip_sw_all_escalation_resets.1626705108
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.3564272589
/workspace/coverage/default/87.chip_sw_all_escalation_resets.3441961830
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.635755925
/workspace/coverage/default/88.chip_sw_all_escalation_resets.3705824606
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.80194034
/workspace/coverage/default/89.chip_sw_all_escalation_resets.227556252
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.3763443198
/workspace/coverage/default/9.chip_sw_all_escalation_resets.2841429229
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.463931588
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.3459407422
/workspace/coverage/default/90.chip_sw_all_escalation_resets.2164531239
/workspace/coverage/default/91.chip_sw_all_escalation_resets.3754838230
/workspace/coverage/default/92.chip_sw_all_escalation_resets.1085416948
/workspace/coverage/default/94.chip_sw_all_escalation_resets.2649960630
/workspace/coverage/default/95.chip_sw_all_escalation_resets.2272504024
/workspace/coverage/default/96.chip_sw_all_escalation_resets.3429220157
/workspace/coverage/default/99.chip_sw_all_escalation_resets.3937157695
/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.2277046637
/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.961509534
/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.3659017024
/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.3225340662
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.2989759467
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.2226191392
/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.4225802733
/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.2566894934

---

Total test records in report: 2848

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tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html | tests35.html | tests36.html | tests37.html | tests38.html | tests39.html | tests40.html | tests41.html | tests42.html | tests43.html | tests44.html | tests45.html | tests46.html | tests47.html | tests48.html | tests49.html | tests50.html | tests51.html | tests52.html | tests53.html | tests54.html | tests55.html | tests56.html | tests57.html | tests58.html | tests59.html | tests60.html

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T29	/workspace/coverage/cover_reg_top/89.xbar_unmapped_addr.1615255810			Jan 21 07:13:25 PM PST 24	Jan 21 07:13:59 PM PST 24	255623252 ps
T30	/workspace/coverage/cover_reg_top/6.xbar_error_random.8697912			Jan 21 06:21:01 PM PST 24	Jan 21 06:22:15 PM PST 24	1783937858 ps
T31	/workspace/coverage/cover_reg_top/50.xbar_smoke_slow_rsp.1733383997			Jan 21 07:11:45 PM PST 24	Jan 21 07:13:06 PM PST 24	4522031792 ps
T59	/workspace/coverage/cover_reg_top/64.xbar_smoke_zero_delays.2599409430			Jan 21 07:02:18 PM PST 24	Jan 21 07:02:30 PM PST 24	44880598 ps
T60	/workspace/coverage/cover_reg_top/48.xbar_smoke_large_delays.513195725			Jan 21 06:53:56 PM PST 24	Jan 21 06:55:46 PM PST 24	10459528255 ps
T61	/workspace/coverage/cover_reg_top/55.xbar_unmapped_addr.1962148639			Jan 21 06:57:52 PM PST 24	Jan 21 06:58:16 PM PST 24	163155822 ps
T313	/workspace/coverage/cover_reg_top/51.xbar_unmapped_addr.3905393119			Jan 21 06:55:49 PM PST 24	Jan 21 06:56:25 PM PST 24	810759633 ps
T314	/workspace/coverage/cover_reg_top/46.xbar_smoke.971058847			Jan 21 07:10:43 PM PST 24	Jan 21 07:10:53 PM PST 24	48388647 ps
T188	/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.2719163473			Jan 21 06:29:07 PM PST 24	Jan 21 06:29:28 PM PST 24	431391765 ps
T131	/workspace/coverage/cover_reg_top/26.xbar_stress_all.3538292344			Jan 21 06:41:18 PM PST 24	Jan 21 06:41:28 PM PST 24	174376780 ps
T114	/workspace/coverage/cover_reg_top/99.xbar_stress_all_with_reset_error.1992687348			Jan 21 07:32:48 PM PST 24	Jan 21 07:39:54 PM PST 24	3091368564 ps
T132	/workspace/coverage/cover_reg_top/2.xbar_stress_all_with_rand_reset.176945026			Jan 21 06:16:36 PM PST 24	Jan 21 06:19:31 PM PST 24	372422673 ps
T115	/workspace/coverage/cover_reg_top/34.xbar_stress_all_with_error.3008298432			Jan 21 06:46:34 PM PST 24	Jan 21 06:49:26 PM PST 24	4384712006 ps
T357	/workspace/coverage/cover_reg_top/45.xbar_random_slow_rsp.3926443090			Jan 21 06:52:23 PM PST 24	Jan 21 07:11:47 PM PST 24	64308814064 ps
T358	/workspace/coverage/cover_reg_top/43.xbar_random_zero_delays.3555583338			Jan 21 06:51:04 PM PST 24	Jan 21 06:51:37 PM PST 24	313264098 ps
T417	/workspace/coverage/cover_reg_top/31.xbar_error_random.312946120			Jan 21 06:44:38 PM PST 24	Jan 21 06:44:56 PM PST 24	391581908 ps
T377	/workspace/coverage/cover_reg_top/95.xbar_random.817277304			Jan 21 07:15:45 PM PST 24	Jan 21 07:16:32 PM PST 24	500687281 ps
T356	/workspace/coverage/cover_reg_top/59.xbar_access_same_device_slow_rsp.365452761			Jan 21 06:59:52 PM PST 24	Jan 21 07:34:02 PM PST 24	115333318833 ps
T28	/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.1798308909			Jan 21 06:13:57 PM PST 24	Jan 21 06:24:03 PM PST 24	12943383563 ps
T413	/workspace/coverage/cover_reg_top/78.xbar_random_zero_delays.1471298398			Jan 21 07:08:42 PM PST 24	Jan 21 07:09:31 PM PST 24	563147977 ps
T414	/workspace/coverage/cover_reg_top/73.xbar_stress_all_with_rand_reset.614634526			Jan 21 07:06:51 PM PST 24	Jan 21 07:08:37 PM PST 24	283826744 ps
T419	/workspace/coverage/cover_reg_top/75.xbar_stress_all_with_reset_error.3032507651			Jan 21 07:07:42 PM PST 24	Jan 21 07:11:50 PM PST 24	764994953 ps
T411	/workspace/coverage/cover_reg_top/79.xbar_stress_all_with_rand_reset.961657518			Jan 21 07:36:44 PM PST 24	Jan 21 07:43:17 PM PST 24	3425957279 ps
T376	/workspace/coverage/cover_reg_top/53.xbar_random_slow_rsp.926032299			Jan 21 06:56:44 PM PST 24	Jan 21 07:00:37 PM PST 24	12237686683 ps
T359	/workspace/coverage/cover_reg_top/34.xbar_stress_all.812847473			Jan 21 06:46:23 PM PST 24	Jan 21 06:49:53 PM PST 24	2544137490 ps
T410	/workspace/coverage/cover_reg_top/83.xbar_stress_all_with_rand_reset.3535880117			Jan 21 07:33:50 PM PST 24	Jan 21 07:41:34 PM PST 24	3027349051 ps
T930	/workspace/coverage/cover_reg_top/75.xbar_stress_all_with_rand_reset.1080086687			Jan 21 07:07:34 PM PST 24	Jan 21 07:07:54 PM PST 24	22546218 ps
T418	/workspace/coverage/cover_reg_top/1.xbar_access_same_device.4215745066			Jan 21 06:14:39 PM PST 24	Jan 21 06:16:21 PM PST 24	1315700460 ps
T420	/workspace/coverage/cover_reg_top/16.xbar_stress_all_with_error.1357882108			Jan 21 06:32:50 PM PST 24	Jan 21 06:34:12 PM PST 24	963145484 ps
T378	/workspace/coverage/cover_reg_top/24.xbar_random_zero_delays.1408449527			Jan 21 06:39:13 PM PST 24	Jan 21 06:39:29 PM PST 24	155206178 ps
T874	/workspace/coverage/cover_reg_top/55.xbar_access_same_device_slow_rsp.1337436824			Jan 21 06:57:50 PM PST 24	Jan 21 07:11:48 PM PST 24	44850674755 ps
T422	/workspace/coverage/cover_reg_top/19.xbar_error_random.3192689417			Jan 21 07:04:43 PM PST 24	Jan 21 07:05:38 PM PST 24	1255077384 ps
T375	/workspace/coverage/cover_reg_top/48.xbar_random_zero_delays.1808012224			Jan 21 06:53:53 PM PST 24	Jan 21 06:54:24 PM PST 24	283849925 ps
T423	/workspace/coverage/cover_reg_top/99.xbar_smoke_zero_delays.1978453638			Jan 21 07:17:10 PM PST 24	Jan 21 07:17:17 PM PST 24	41807448 ps
T931	/workspace/coverage/cover_reg_top/99.xbar_smoke_slow_rsp.1973871674			Jan 21 07:17:15 PM PST 24	Jan 21 07:18:37 PM PST 24	4636657534 ps
T424	/workspace/coverage/cover_reg_top/63.xbar_stress_all_with_reset_error.2811559372			Jan 21 07:02:13 PM PST 24	Jan 21 07:04:26 PM PST 24	442118117 ps
T932	/workspace/coverage/cover_reg_top/91.xbar_error_random.332410877			Jan 21 07:29:57 PM PST 24	Jan 21 07:30:05 PM PST 24	24593647 ps
T409	/workspace/coverage/cover_reg_top/56.xbar_random_zero_delays.2972450156			Jan 21 06:58:05 PM PST 24	Jan 21 06:58:13 PM PST 24	23629291 ps
T1	/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.1392582250			Jan 21 08:56:09 PM PST 24	Jan 21 09:01:04 PM PST 24	3969883195 ps
T2	/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.4225802733			Jan 21 08:56:10 PM PST 24	Jan 21 09:00:49 PM PST 24	4870546927 ps
T3	/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.3659017024			Jan 21 08:56:08 PM PST 24	Jan 21 09:01:35 PM PST 24	4786040185 ps
T7	/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.2226191392			Jan 21 08:56:11 PM PST 24	Jan 21 09:00:48 PM PST 24	4224728472 ps
T67	/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.2989759467			Jan 21 08:56:09 PM PST 24	Jan 21 09:01:33 PM PST 24	4633134018 ps
T68	/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.961509534			Jan 21 08:56:02 PM PST 24	Jan 21 09:01:44 PM PST 24	5342418574 ps
T69	/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.3811702641			Jan 21 08:56:08 PM PST 24	Jan 21 09:00:56 PM PST 24	5415746724 ps
T70	/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.3225340662			Jan 21 08:56:11 PM PST 24	Jan 21 09:00:50 PM PST 24	5578861935 ps
T71	/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.2566894934			Jan 21 08:56:11 PM PST 24	Jan 21 09:00:58 PM PST 24	5374326968 ps
T72	/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.2277046637			Jan 21 08:56:03 PM PST 24	Jan 21 09:00:36 PM PST 24	4443763367 ps
T17	/workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.990951028			Jan 21 04:22:19 PM PST 24	Jan 21 04:29:13 PM PST 24	7298702572 ps
T18	/workspace/coverage/default/0.chip_plic_all_irqs_0.2210442922			Jan 21 04:25:03 PM PST 24	Jan 21 04:43:31 PM PST 24	6061434000 ps
T19	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.396470721			Jan 21 04:42:44 PM PST 24	Jan 21 04:52:43 PM PST 24	4981898836 ps
T20	/workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.3555594278			Jan 21 04:44:30 PM PST 24	Jan 21 04:53:20 PM PST 24	4513110560 ps
T98	/workspace/coverage/default/2.chip_sw_edn_auto_mode.1681739			Jan 21 04:53:52 PM PST 24	Jan 21 05:10:57 PM PST 24	4692775048 ps
T147	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.118684126			Jan 21 05:12:45 PM PST 24	Jan 21 05:23:07 PM PST 24	4332578806 ps
T148	/workspace/coverage/default/2.chip_sw_uart_smoketest.2660065863			Jan 21 05:02:23 PM PST 24	Jan 21 05:07:24 PM PST 24	3205045590 ps
T145	/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.3225580161			Jan 21 05:13:11 PM PST 24	Jan 21 05:21:37 PM PST 24	4440023332 ps
T99	/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.3603815429			Jan 21 05:12:11 PM PST 24	Jan 21 05:20:42 PM PST 24	4298275084 ps
T100	/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.253585821			Jan 21 05:05:45 PM PST 24	Jan 21 05:19:36 PM PST 24	5159972856 ps
T193	/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.508430760			Jan 21 05:55:46 PM PST 24	Jan 21 06:04:45 PM PST 24	3915314258 ps
T44	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.1204502369			Jan 21 04:55:25 PM PST 24	Jan 21 05:04:43 PM PST 24	4545138603 ps
T41	/workspace/coverage/default/7.chip_sw_all_escalation_resets.475883983			Jan 21 06:45:38 PM PST 24	Jan 21 06:57:57 PM PST 24	4828523824 ps
T50	/workspace/coverage/default/2.chip_jtag_mem_access.984905205			Jan 21 05:53:09 PM PST 24	Jan 21 06:20:40 PM PST 24	13237187130 ps
T42	/workspace/coverage/default/2.chip_sw_data_integrity_escalation.2124658555			Jan 21 04:46:57 PM PST 24	Jan 21 05:03:06 PM PST 24	6114828358 ps
T216	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.656457437			Jan 21 04:35:05 PM PST 24	Jan 21 04:54:11 PM PST 24	5782109336 ps
T217	/workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.3431163433			Jan 21 04:47:09 PM PST 24	Jan 21 04:51:55 PM PST 24	3182876450 ps
T218	/workspace/coverage/default/1.chip_sw_uart_smoketest.2220340915			Jan 21 04:45:50 PM PST 24	Jan 21 04:50:34 PM PST 24	2909026250 ps
T105	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.2220568617			Jan 21 04:55:25 PM PST 24	Jan 21 05:03:56 PM PST 24	3721576217 ps
T24	/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.1809550147			Jan 21 05:00:07 PM PST 24	Jan 21 05:06:08 PM PST 24	3902191245 ps
T170	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation.4079170091			Jan 21 05:16:19 PM PST 24	Jan 21 05:26:25 PM PST 24	5580050414 ps
T43	/workspace/coverage/default/81.chip_sw_all_escalation_resets.3110521247			Jan 21 07:33:42 PM PST 24	Jan 21 07:45:20 PM PST 24	5812864120 ps
T106	/workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.1344596829			Jan 21 06:50:38 PM PST 24	Jan 21 07:06:42 PM PST 24	4889171601 ps
T113	/workspace/coverage/default/2.chip_sw_edn_sw_mode.3585090991			Jan 21 07:38:03 PM PST 24	Jan 21 07:56:09 PM PST 24	5710468660 ps
T52	/workspace/coverage/default/1.chip_tap_straps_dev.333531229			Jan 21 04:41:59 PM PST 24	Jan 21 05:11:32 PM PST 24	14158207124 ps
T161	/workspace/coverage/default/1.chip_sival_flash_info_access.21013598			Jan 21 06:17:18 PM PST 24	Jan 21 06:26:12 PM PST 24	3753797872 ps
T171	/workspace/coverage/default/0.rom_keymgr_functest.2751944414			Jan 21 04:32:50 PM PST 24	Jan 21 04:41:06 PM PST 24	4121833280 ps
T104	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.933867052			Jan 21 05:56:08 PM PST 24	Jan 21 07:10:51 PM PST 24	18582673203 ps
T149	/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.3514005301			Jan 21 05:14:21 PM PST 24	Jan 21 05:22:10 PM PST 24	3633264982 ps
T933	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.1750989842			Jan 21 04:22:11 PM PST 24	Jan 21 04:27:21 PM PST 24	2717209016 ps
T737	/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.2153356773			Jan 21 05:13:44 PM PST 24	Jan 21 05:22:26 PM PST 24	3312267600 ps
T256	/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.3260363124			Jan 21 07:28:35 PM PST 24	Jan 21 07:46:06 PM PST 24	6166817716 ps
T399	/workspace/coverage/default/0.chip_sw_kmac_entropy.3659541871			Jan 21 04:20:36 PM PST 24	Jan 21 04:25:42 PM PST 24	2779385088 ps
T139	/workspace/coverage/default/0.chip_sw_spi_device_tx_rx.2480647777			Jan 21 04:18:28 PM PST 24	Jan 21 04:26:03 PM PST 24	3319176572 ps
T729	/workspace/coverage/default/2.chip_sw_aes_masking_off.3865663694			Jan 21 04:53:22 PM PST 24	Jan 21 04:58:08 PM PST 24	3082511056 ps
T146	/workspace/coverage/default/20.chip_sw_all_escalation_resets.3666705380			Jan 21 05:07:56 PM PST 24	Jan 21 05:18:31 PM PST 24	4153046276 ps
T742	/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.1586682165			Jan 21 07:21:46 PM PST 24	Jan 21 07:28:54 PM PST 24	3589991552 ps
T732	/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.2111041207			Jan 21 05:15:16 PM PST 24	Jan 21 05:22:40 PM PST 24	3029854800 ps
T109	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3142975278			Jan 21 04:21:21 PM PST 24	Jan 21 05:10:48 PM PST 24	24589408748 ps
T266	/workspace/coverage/default/2.chip_sw_otbn_randomness.4234705824			Jan 21 06:38:05 PM PST 24	Jan 21 06:48:56 PM PST 24	6510870400 ps
T317	/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.1493379636			Jan 21 05:02:37 PM PST 24	Jan 21 05:10:12 PM PST 24	3558590212 ps
T162	/workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.1006186620			Jan 21 04:49:05 PM PST 24	Jan 21 05:21:41 PM PST 24	7000987594 ps
T156	/workspace/coverage/default/24.chip_sw_all_escalation_resets.28988324			Jan 21 05:09:18 PM PST 24	Jan 21 05:21:22 PM PST 24	5016844108 ps
T934	/workspace/coverage/default/1.chip_sw_aes_idle.610348422			Jan 21 05:10:25 PM PST 24	Jan 21 05:14:10 PM PST 24	2084976340 ps
T155	/workspace/coverage/default/53.chip_sw_all_escalation_resets.3301226441			Jan 21 05:13:33 PM PST 24	Jan 21 05:24:06 PM PST 24	5083029028 ps
T267	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.1797006961			Jan 21 04:18:42 PM PST 24	Jan 21 04:35:28 PM PST 24	5022167070 ps
T935	/workspace/coverage/default/0.chip_sw_hmac_smoketest.2310157464			Jan 21 04:33:27 PM PST 24	Jan 21 04:40:05 PM PST 24	3130559176 ps
T936	/workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.4105139413			Jan 21 04:45:12 PM PST 24	Jan 21 04:49:24 PM PST 24	3534142040 ps
T937	/workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.2786085746			Jan 21 07:27:27 PM PST 24	Jan 21 07:32:13 PM PST 24	3057177836 ps
T49	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3703794558			Jan 21 04:25:30 PM PST 24	Jan 21 04:38:50 PM PST 24	4065964922 ps
T140	/workspace/coverage/default/0.chip_plic_all_irqs_10.1122073643			Jan 21 04:26:16 PM PST 24	Jan 21 04:36:47 PM PST 24	4189312608 ps
T277	/workspace/coverage/default/1.chip_sw_uart_rand_baudrate.2317929496			Jan 21 04:33:55 PM PST 24	Jan 21 05:32:10 PM PST 24	14942877200 ps
T269	/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.1336676932			Jan 21 04:48:07 PM PST 24	Jan 21 05:05:44 PM PST 24	4941346344 ps
T320	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.613540643			Jan 21 04:34:05 PM PST 24	Jan 21 05:15:32 PM PST 24	8642782280 ps
T110	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.270698601			Jan 21 05:17:22 PM PST 24	Jan 21 05:29:07 PM PST 24	6464968056 ps
T336	/workspace/coverage/default/0.rom_e2e_static_critical.2015446092			Jan 21 06:18:21 PM PST 24	Jan 21 07:13:45 PM PST 24	10716418020 ps
T337	/workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.4246326168			Jan 21 06:01:55 PM PST 24	Jan 21 06:23:00 PM PST 24	5769583978 ps
T338	/workspace/coverage/default/1.chip_sw_aes_smoketest.2458678543			Jan 21 04:45:44 PM PST 24	Jan 21 04:49:49 PM PST 24	2582047844 ps
T321	/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.3036832042			Jan 21 05:16:21 PM PST 24	Jan 21 05:29:20 PM PST 24	8029430360 ps
T339	/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.862775470			Jan 21 05:09:02 PM PST 24	Jan 21 05:16:02 PM PST 24	3771878948 ps
T343	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.3264306354			Jan 21 04:34:17 PM PST 24	Jan 21 05:41:09 PM PST 24	11992564800 ps
T263	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.2419964726			Jan 21 04:48:21 PM PST 24	Jan 21 05:03:39 PM PST 24	5085517051 ps
T189	/workspace/coverage/default/2.chip_sw_plic_sw_irq.3964206589			Jan 21 04:57:21 PM PST 24	Jan 21 05:02:32 PM PST 24	3368618620 ps
T62	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.1098631172			Jan 21 04:53:40 PM PST 24	Jan 21 05:20:41 PM PST 24	11962886040 ps
T708	/workspace/coverage/default/61.chip_sw_all_escalation_resets.1149872460			Jan 21 05:15:07 PM PST 24	Jan 21 05:28:45 PM PST 24	5570028000 ps
T259	/workspace/coverage/default/11.chip_sw_uart_rand_baudrate.2430795592			Jan 21 05:06:22 PM PST 24	Jan 21 05:55:32 PM PST 24	13368228820 ps
T355	/workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.2291188926			Jan 21 05:28:59 PM PST 24	Jan 21 06:02:57 PM PST 24	6977970262 ps
T714	/workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.1664945503			Jan 21 04:23:55 PM PST 24	Jan 21 04:34:33 PM PST 24	9739392526 ps
T938	/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.1328863004			Jan 21 04:58:00 PM PST 24	Jan 21 05:08:44 PM PST 24	7325114200 ps
T709	/workspace/coverage/default/8.chip_sw_all_escalation_resets.4265516499			Jan 21 05:39:21 PM PST 24	Jan 21 05:50:45 PM PST 24	5048987400 ps
T183	/workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.1860713913			Jan 21 04:37:14 PM PST 24	Jan 21 04:43:15 PM PST 24	4308377888 ps
T939	/workspace/coverage/default/0.chip_sw_kmac_app_rom.1027239752			Jan 21 04:23:32 PM PST 24	Jan 21 04:27:30 PM PST 24	2467759870 ps
T133	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.144153176			Jan 21 05:38:06 PM PST 24	Jan 21 06:06:36 PM PST 24	6313916820 ps
T940	/workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.4083915052			Jan 21 04:49:02 PM PST 24	Jan 21 05:05:16 PM PST 24	9649731610 ps
T799	/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.4106113177			Jan 21 06:32:57 PM PST 24	Jan 21 06:40:29 PM PST 24	3704253846 ps
T389	/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.1958545330			Jan 21 05:05:43 PM PST 24	Jan 21 05:14:05 PM PST 24	3626529062 ps
T710	/workspace/coverage/default/84.chip_sw_all_escalation_resets.2379609096			Jan 21 05:19:54 PM PST 24	Jan 21 05:33:19 PM PST 24	5883095792 ps
T38	/workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.2649575410			Jan 21 04:20:05 PM PST 24	Jan 21 04:36:45 PM PST 24	8356369880 ps
T111	/workspace/coverage/default/1.chip_sw_entropy_src_fuse_en_fw_read_test.1227527785			Jan 21 04:38:59 PM PST 24	Jan 21 04:47:56 PM PST 24	3702854864 ps
T941	/workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.1951778609			Jan 21 04:52:47 PM PST 24	Jan 21 05:01:17 PM PST 24	7733958512 ps
T197	/workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.273597498			Jan 21 05:57:47 PM PST 24	Jan 21 06:17:39 PM PST 24	5572773320 ps
T730	/workspace/coverage/default/46.chip_sw_all_escalation_resets.3088027057			Jan 21 05:55:59 PM PST 24	Jan 21 06:08:47 PM PST 24	5938265648 ps
T942	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.415573350			Jan 21 04:33:42 PM PST 24	Jan 21 05:02:58 PM PST 24	6986399840 ps
T943	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1722542185			Jan 21 05:11:36 PM PST 24	Jan 21 05:17:30 PM PST 24	3305788943 ps
T48	/workspace/coverage/default/3.chip_tap_straps_testunlock0.374156700			Jan 21 05:04:05 PM PST 24	Jan 21 05:12:59 PM PST 24	4685591433 ps
T108	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3902134325			Jan 21 04:26:54 PM PST 24	Jan 21 04:39:14 PM PST 24	4031524340 ps
T734	/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.2040313492			Jan 21 05:13:12 PM PST 24	Jan 21 05:20:58 PM PST 24	3246155322 ps
T39	/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.463931588			Jan 21 05:05:37 PM PST 24	Jan 21 05:16:25 PM PST 24	7178489414 ps
T944	/workspace/coverage/default/1.rom_e2e_asm_init_rma.3258436438			Jan 21 05:24:07 PM PST 24	Jan 21 06:03:00 PM PST 24	8474856060 ps
T271	/workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.1769091606			Jan 21 04:46:59 PM PST 24	Jan 21 04:58:02 PM PST 24	3779298728 ps
T945	/workspace/coverage/default/0.chip_sw_example_concurrency.2600905042			Jan 21 04:17:23 PM PST 24	Jan 21 04:22:09 PM PST 24	2915196568 ps
T129	/workspace/coverage/default/0.chip_sw_gpio_smoketest.1806037808			Jan 21 04:33:50 PM PST 24	Jan 21 04:37:51 PM PST 24	2893848565 ps
T400	/workspace/coverage/default/2.chip_sw_kmac_entropy.1164031948			Jan 21 04:48:09 PM PST 24	Jan 21 04:52:14 PM PST 24	3166099000 ps
T122	/workspace/coverage/default/2.chip_sw_sensor_ctrl_status.3563934463			Jan 21 04:57:09 PM PST 24	Jan 21 05:02:25 PM PST 24	3248587814 ps
T184	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.4140224786			Jan 21 04:34:47 PM PST 24	Jan 21 05:11:10 PM PST 24	8938856849 ps
T283	/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.3740950465			Jan 21 04:48:14 PM PST 24	Jan 21 05:08:39 PM PST 24	5525161972 ps
T278	/workspace/coverage/default/1.chip_sw_uart_tx_rx.2518263104			Jan 21 04:33:44 PM PST 24	Jan 21 04:49:05 PM PST 24	6008514040 ps
T946	/workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.3578794089			Jan 21 04:49:07 PM PST 24	Jan 21 05:11:29 PM PST 24	5736555009 ps
T150	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.2020652635			Jan 21 05:12:41 PM PST 24	Jan 21 05:46:28 PM PST 24	7600288800 ps
T134	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.1008593436			Jan 21 05:13:52 PM PST 24	Jan 21 05:53:57 PM PST 24	8020449120 ps
T759	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.744528942			Jan 21 04:20:36 PM PST 24	Jan 21 04:46:13 PM PST 24	22220918394 ps
T736	/workspace/coverage/default/51.chip_sw_all_escalation_resets.2973461811			Jan 21 05:13:41 PM PST 24	Jan 21 05:26:56 PM PST 24	4843493048 ps
T947	/workspace/coverage/default/0.rom_e2e_asm_init_rma.50361768			Jan 21 04:35:27 PM PST 24	Jan 21 05:14:40 PM PST 24	8576655703 ps
T299	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.2793898322			Jan 21 04:37:45 PM PST 24	Jan 21 04:42:25 PM PST 24	2978212746 ps
T198	/workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.116928098			Jan 21 04:38:16 PM PST 24	Jan 21 04:55:11 PM PST 24	5775434090 ps
T94	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2623003855			Jan 21 04:22:49 PM PST 24	Jan 21 04:33:14 PM PST 24	19819031384 ps
T948	/workspace/coverage/default/3.chip_sw_uart_tx_rx.364709445			Jan 21 05:30:57 PM PST 24	Jan 21 05:49:35 PM PST 24	4851482800 ps
T268	/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.1336527173			Jan 21 05:02:55 PM PST 24	Jan 21 05:57:26 PM PST 24	13545604272 ps
T260	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.12644134			Jan 21 05:19:09 PM PST 24	Jan 21 05:36:43 PM PST 24	5696599236 ps
T398	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.1647491327			Jan 21 04:43:35 PM PST 24	Jan 21 05:17:37 PM PST 24	7580227490 ps
T738	/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.1180636142			Jan 21 05:57:42 PM PST 24	Jan 21 06:04:44 PM PST 24	3366251722 ps
T298	/workspace/coverage/default/13.chip_sw_all_escalation_resets.1109218279			Jan 21 05:06:47 PM PST 24	Jan 21 05:19:01 PM PST 24	6225798060 ps
T949	/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1972528835			Jan 21 04:58:47 PM PST 24	Jan 21 05:21:16 PM PST 24	7688734681 ps
T167	/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.712810793			Jan 21 04:28:03 PM PST 24	Jan 21 05:06:31 PM PST 24	26649684870 ps
T346	/workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.1342719132			Jan 21 05:00:32 PM PST 24	Jan 21 05:03:28 PM PST 24	2460396808 ps
T157	/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.2831970654			Jan 21 05:19:23 PM PST 24	Jan 21 05:27:24 PM PST 24	3530869480 ps
T130	/workspace/coverage/default/2.chip_sw_gpio_smoketest.473140455			Jan 21 05:50:25 PM PST 24	Jan 21 05:54:40 PM PST 24	2494317407 ps
T950	/workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.278893836			Jan 21 05:32:38 PM PST 24	Jan 21 05:41:52 PM PST 24	3878272840 ps
T135	/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.849755786			Jan 21 04:18:24 PM PST 24	Jan 21 04:27:14 PM PST 24	3812826622 ps
T735	/workspace/coverage/default/63.chip_sw_all_escalation_resets.3256403249			Jan 21 05:15:43 PM PST 24	Jan 21 05:28:51 PM PST 24	5679454664 ps
T324	/workspace/coverage/default/73.chip_sw_all_escalation_resets.1025944156			Jan 21 05:16:55 PM PST 24	Jan 21 05:27:38 PM PST 24	4410949880 ps
T326	/workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.2534255592			Jan 21 04:24:38 PM PST 24	Jan 21 04:31:19 PM PST 24	3856347750 ps
T327	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.3387912851			Jan 21 05:43:52 PM PST 24	Jan 21 06:08:17 PM PST 24	7735647104 ps
T328	/workspace/coverage/default/1.rom_e2e_static_critical.3492651212			Jan 21 04:49:03 PM PST 24	Jan 21 05:39:19 PM PST 24	10834434476 ps
T270	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.1540619459			Jan 21 05:02:59 PM PST 24	Jan 21 05:19:11 PM PST 24	5674247920 ps
T329	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1358397103			Jan 21 07:55:53 PM PST 24	Jan 21 08:08:20 PM PST 24	5236065456 ps
T279	/workspace/coverage/default/2.chip_sw_uart_rand_baudrate.4291464856			Jan 21 04:46:51 PM PST 24	Jan 21 05:05:04 PM PST 24	5182924128 ps
T330	/workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.454237225			Jan 21 04:46:50 PM PST 24	Jan 21 04:58:13 PM PST 24	5458866060 ps
T107	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1589478178			Jan 21 04:28:02 PM PST 24	Jan 21 04:39:13 PM PST 24	5282743775 ps
T230	/workspace/coverage/default/3.chip_tap_straps_prod.3918218453			Jan 21 05:01:51 PM PST 24	Jan 21 05:04:56 PM PST 24	2819523030 ps
T231	/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.3521628188			Jan 21 05:07:38 PM PST 24	Jan 21 05:14:55 PM PST 24	3139847432 ps
T168	/workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.1309975824			Jan 21 04:48:45 PM PST 24	Jan 21 04:57:01 PM PST 24	4881434717 ps
T232	/workspace/coverage/default/0.chip_sw_aon_timer_irq.3731619448			Jan 21 04:20:41 PM PST 24	Jan 21 04:27:55 PM PST 24	4163322454 ps
T233	/workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.3616551091			Jan 21 05:03:54 PM PST 24	Jan 21 05:10:59 PM PST 24	4144824350 ps
T234	/workspace/coverage/default/1.rom_keymgr_functest.878699534			Jan 21 04:54:57 PM PST 24	Jan 21 05:07:33 PM PST 24	4843882404 ps
T235	/workspace/coverage/default/16.chip_sw_uart_rand_baudrate.3734360564			Jan 21 05:36:24 PM PST 24	Jan 21 06:31:09 PM PST 24	14339713450 ps
T194	/workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3355141041			Jan 21 07:45:05 PM PST 24	Jan 21 07:55:27 PM PST 24	4810244118 ps
T318	/workspace/coverage/default/32.chip_sw_all_escalation_resets.1379881759			Jan 21 05:11:28 PM PST 24	Jan 21 05:24:23 PM PST 24	5440765768 ps
T951	/workspace/coverage/default/0.chip_sw_example_flash.2770076050			Jan 21 04:17:14 PM PST 24	Jan 21 04:21:20 PM PST 24	2263904104 ps
T952	/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.1117414320			Jan 21 05:24:37 PM PST 24	Jan 21 05:40:26 PM PST 24	5450260418 ps
T40	/workspace/coverage/default/10.chip_sw_lc_ctrl_transition.286154564			Jan 21 05:05:20 PM PST 24	Jan 21 05:15:58 PM PST 24	6255943970 ps
T953	/workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.3689134592			Jan 21 04:41:34 PM PST 24	Jan 21 04:50:25 PM PST 24	4786325044 ps
T25	/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.665845105			Jan 21 04:36:23 PM PST 24	Jan 21 04:41:18 PM PST 24	4542839344 ps
T954	/workspace/coverage/default/1.chip_sw_example_manufacturer.1280190743			Jan 21 05:07:17 PM PST 24	Jan 21 05:12:41 PM PST 24	2537015792 ps
T302	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.2133593085			Jan 21 04:21:38 PM PST 24	Jan 21 05:28:45 PM PST 24	17322721044 ps
T739	/workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.4238755364			Jan 21 04:27:04 PM PST 24	Jan 21 04:33:36 PM PST 24	2770044550 ps
T390	/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.2257488797			Jan 21 07:32:23 PM PST 24	Jan 21 07:40:03 PM PST 24	4006826412 ps
T955	/workspace/coverage/default/0.chip_sw_aes_enc.3466791131			Jan 21 06:47:13 PM PST 24	Jan 21 06:52:48 PM PST 24	2719111964 ps
T112	/workspace/coverage/default/1.chip_sw_edn_auto_mode.1472479396			Jan 21 04:40:25 PM PST 24	Jan 21 04:57:02 PM PST 24	4653763930 ps
T715	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.3600158510			Jan 21 04:35:07 PM PST 24	Jan 21 05:16:28 PM PST 24	8574392168 ps
T169	/workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.441651992			Jan 21 04:49:02 PM PST 24	Jan 21 06:49:28 PM PST 24	50107696176 ps
T956	/workspace/coverage/default/2.chip_sw_uart_tx_rx.2431607597			Jan 21 05:10:03 PM PST 24	Jan 21 05:28:32 PM PST 24	5561247244 ps
T166	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.2757017810			Jan 21 04:24:58 PM PST 24	Jan 21 04:45:09 PM PST 24	13949920579 ps
T716	/workspace/coverage/default/0.chip_sw_inject_scramble_seed.2741712574			Jan 21 04:18:20 PM PST 24	Jan 21 09:03:12 PM PST 24	67206669760 ps
T178	/workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.3864681275			Jan 21 07:07:02 PM PST 24	Jan 21 07:18:32 PM PST 24	5998219189 ps
T731	/workspace/coverage/default/57.chip_sw_all_escalation_resets.3536974206			Jan 21 05:13:53 PM PST 24	Jan 21 05:28:04 PM PST 24	5885914612 ps
T261	/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.1168311806			Jan 21 05:14:45 PM PST 24	Jan 21 06:10:33 PM PST 24	12792861202 ps
T957	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.178249537			Jan 21 04:18:02 PM PST 24	Jan 21 04:34:58 PM PST 24	5444046912 ps
T958	/workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.2600747277			Jan 21 04:43:28 PM PST 24	Jan 21 04:54:17 PM PST 24	5064149774 ps
T733	/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.1286199615			Jan 21 06:32:20 PM PST 24	Jan 21 06:38:57 PM PST 24	3163499812 ps
T795	/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.1757962834			Jan 21 05:17:39 PM PST 24	Jan 21 05:23:35 PM PST 24	3162625844 ps
T959	/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.4081870348			Jan 21 05:15:28 PM PST 24	Jan 21 05:20:00 PM PST 24	2440939850 ps
T760	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.25060461			Jan 21 04:50:17 PM PST 24	Jan 21 05:39:39 PM PST 24	25096197532 ps
T307	/workspace/coverage/default/62.chip_sw_all_escalation_resets.3531834115			Jan 21 05:15:11 PM PST 24	Jan 21 05:24:53 PM PST 24	4191110004 ps
T960	/workspace/coverage/default/1.chip_sw_otbn_randomness.3759733192			Jan 21 04:37:55 PM PST 24	Jan 21 04:49:03 PM PST 24	6207967460 ps
T289	/workspace/coverage/default/0.chip_sw_hmac_enc.1894620732			Jan 21 04:23:28 PM PST 24	Jan 21 04:27:42 PM PST 24	2479531354 ps
T961	/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3550027598			Jan 21 04:18:48 PM PST 24	Jan 21 04:29:43 PM PST 24	4864066675 ps
T63	/workspace/coverage/default/0.chip_sw_alert_handler_entropy.3918121306			Jan 21 04:23:48 PM PST 24	Jan 21 04:29:10 PM PST 24	2627318402 ps
T195	/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3163644605			Jan 21 04:27:24 PM PST 24	Jan 21 04:39:25 PM PST 24	4876843320 ps
T396	/workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.3232361392			Jan 21 04:19:08 PM PST 24	Jan 21 04:27:42 PM PST 24	5514593296 ps
T962	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.969017228			Jan 21 04:57:14 PM PST 24	Jan 21 05:08:36 PM PST 24	5129407530 ps
T963	/workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.1444091531			Jan 21 05:38:31 PM PST 24	Jan 21 05:43:43 PM PST 24	2645089656 ps
T264	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops.3008755062			Jan 21 04:35:48 PM PST 24	Jan 21 04:55:43 PM PST 24	4758749018 ps
T397	/workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.1274548043			Jan 21 04:46:40 PM PST 24	Jan 21 04:56:49 PM PST 24	5608202290 ps
T964	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.420860454			Jan 21 04:53:19 PM PST 24	Jan 21 05:05:36 PM PST 24	4098297668 ps
T176	/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.1638797965			Jan 21 05:05:16 PM PST 24	Jan 21 05:15:18 PM PST 24	6087661589 ps
T45	/workspace/coverage/default/2.chip_tap_straps_testunlock0.4101883505			Jan 21 06:05:20 PM PST 24	Jan 21 06:08:38 PM PST 24	2584815961 ps
T403	/workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.1359261449			Jan 21 04:23:21 PM PST 24	Jan 21 04:29:24 PM PST 24	3956082160 ps
T741	/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.1149205196			Jan 21 05:09:24 PM PST 24	Jan 21 05:16:15 PM PST 24	3635524120 ps
T965	/workspace/coverage/default/2.chip_sw_example_flash.2014111776			Jan 21 04:47:14 PM PST 24	Jan 21 04:50:31 PM PST 24	2182191000 ps
T966	/workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.1303708079			Jan 21 04:57:58 PM PST 24	Jan 21 05:06:53 PM PST 24	4962711344 ps
T967	/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.602901595			Jan 21 05:54:22 PM PST 24	Jan 21 06:02:42 PM PST 24	4109600002 ps
T772	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.3233375532			Jan 21 05:28:05 PM PST 24	Jan 21 06:40:01 PM PST 24	21019004578 ps
T968	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.1023484607			Jan 21 04:34:02 PM PST 24	Jan 21 05:15:17 PM PST 24	9012385300 ps
T791	/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.2933854389			Jan 21 05:42:09 PM PST 24	Jan 21 05:48:52 PM PST 24	3629430272 ps
T969	/workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.2868544902			Jan 21 04:38:39 PM PST 24	Jan 21 04:54:29 PM PST 24	8513968864 ps
T191	/workspace/coverage/default/2.chip_sw_rv_timer_smoketest.3280588503			Jan 21 05:42:56 PM PST 24	Jan 21 05:47:08 PM PST 24	2431082740 ps
T834	/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.3564272589			Jan 21 05:19:03 PM PST 24	Jan 21 05:27:13 PM PST 24	3820978084 ps
T304	/workspace/coverage/default/89.chip_sw_all_escalation_resets.227556252			Jan 21 05:19:30 PM PST 24	Jan 21 05:32:12 PM PST 24	6593516756 ps
T154	/workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.2439155615			Jan 21 04:26:41 PM PST 24	Jan 21 04:36:49 PM PST 24	5155772136 ps
T970	/workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.2660760771			Jan 21 04:33:10 PM PST 24	Jan 21 04:38:54 PM PST 24	5425432300 ps
T971	/workspace/coverage/default/0.rom_e2e_asm_init_dev.3639672704			Jan 21 04:35:25 PM PST 24	Jan 21 05:14:03 PM PST 24	8493553477 ps
T972	/workspace/coverage/default/0.chip_sw_uart_smoketest_signed.1237032651			Jan 21 05:02:13 PM PST 24	Jan 21 05:41:46 PM PST 24	8600021668 ps
T973	/workspace/coverage/default/0.chip_tap_straps_prod.1454052303			Jan 21 05:05:24 PM PST 24	Jan 21 05:44:56 PM PST 24	16419868504 ps
T792	/workspace/coverage/default/11.chip_sw_all_escalation_resets.3780396567			Jan 21 05:31:28 PM PST 24	Jan 21 05:42:35 PM PST 24	5011050998 ps
T121	/workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3971792409			Jan 21 05:39:00 PM PST 24	Jan 21 05:49:14 PM PST 24	5831386846 ps
T974	/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.1672802921			Jan 21 05:04:28 PM PST 24	Jan 21 05:13:36 PM PST 24	5374285222 ps
T975	/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.124361301			Jan 21 05:59:54 PM PST 24	Jan 21 06:50:33 PM PST 24	13481553868 ps
T151	/workspace/coverage/default/2.chip_plic_all_irqs_20.2364565673			Jan 21 04:57:35 PM PST 24	Jan 21 05:13:56 PM PST 24	4459433016 ps
T222	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1103688789			Jan 21 04:43:35 PM PST 24	Jan 21 04:53:51 PM PST 24	5524947801 ps
T976	/workspace/coverage/default/1.chip_sw_clkmgr_jitter.3516645481			Jan 21 05:46:14 PM PST 24	Jan 21 05:50:45 PM PST 24	2634620909 ps
T977	/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.957808034			Jan 21 07:37:51 PM PST 24	Jan 21 07:56:16 PM PST 24	7396880652 ps