Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.spi_device_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	145966	1			T29	44		T30	77		T31	6
values[2]	10930	1			T30	1		T313	1		T114	10
values[3]	4355	1			T114	4		T410	27		T418	12
values[4]	2549	1			T114	5		T410	28		T418	15
values[5]	1569	1			T114	5		T410	21		T418	11
values[6]	1074	1			T114	8		T410	25		T418	14
values[7]	738	1			T114	10		T410	22		T418	11
values[8]	682	1			T114	13		T410	20		T418	22
values[9]	594	1			T114	11		T410	20		T418	11
values[10]	521	1			T114	12		T410	13		T418	18
values[11]	482	1			T114	8		T410	9		T418	21
values[12]	372	1			T114	8		T410	19		T418	18
values[13]	375	1			T114	5		T410	4		T418	9
values[14]	336	1			T114	4		T410	6		T418	9
values[15]	325	1			T114	5		T410	7		T418	19
values[16]	325	1			T114	5		T410	7		T418	10
values[17]	322	1			T114	14		T410	7		T418	19
values[18]	334	1			T114	9		T410	5		T418	10
values[19]	356	1			T114	7		T410	11		T418	11
values[20]	341	1			T114	9		T410	17		T418	43
values[21]	302	1			T114	6		T410	6		T418	7
values[22]	338	1			T114	7		T410	8		T418	7
values[23]	323	1			T114	8		T410	4		T418	7
values[24]	317	1			T114	4		T410	6		T418	20
values[25]	371	1			T114	7		T410	28		T418	30
values[26]	364	1			T114	16		T410	4		T418	11
values[27]	317	1			T114	13		T410	5		T418	7
values[28]	338	1			T114	14		T410	6		T418	12
values[29]	299	1			T114	4		T410	6		T418	9
values[30]	323	1			T114	6		T410	4		T418	15
values[31]	298	1			T114	6		T410	14		T418	9
values[32]	311	1			T114	6		T410	6		T418	25
values[33]	301	1			T114	8		T410	5		T418	26
values[34]	311	1			T114	8		T410	4		T418	15
values[35]	273	1			T114	9		T410	7		T418	13
values[36]	309	1			T114	12		T410	6		T418	13
values[37]	295	1			T114	6		T410	7		T418	9
values[38]	299	1			T114	4		T410	4		T418	15
values[39]	318	1			T114	3		T410	5		T418	11
values[40]	280	1			T114	3		T410	7		T418	17
values[41]	286	1			T114	8		T410	4		T418	16
values[42]	269	1			T114	5		T410	10		T418	18
values[43]	292	1			T114	13		T410	6		T418	32
values[44]	292	1			T114	10		T410	8		T418	16
values[45]	247	1			T114	5		T410	8		T418	13
values[46]	288	1			T114	9		T410	25		T418	24
values[47]	263	1			T114	15		T410	18		T418	15
values[48]	233	1			T114	11		T410	3		T418	10
values[49]	239	1			T114	9		T418	9		T379	20
values[50]	221	1			T114	3		T418	13		T379	4
values[51]	249	1			T114	16		T418	9		T379	3
values[52]	220	1			T114	9		T418	14		T379	4
values[53]	232	1			T114	7		T418	15		T379	6
values[54]	263	1			T114	8		T418	23		T379	12
values[55]	257	1			T114	4		T418	15		T379	12
values[56]	242	1			T114	4		T418	33		T379	4
values[57]	226	1			T114	7		T418	9		T379	8
values[58]	219	1			T114	4		T418	10		T379	11
values[59]	201	1			T114	8		T418	20		T379	9
values[60]	201	1			T114	3		T418	8		T379	6
values[61]	191	1			T114	5		T418	3		T379	5
values[62]	181	1			T114	7		T418	4		T379	4
values[63]	159	1			T114	5		T418	8		T379	9
values[64]	168	1			T114	7		T418	7		T379	4
values[65]	134	1			T114	5		T418	9		T379	6
values[66]	109	1			T114	1		T418	10		T379	3
values[67]	125	1			T418	7		T379	7		T449	2
values[68]	112	1			T418	5		T449	1		T889	4
values[69]	107	1			T418	3		T449	2		T889	6
values[70]	75	1			T449	1		T889	5		T890	1
values[71]	101	1			T449	3		T889	8		T890	1
values[72]	101	1			T449	5		T889	6		T890	1
values[73]	100	1			T449	5		T889	9		T890	1
values[74]	88	1			T449	9		T890	1		T896	1
values[75]	110	1			T449	12		T890	1		T896	1
values[76]	120	1			T449	16		T890	1		T896	1
values[77]	111	1			T449	6		T890	1		T896	1
values[78]	82	1			T890	1		T896	1		T535	1
values[79]	78	1			T890	1		T896	1		T535	1
values[80]	65	1			T890	1		T896	1		T535	1
values[81]	69	1			T890	1		T896	1		T535	1
values[82]	75	1			T890	1		T896	1		T535	1
values[83]	97	1			T890	1		T896	1		T535	1
values[84]	74	1			T890	1		T896	1		T535	1
values[85]	92	1			T890	1		T896	1		T535	1
values[86]	82	1			T890	1		T896	1		T535	2
values[87]	74	1			T890	1		T896	1		T535	1
values[88]	87	1			T890	1		T896	1		T535	1
values[89]	86	1			T890	1		T896	1		T535	1
values[90]	91	1			T890	1		T896	1		T535	1
values[91]	83	1			T890	1		T896	1		T535	1
values[92]	91	1			T890	1		T896	1		T535	1
values[93]	66	1			T890	1		T896	1		T535	1
values[94]	88	1			T890	1		T896	1		T535	1
values[95]	80	1			T890	1		T896	1		T535	1
values[96]	82	1			T890	1		T896	1		T535	1
values[97]	77	1			T890	1		T896	1		T535	1
values[98]	76	1			T890	1		T896	1		T535	1
values[99]	69	1			T890	1		T896	2		T535	1
values[100]	74	1			T890	1		T896	1		T535	1
values[101]	82	1			T890	1		T896	2		T535	1
values[102]	90	1			T890	1		T896	1		T535	1
values[103]	98	1			T890	1		T896	2		T535	1
values[104]	85	1			T890	1		T896	3		T535	1
values[105]	84	1			T890	1		T896	1		T535	1
values[106]	72	1			T890	1		T896	3		T535	1
values[107]	80	1			T890	1		T896	3		T535	1
values[108]	89	1			T890	1		T896	1		T535	3
values[109]	81	1			T890	1		T896	5		T535	2
values[110]	88	1			T890	1		T896	2		T535	1
values[111]	83	1			T890	1		T896	2		T535	2
values[112]	93	1			T890	1		T896	1		T535	1
values[113]	80	1			T890	1		T896	3		T535	2
values[114]	73	1			T890	1		T896	1		T535	1
values[115]	71	1			T890	1		T896	1		T535	1
values[116]	72	1			T890	1		T896	1		T535	2
values[117]	80	1			T890	2		T896	4		T535	4
values[118]	74	1			T890	1		T896	1		T535	2
values[119]	72	1			T890	1		T896	2		T535	1
values[120]	87	1			T890	1		T896	1		T535	1
values[121]	73	1			T890	1		T896	8		T535	4
values[122]	72	1			T890	1		T896	1		T535	1
values[123]	79	1			T890	1		T896	1		T535	5
values[124]	89	1			T890	1		T896	3		T535	1
values[125]	82	1			T890	4		T896	1		T535	2
values[126]	146	1			T890	2		T896	2		T535	1
values[127]	952	1			T890	31		T896	34		T535	22
values[128]	7656	1			T890	293		T896	304		T535	294