Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.spi_host0_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	154470	1			T29	59		T30	96		T31	4
values[2]	14759	1			T30	4		T313	1		T114	10
values[3]	7416	1			T30	1		T418	218		T420	34
values[4]	3687	1			T418	43		T722	17		T430	13
values[5]	1499	1			T722	18		T505	45		T600	15
values[6]	913	1			T722	14		T505	29		T600	19
values[7]	575	1			T722	20		T505	26		T600	7
values[8]	428	1			T722	5		T505	50		T600	3
values[9]	313	1			T722	3		T505	31		T600	9
values[10]	290	1			T722	3		T505	27		T600	4
values[11]	263	1			T722	4		T505	36		T600	3
values[12]	181	1			T722	10		T505	11		T600	1
values[13]	122	1			T722	3		T505	6		T600	6
values[14]	74	1			T505	2		T600	6		T901	7
values[15]	80	1			T505	4		T600	3		T901	27
values[16]	92	1			T505	4		T600	11		T901	25
values[17]	138	1			T505	4		T600	8		T901	38
values[18]	137	1			T505	7		T600	8		T901	33
values[19]	105	1			T505	14		T600	7		T901	10
values[20]	81	1			T505	12		T600	10		T901	3
values[21]	67	1			T505	3		T600	10		T902	1
values[22]	66	1			T505	5		T600	19		T902	1
values[23]	45	1			T505	2		T600	6		T902	1
values[24]	47	1			T505	2		T600	11		T902	1
values[25]	43	1			T505	4		T600	9		T902	1
values[26]	51	1			T505	4		T600	12		T902	1
values[27]	69	1			T505	4		T600	12		T902	1
values[28]	34	1			T505	2		T600	6		T902	1
values[29]	48	1			T505	8		T600	5		T902	1
values[30]	65	1			T505	29		T600	6		T902	1
values[31]	65	1			T505	36		T600	3		T902	1
values[32]	63	1			T505	9		T600	17		T902	1
values[33]	55	1			T505	3		T600	10		T902	1
values[34]	49	1			T505	6		T600	9		T902	1
values[35]	49	1			T505	7		T600	5		T902	1
values[36]	31	1			T505	5		T600	2		T902	1
values[37]	48	1			T505	9		T600	7		T902	1
values[38]	35	1			T505	3		T600	3		T902	1
values[39]	28	1			T505	1		T600	2		T902	1
values[40]	37	1			T505	8		T600	2		T902	1
values[41]	41	1			T505	10		T600	6		T902	1
values[42]	48	1			T505	7		T600	5		T902	1
values[43]	44	1			T505	5		T600	4		T902	1
values[44]	41	1			T505	8		T600	3		T902	1
values[45]	40	1			T505	6		T600	1		T902	1
values[46]	45	1			T505	8		T600	4		T902	1
values[47]	44	1			T505	3		T600	1		T902	1
values[48]	48	1			T505	1		T600	3		T902	1
values[49]	42	1			T505	3		T600	3		T902	1
values[50]	51	1			T505	12		T600	2		T902	1
values[51]	65	1			T505	19		T600	5		T902	2
values[52]	103	1			T505	36		T600	2		T902	1
values[53]	110	1			T505	35		T600	5		T902	1
values[54]	92	1			T505	21		T600	7		T902	1
values[55]	55	1			T505	2		T600	3		T902	1
values[56]	44	1			T600	5		T902	1		T480	1
values[57]	38	1			T600	7		T902	1		T480	1
values[58]	28	1			T600	2		T902	1		T480	1
values[59]	36	1			T600	11		T902	1		T480	1
values[60]	56	1			T600	32		T902	1		T480	1
values[61]	37	1			T600	16		T902	1		T480	1
values[62]	26	1			T600	8		T902	1		T480	1
values[63]	25	1			T600	7		T902	1		T480	1
values[64]	30	1			T600	11		T902	1		T480	1
values[65]	26	1			T600	7		T902	1		T480	1
values[66]	49	1			T600	31		T902	1		T480	1
values[67]	45	1			T600	26		T902	2		T480	1
values[68]	22	1			T600	4		T902	1		T480	1
values[69]	21	1			T600	3		T902	1		T480	1
values[70]	21	1			T600	2		T902	1		T480	1
values[71]	18	1			T902	1		T480	1		T903	1
values[72]	18	1			T902	1		T480	1		T903	1
values[73]	18	1			T902	1		T480	1		T903	1
values[74]	20	1			T902	1		T480	1		T903	1
values[75]	18	1			T902	1		T480	1		T903	1
values[76]	18	1			T902	1		T480	1		T903	1
values[77]	18	1			T902	1		T480	1		T903	1
values[78]	18	1			T902	1		T480	1		T903	1
values[79]	18	1			T902	1		T480	1		T903	1
values[80]	18	1			T902	1		T480	1		T903	1
values[81]	18	1			T902	1		T480	1		T903	1
values[82]	20	1			T902	1		T480	1		T903	1
values[83]	23	1			T902	1		T480	1		T903	1
values[84]	22	1			T902	1		T480	1		T903	1
values[85]	19	1			T902	1		T480	1		T903	1
values[86]	19	1			T902	1		T480	1		T903	1
values[87]	19	1			T902	1		T480	1		T903	1
values[88]	22	1			T902	1		T480	1		T903	1
values[89]	22	1			T902	1		T480	1		T903	1
values[90]	23	1			T902	1		T480	1		T903	1
values[91]	29	1			T902	1		T480	1		T903	2
values[92]	26	1			T902	1		T480	1		T903	1
values[93]	30	1			T902	1		T480	1		T903	1
values[94]	30	1			T902	1		T480	3		T903	1
values[95]	37	1			T902	1		T480	3		T903	1
values[96]	33	1			T902	1		T480	2		T903	3
values[97]	32	1			T902	1		T480	1		T903	3
values[98]	29	1			T902	1		T480	3		T903	1
values[99]	29	1			T902	1		T480	3		T903	1
values[100]	38	1			T902	1		T480	2		T903	2
values[101]	36	1			T902	1		T480	1		T903	3
values[102]	37	1			T902	1		T480	1		T903	5
values[103]	27	1			T902	1		T480	2		T903	2
values[104]	25	1			T902	2		T480	2		T903	1
values[105]	30	1			T902	2		T480	1		T903	3
values[106]	29	1			T902	3		T480	1		T903	3
values[107]	37	1			T902	4		T480	1		T903	1
values[108]	38	1			T902	4		T480	3		T903	1
values[109]	34	1			T902	3		T480	4		T903	3
values[110]	29	1			T902	4		T480	1		T903	3
values[111]	30	1			T902	2		T480	1		T903	1
values[112]	39	1			T902	3		T480	3		T903	3
values[113]	30	1			T902	4		T480	1		T903	3
values[114]	35	1			T902	5		T480	2		T903	1
values[115]	41	1			T902	3		T480	4		T903	4
values[116]	35	1			T902	2		T480	2		T903	2
values[117]	39	1			T902	1		T480	1		T903	3
values[118]	33	1			T902	1		T480	3		T903	2
values[119]	41	1			T902	2		T480	2		T903	1
values[120]	40	1			T902	2		T480	3		T903	1
values[121]	39	1			T902	2		T480	1		T903	2
values[122]	36	1			T902	1		T480	3		T903	5
values[123]	33	1			T902	2		T480	2		T903	2
values[124]	37	1			T902	4		T480	2		T903	1
values[125]	42	1			T902	1		T480	2		T903	1
values[126]	223	1			T902	11		T480	17		T903	11
values[127]	1873	1			T902	105		T480	119		T903	89
values[128]	3776	1			T902	185		T480	198		T903	233