Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.flash_ctrl__core_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	159775	1			T29	53		T30	87		T31	8
values[2]	4658	1			T30	1		T60	1		T313	4
values[3]	2211	1			T421	1		T722	17		T528	1
values[4]	1579	1			T722	31		T452	76		T871	1
values[5]	1089	1			T722	19		T452	54		T871	1
values[6]	893	1			T722	5		T452	41		T871	1
values[7]	767	1			T722	2		T452	31		T871	1
values[8]	550	1			T722	10		T452	17		T871	1
values[9]	556	1			T722	14		T452	11		T871	1
values[10]	533	1			T722	24		T452	6		T871	1
values[11]	591	1			T722	29		T452	19		T871	1
values[12]	631	1			T722	12		T452	23		T871	1
values[13]	541	1			T722	12		T452	14		T871	1
values[14]	444	1			T722	6		T452	2		T871	1
values[15]	362	1			T722	3		T871	1		T459	5
values[16]	327	1			T722	11		T871	1		T459	15
values[17]	373	1			T722	14		T871	1		T459	24
values[18]	393	1			T722	22		T871	1		T459	17
values[19]	385	1			T722	19		T871	1		T459	21
values[20]	367	1			T722	20		T871	1		T459	25
values[21]	423	1			T722	14		T871	1		T459	21
values[22]	387	1			T722	10		T871	1		T459	13
values[23]	320	1			T722	10		T871	1		T459	17
values[24]	278	1			T722	9		T871	1		T459	5
values[25]	311	1			T722	27		T871	1		T459	5
values[26]	299	1			T722	33		T871	1		T459	3
values[27]	248	1			T722	36		T871	1		T884	20
values[28]	169	1			T722	26		T871	1		T884	15
values[29]	150	1			T722	26		T871	1		T884	12
values[30]	152	1			T722	16		T871	1		T884	15
values[31]	116	1			T722	8		T871	1		T884	18
values[32]	101	1			T722	1		T871	1		T884	17
values[33]	115	1			T871	1		T884	32		T880	1
values[34]	95	1			T871	1		T884	18		T880	1
values[35]	84	1			T871	1		T884	6		T880	1
values[36]	70	1			T871	1		T884	1		T880	1
values[37]	55	1			T871	1		T880	1		T467	1
values[38]	51	1			T871	1		T880	1		T467	1
values[39]	49	1			T871	1		T880	1		T467	1
values[40]	55	1			T871	1		T880	1		T467	1
values[41]	64	1			T871	1		T880	1		T467	1
values[42]	35	1			T871	1		T880	1		T467	1
values[43]	40	1			T871	1		T880	1		T467	1
values[44]	36	1			T871	1		T880	1		T467	1
values[45]	35	1			T871	1		T880	1		T467	1
values[46]	51	1			T871	1		T880	1		T467	1
values[47]	50	1			T871	1		T880	1		T467	1
values[48]	39	1			T871	1		T880	1		T467	1
values[49]	41	1			T871	1		T880	1		T467	1
values[50]	41	1			T871	1		T880	1		T467	1
values[51]	48	1			T871	1		T880	1		T467	1
values[52]	34	1			T871	1		T880	1		T467	1
values[53]	42	1			T871	1		T880	1		T467	1
values[54]	46	1			T871	1		T880	1		T467	1
values[55]	42	1			T871	1		T880	1		T467	1
values[56]	35	1			T871	1		T880	1		T467	1
values[57]	38	1			T871	1		T880	1		T467	1
values[58]	40	1			T871	1		T880	1		T467	1
values[59]	50	1			T871	1		T880	1		T467	1
values[60]	43	1			T871	1		T880	1		T467	1
values[61]	56	1			T871	1		T880	1		T467	1
values[62]	37	1			T871	1		T880	1		T467	1
values[63]	41	1			T871	1		T880	1		T467	1
values[64]	43	1			T871	1		T880	1		T467	2
values[65]	37	1			T871	1		T880	1		T467	1
values[66]	32	1			T871	1		T880	1		T467	1
values[67]	33	1			T871	1		T880	1		T467	1
values[68]	45	1			T871	1		T880	1		T467	1
values[69]	48	1			T871	1		T880	1		T467	1
values[70]	47	1			T871	2		T880	1		T467	1
values[71]	49	1			T871	1		T880	1		T467	1
values[72]	33	1			T871	1		T880	1		T467	1
values[73]	43	1			T871	1		T880	1		T467	1
values[74]	40	1			T871	1		T880	1		T467	1
values[75]	38	1			T871	1		T880	1		T467	1
values[76]	38	1			T871	1		T880	1		T467	1
values[77]	42	1			T871	1		T880	1		T467	1
values[78]	52	1			T871	1		T880	1		T467	1
values[79]	37	1			T871	1		T880	1		T467	1
values[80]	43	1			T871	1		T880	1		T467	1
values[81]	46	1			T871	1		T880	1		T467	1
values[82]	63	1			T871	1		T880	1		T467	1
values[83]	68	1			T871	1		T880	1		T467	1
values[84]	52	1			T871	1		T880	1		T467	1
values[85]	66	1			T871	1		T880	1		T467	1
values[86]	61	1			T871	1		T880	1		T467	1
values[87]	65	1			T871	1		T880	1		T467	1
values[88]	68	1			T871	1		T880	1		T467	1
values[89]	64	1			T871	1		T880	1		T467	1
values[90]	66	1			T871	1		T880	1		T467	1
values[91]	74	1			T871	4		T880	1		T467	1
values[92]	56	1			T871	2		T880	1		T467	1
values[93]	56	1			T871	4		T880	1		T467	1
values[94]	57	1			T871	3		T880	1		T467	1
values[95]	57	1			T871	2		T880	1		T467	1
values[96]	52	1			T871	1		T880	1		T467	1
values[97]	70	1			T871	1		T880	1		T467	2
values[98]	62	1			T871	1		T880	1		T467	3
values[99]	76	1			T871	2		T880	1		T467	2
values[100]	85	1			T871	2		T880	1		T467	2
values[101]	49	1			T871	3		T880	1		T467	1
values[102]	61	1			T871	2		T880	1		T467	1
values[103]	70	1			T871	2		T880	1		T467	1
values[104]	79	1			T871	3		T880	1		T467	1
values[105]	60	1			T871	1		T880	1		T467	5
values[106]	54	1			T871	4		T880	1		T467	3
values[107]	69	1			T871	6		T880	1		T467	2
values[108]	73	1			T871	6		T880	1		T467	2
values[109]	66	1			T871	3		T880	1		T467	2
values[110]	56	1			T871	3		T880	1		T467	1
values[111]	64	1			T871	4		T880	1		T467	1
values[112]	73	1			T871	1		T880	1		T467	5
values[113]	75	1			T871	1		T880	1		T467	2
values[114]	58	1			T871	1		T880	1		T467	2
values[115]	59	1			T871	3		T880	1		T467	2
values[116]	62	1			T871	1		T880	1		T467	2
values[117]	75	1			T871	1		T880	1		T467	1
values[118]	66	1			T871	2		T880	1		T467	2
values[119]	58	1			T871	1		T880	1		T467	2
values[120]	74	1			T871	3		T880	1		T467	1
values[121]	83	1			T871	3		T880	1		T467	4
values[122]	81	1			T871	2		T880	2		T467	4
values[123]	96	1			T871	1		T880	2		T467	2
values[124]	181	1			T871	3		T880	2		T467	2
values[125]	385	1			T871	1		T880	1		T467	2
values[126]	658	1			T871	27		T880	14		T467	9
values[127]	1455	1			T871	115		T880	136		T467	99
values[128]	2300	1			T871	146		T880	263		T467	249