Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	492	1			T114	2		T132	1		T356	1
all_values[1]	458	1			T114	4		T132	1		T419	2
all_values[2]	458	1			T114	4		T132	2		T414	2
all_values[3]	487	1			T114	1		T115	1		T414	1
all_values[4]	501	1			T114	3		T132	2		T414	2
all_values[5]	536	1			T114	1		T414	1		T419	3
all_values[6]	453	1			T114	2		T132	2		T419	3
all_values[7]	445	1			T114	1		T132	1		T419	1
all_values[8]	491	1			T114	6		T132	1		T419	3
all_values[9]	514	1			T114	5		T132	3		T356	2
all_values[10]	486	1			T114	2		T132	4		T414	1
all_values[11]	526	1			T114	6		T132	1		T356	1
all_values[12]	470	1			T114	4		T414	1		T419	2
all_values[13]	512	1			T114	5		T132	1		T115	1
all_values[14]	464	1			T114	3		T132	1		T414	1
all_values[15]	487	1			T114	2		T132	1		T419	3
all_values[16]	510	1			T114	1		T132	2		T419	5
all_values[17]	473	1			T114	4		T132	1		T414	1
all_values[18]	502	1			T114	4		T132	3		T414	1
all_values[19]	449	1			T114	3		T132	2		T115	1
all_values[20]	491	1			T114	1		T132	3		T356	1
all_values[21]	465	1			T114	2		T356	1		T414	1
all_values[22]	508	1			T114	3		T132	2		T115	1
all_values[23]	476	1			T114	2		T414	2		T419	1
all_values[24]	472	1			T114	2		T132	3		T414	1
all_values[25]	447	1			T114	3		T414	2		T419	2
all_values[26]	463	1			T114	3		T132	1		T115	1
all_values[27]	467	1			T114	3		T132	1		T419	2
all_values[28]	486	1			T114	2		T132	1		T414	2
all_values[29]	493	1			T114	2		T132	1		T115	1
all_values[30]	474	1			T114	8		T132	3		T356	1
all_values[31]	490	1			T114	3		T132	2		T356	1
all_values[32]	472	1			T114	4		T132	2		T419	4
all_values[33]	491	1			T114	3		T414	1		T419	5
all_values[34]	479	1			T114	1		T132	1		T356	1
all_values[35]	506	1			T114	5		T132	2		T414	1
all_values[36]	501	1			T114	3		T132	2		T414	2
all_values[37]	473	1			T114	6		T132	1		T414	1
all_values[38]	475	1			T114	1		T132	2		T356	1
all_values[39]	547	1			T114	3		T419	4		T411	4
all_values[40]	474	1			T114	2		T132	2		T356	2
all_values[41]	463	1			T114	7		T132	3		T356	1
all_values[42]	523	1			T114	4		T132	2		T419	2
all_values[43]	478	1			T114	3		T419	2		T411	1
all_values[44]	525	1			T114	5		T132	2		T356	1
all_values[45]	498	1			T114	4		T414	1		T419	1
all_values[46]	484	1			T114	5		T132	1		T414	1
all_values[47]	487	1			T114	3		T132	3		T414	2
all_values[48]	481	1			T114	3		T132	1		T414	2
all_values[49]	497	1			T114	3		T414	1		T419	4