Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3482	1			T114	21		T132	20		T115	5
all_values[1]	3558	1			T114	21		T132	16		T115	2
all_values[2]	3428	1			T114	21		T132	14		T115	6
all_values[3]	3555	1			T114	19		T132	15		T115	1
all_values[4]	3460	1			T114	16		T132	24		T115	5
all_values[5]	3554	1			T114	24		T132	13		T115	6
all_values[6]	3408	1			T114	20		T132	17		T115	4
all_values[7]	3518	1			T114	12		T132	16		T115	5
all_values[8]	3407	1			T114	18		T132	14		T115	3
all_values[9]	3583	1			T114	24		T132	14		T115	5
all_values[10]	3564	1			T114	20		T132	21		T115	1
all_values[11]	3564	1			T114	12		T132	26		T115	2
all_values[12]	3572	1			T114	15		T132	22		T115	4
all_values[13]	3599	1			T114	19		T132	24		T115	4
all_values[14]	3610	1			T114	16		T132	21		T115	3
all_values[15]	3357	1			T114	16		T132	12		T115	3
all_values[16]	3412	1			T114	22		T132	17		T115	3
all_values[17]	3555	1			T114	18		T132	15		T115	4
all_values[18]	3551	1			T114	19		T132	19		T115	7
all_values[19]	3528	1			T114	17		T132	16		T115	3
all_values[20]	3513	1			T114	19		T132	17		T115	3
all_values[21]	3529	1			T114	25		T132	20		T115	2
all_values[22]	3516	1			T114	19		T132	20		T115	5
all_values[23]	3479	1			T114	22		T132	23		T115	4
all_values[24]	3536	1			T114	21		T132	18		T115	3
all_values[25]	3443	1			T114	21		T132	16		T115	3
all_values[26]	3563	1			T114	21		T132	13		T115	4
all_values[27]	3639	1			T114	18		T132	22		T115	4
all_values[28]	3511	1			T114	19		T132	19		T115	4
all_values[29]	3462	1			T114	17		T132	16		T115	5
all_values[30]	3637	1			T114	24		T132	18		T115	1
all_values[31]	3503	1			T114	17		T132	20		T115	3
all_values[32]	3480	1			T114	24		T132	17		T115	5
all_values[33]	3486	1			T114	18		T132	14		T115	6
all_values[34]	3461	1			T114	12		T132	16		T115	5
all_values[35]	3429	1			T114	22		T132	15		T115	3
all_values[36]	3456	1			T114	18		T132	16		T115	2
all_values[37]	3463	1			T114	14		T132	19		T115	3
all_values[38]	3492	1			T114	15		T132	16		T115	2
all_values[39]	3504	1			T114	11		T132	25		T414	8
all_values[40]	3478	1			T114	20		T132	19		T115	3
all_values[41]	3463	1			T114	11		T132	20		T115	1
all_values[42]	3424	1			T114	22		T132	17		T115	1
all_values[43]	3400	1			T114	15		T132	13		T115	7
all_values[44]	3401	1			T114	23		T132	23		T115	2
all_values[45]	3591	1			T114	18		T132	21		T115	2
all_values[46]	3532	1			T114	17		T132	22		T115	9
all_values[47]	3471	1			T114	12		T132	26		T115	4
all_values[48]	3479	1			T114	21		T132	18		T115	2
all_values[49]	3462	1			T114	21		T132	19		T115	8
all_values[50]	3520	1			T114	24		T132	23		T115	5
all_values[51]	3501	1			T114	10		T132	15		T115	2
all_values[52]	3485	1			T114	18		T132	17		T115	6
all_values[53]	3548	1			T114	26		T132	19		T115	3
all_values[54]	3538	1			T114	24		T132	23		T115	3
all_values[55]	3516	1			T114	16		T132	16		T115	3
all_values[56]	3539	1			T114	12		T132	19		T115	6
all_values[57]	3472	1			T114	24		T132	15		T115	3
all_values[58]	3495	1			T114	19		T132	12		T115	3
all_values[59]	3531	1			T114	20		T132	23		T115	3
all_values[60]	3523	1			T114	19		T132	20		T115	4
all_values[61]	3565	1			T114	14		T132	19		T115	1
all_values[62]	3467	1			T114	20		T132	21		T115	4
all_values[63]	3475	1			T114	18		T132	19		T115	3