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 LINE       35389
 EXPRESSION (addr_hit[551] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT29,T60,T313
101CoveredT411,T359,T410
110CoveredT585,T506,T448
111CoveredT13,T14,T379

 LINE       35391
 EXPRESSION (addr_hit[552] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT29,T60,T313
101CoveredT114,T115,T356
110CoveredT502,T530,T535
111CoveredT11,T12,T13

 LINE       35393
 EXPRESSION (addr_hit[553] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT29,T60,T313
101CoveredT114,T377,T359
110CoveredT435,T535,T539
111CoveredT13,T14,T379

 LINE       35395
 EXPRESSION (addr_hit[554] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT29,T60,T313
101CoveredT114,T115,T377
110CoveredT500,T546,T703
111CoveredT13,T14,T126

 LINE       35397
 EXPRESSION (addr_hit[555] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT29,T60,T313
101CoveredT313,T114,T115
110CoveredT459,T482,T477
111CoveredT356,T13,T14

 LINE       35399
 EXPRESSION (addr_hit[556] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT29,T60,T313
101CoveredT115,T377,T356
110CoveredT430,T459,T502
111CoveredT13,T14,T379

 LINE       35401
 EXPRESSION (addr_hit[557] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT29,T60,T313
101CoveredT114,T356,T413
110CoveredT449,T452,T435
111CoveredT13,T14,T126

 LINE       35403
 EXPRESSION (addr_hit[558] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT29,T60,T313
101CoveredT358,T377,T410
110CoveredT446,T521,T441
111CoveredT13,T14,T126

 LINE       35405
 EXPRESSION (addr_hit[559] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT29,T60,T313
101CoveredT29,T413,T359
110CoveredT639,T704,T513
111CoveredT410,T9,T13

 LINE       35408
 EXPRESSION (addr_hit[560] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT29,T60,T313
101CoveredT314,T131,T114
110CoveredT438,T600,T469
111CoveredT13,T14,T379

 LINE       35411
 EXPRESSION (addr_hit[561] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT29,T60,T313
101CoveredT61,T188,T114
110CoveredT356,T509,T501
111CoveredT13,T14,T126

 LINE       35414
 EXPRESSION (addr_hit[562] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT29,T60,T313
101CoveredT114,T115,T357
110CoveredT356,T558,T502
111CoveredT13,T14,T126

 LINE       35417
 EXPRESSION (addr_hit[563] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT29,T60,T313
101CoveredT29,T30,T114
110CoveredT464,T442,T434
111CoveredT8,T13,T14

 LINE       35420
 EXPRESSION (addr_hit[564] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT29,T60,T313
101CoveredT114,T115,T357
110CoveredT535,T689,T705
111CoveredT13,T14,T126

 LINE       35423
 EXPRESSION (addr_hit[565] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT29,T60,T313
101CoveredT114,T413,T411
110CoveredT449,T453,T435
111CoveredT10,T13,T14

 LINE       35426
 EXPRESSION (addr_hit[566] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT29,T60,T313
101CoveredT114,T115,T357
110CoveredT508,T482,T434
111CoveredT13,T14,T126

 LINE       35429
 EXPRESSION (addr_hit[567] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT29,T60,T313
101CoveredT358,T413,T359
110CoveredT446,T541,T435
111CoveredT356,T9,T13

 LINE       38839
 EXPRESSION (reg_busy_sel | shadow_busy)
             ------1-----   -----2-----
-1--2-StatusTests
00CoveredT29,T30,T31
01Unreachable
10CoveredT8,T9,T10
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